JPH08204341A - Printed board built-in type bypass capacitor - Google Patents

Printed board built-in type bypass capacitor

Info

Publication number
JPH08204341A
JPH08204341A JP7011343A JP1134395A JPH08204341A JP H08204341 A JPH08204341 A JP H08204341A JP 7011343 A JP7011343 A JP 7011343A JP 1134395 A JP1134395 A JP 1134395A JP H08204341 A JPH08204341 A JP H08204341A
Authority
JP
Japan
Prior art keywords
bypass capacitor
circuit board
printed circuit
pattern
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7011343A
Other languages
Japanese (ja)
Inventor
Manabu Kawate
学 川手
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7011343A priority Critical patent/JPH08204341A/en
Publication of JPH08204341A publication Critical patent/JPH08204341A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE: To reduce the inductance of a pattern, to effectively ground it and to easily wire a signal pattern by incorporating a bypass capacitor in a printed board. CONSTITUTION: A dielectric 30 is provided between the pattern 3 of the power terminal 2 of an IC 1 mounted on the surface layer of a multilayer printed board and the inner layer ground pattern 11 of the printed board. Thus, the inductance of the pattern is reduced to suppress high frequency noise and necessary signal. In addition, the bypass capacitor of surface mounting is eliminated and the wiring of the signal pattern is facilitated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はプリント基板内蔵型バイ
パスコンデンサに関して特にマイクロ波帯のICのプリ
ント基板内蔵型バイパスコンデンサに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bypass capacitor with a built-in printed circuit board, and more particularly to a bypass capacitor with a built-in printed circuit board for microwave band ICs.

【0002】[0002]

【従来の技術】従来、プリント基板にICを実装する
際、バイパスコンデンサの挿入を施している。すなわ
ち、ICの電源端子に雑音及び不要信号の混入を抑制す
る目的でバイパスコンデンサの挿入が必要となる。ま
た、帰還によるICの異常発振の発生を阻止する目的で
もバイパスコンデンサの挿入が必要である。
2. Description of the Related Art Conventionally, when mounting an IC on a printed circuit board, a bypass capacitor is inserted. That is, it is necessary to insert a bypass capacitor in the power supply terminal of the IC for the purpose of suppressing the mixing of noise and unnecessary signals. Further, it is necessary to insert a bypass capacitor for the purpose of preventing the abnormal oscillation of the IC due to the feedback.

【0003】図5は従来のバイパスコンデンサの実装方
法の一例を示す斜視図である。本図のプリント基板4上
において、IC1の電源端子部2に電源パターン3が接
続されている。また、該電源パターン3にバイパスコン
デンサとして使用されるチップコンデンサ20が接続さ
れ、該バイパスコンデンサの相反する端子は接地パター
ン5に接続されている。
FIG. 5 is a perspective view showing an example of a conventional bypass capacitor mounting method. A power supply pattern 3 is connected to the power supply terminal portion 2 of the IC 1 on the printed circuit board 4 of this figure. Further, a chip capacitor 20 used as a bypass capacitor is connected to the power supply pattern 3, and opposite terminals of the bypass capacitor are connected to the ground pattern 5.

【0004】電源パターン3よりIC1に電源が供給さ
れる際、直流成分以外に雑音及び不要信号である交流成
分が混在している。前記交流成分はバイパスコンデンサ
20を通過し、接地パターン5に解放されるため、IC
1の電源には、直流成分のみが供給される。
When power is supplied to the IC 1 from the power supply pattern 3, noise and an AC component which is an unnecessary signal are mixed in addition to the DC component. Since the AC component passes through the bypass capacitor 20 and is released to the ground pattern 5, the IC
Only the DC component is supplied to the power supply No. 1.

【0005】図3では、プリント基板上にバイパスコン
デンサ20が配置されているため、昨今の高密度実装化
に対して実装面積を占有し、実装部品点数の増加をもた
らす等の問題を有していた。この問題を解決するため例
えば、特開平01−155643号公報に示されるセラ
ミック基板内蔵型バイパスコンデンサの実装方法が知ら
れているが、該実装方法は、集積回路のセラミックパッ
ケージ材質内にバイパスコンデンサを形成する方法であ
り、既存の集積回路には適用できない。
In FIG. 3, since the bypass capacitor 20 is arranged on the printed circuit board, it has a problem that it occupies a mounting area and increases the number of mounted parts in view of recent high-density mounting. It was In order to solve this problem, for example, a mounting method of a bypass capacitor with a built-in ceramic substrate disclosed in Japanese Patent Laid-Open No. 01-155643 is known. In this mounting method, a bypass capacitor is provided in a ceramic package material of an integrated circuit. It is a method of forming and cannot be applied to existing integrated circuits.

【0006】[0006]

【発明が解決しようとする課題】以上説明した実装面
積,実装部品点数の問題以外に、電気的問題を有してい
る。すなわち、従来の実装方法では、ICの電源端子と
バイパスコンデンサとの距離が必ず発生する。この間を
パターンで接続する際、前記の距離に比例し、電源パタ
ーンにインダクタンスが発生するため、インダクタンス
が無視できる周波数では、バイパスコンデンサとして作
用するものの、高周波帯、特にマイクロ波帯以上の高周
波では、雑音及び不要信号の抑制が不充分となってく
る。また、該インダクタンスを極力小さく実装する場
合、ICとバイパスコンデンサが隣り合せに実装され、
該ICの電源以外の信号パターンを複雑化する事が考え
られる。以上説明したごとく本発明は、実装上の問題と
高周波特性を劣化させる電気的問題にかんがみてなされ
たものであり、電源パターンによりインダクタンスを確
実になくしたうえ、他の信号パターンの邪魔にならない
バイパスコンデンサの実装方法の提供を目的とする。
In addition to the mounting area and the number of mounting components described above, there are electrical problems. That is, in the conventional mounting method, the distance between the power supply terminal of the IC and the bypass capacitor is always generated. When connecting with a pattern between these, since the inductance is generated in the power supply pattern in proportion to the above distance, at a frequency where the inductance can be ignored, it acts as a bypass capacitor, but in a high frequency band, particularly in a microwave band or higher, Noise and unnecessary signals are not sufficiently suppressed. When mounting the inductance as small as possible, the IC and the bypass capacitor are mounted side by side,
It is conceivable to complicate the signal pattern other than the power source of the IC. As described above, the present invention has been made in view of the mounting problem and the electrical problem that deteriorates the high frequency characteristics. In addition to reliably eliminating the inductance by the power supply pattern, the bypass that does not disturb other signal patterns is provided. It is intended to provide a method for mounting a capacitor.

【0007】[0007]

【課題を解決するための手段】前記目的を達成するため
に、本発明のプリント基板内蔵型バイパスコンデンサ表
面実装されたICの電源端子のパターンと多層プリント
基板の内層接地(GND)パターンとの間に、誘電体を
備える構成を有している。
In order to achieve the above object, a power supply terminal pattern of a surface mounted IC of a bypass capacitor with a built-in printed circuit board according to the present invention and an inner layer ground (GND) pattern of a multilayer printed circuit board are provided. In addition, it has a structure including a dielectric.

【0008】[0008]

【実施例】次に、本発明の実装方法について図面を用い
て説明する。図1は本発明のバイパスコンデンサの実装
方法を示す斜視図であり、図2は図1のA−A′線に係
るプリント基板の内部構成を示す断面図である。
Next, a mounting method of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view showing a mounting method of a bypass capacitor according to the present invention, and FIG. 2 is a sectional view showing an internal structure of a printed circuit board taken along the line AA ′ in FIG.

【0009】図1及び図2において発明は、第1層6と
第2層7からなる多層プリント基板8の表層部と、第1
層6との間にブラインドヴィアスルーホール型の誘電体
30を備えている。
In FIGS. 1 and 2, the invention is based on a surface layer portion of a multilayer printed circuit board 8 comprising a first layer 6 and a second layer 7, and a first layer.
A blind via through-hole type dielectric 30 is provided between the layer 6 and the layer 6.

【0010】前記誘電体30には、上下を覆うように狭
むプリントパターンが設けられている。基板表層部パタ
ーン3は表面実装型IC1の電源端子2が実装される電
源パターン3であり、該誘電体30の上部と接してい
る。このとき、誘電体30と電源パターン30とが接続
するよう多層プリント基板8の表層部の絶縁部9を誘電
体30の上部形状で切り欠いている。
The dielectric 30 is provided with a print pattern which is narrowed so as to cover the top and bottom. The board surface layer pattern 3 is a power supply pattern 3 on which the power supply terminal 2 of the surface mount type IC 1 is mounted, and is in contact with the upper portion of the dielectric 30. At this time, the insulating portion 9 in the surface layer portion of the multilayer printed circuit board 8 is cut out in the upper shape of the dielectric 30 so that the dielectric 30 and the power supply pattern 30 are connected.

【0011】これによって表面実装型IC1の電源端子
2と、設置層11とは、多層プリント基板内蔵型誘電体
30(バイパスコンデンサ)によって最短距離で接続さ
れる。
As a result, the power supply terminal 2 of the surface mount type IC 1 and the installation layer 11 are connected at the shortest distance by the dielectric 30 (bypass capacitor) with a built-in multilayer printed circuit board.

【0012】以上説明した多層プリント板8は、簡単化
するため2層で示したがこれに限定されるものでないの
は勿論である。すなわち、多層プリント基板8の表面層
と表面層に最も近い内層にブランドヴィアスルーホール
型の誘電体を設ければ、他の複数の内層は通常の多層プ
リント基板と全く同等のものでよい。また、表面層を裏
面層に変えても同様に構成できるのは当然である。
The multi-layer printed board 8 described above is shown as two layers for simplification, but it is needless to say that it is not limited to this. That is, if a brand via through-hole type dielectric is provided on the surface layer of the multilayer printed circuit board 8 and the inner layer closest to the surface layer, the other plurality of inner layers may be exactly the same as a normal multilayer printed circuit board. In addition, it goes without saying that the same structure can be obtained by changing the surface layer to the back surface layer.

【0013】さらに、本実施例ではブランドヴィアスル
ーホール型の誘電体を用いたが、これに限定されるもの
でない。
Further, although the brand-via through-hole type dielectric is used in this embodiment, it is not limited to this.

【0014】例えば、図3に示すごとくプリント基板8
の第1層全体を誘電体層10とし、電源パターン3と接
続すべき部分において絶縁部9を切り欠いている。ま
た、誘電体層10は接地層11と接続して接地されてバ
イパスコンデンサを形成している。
For example, as shown in FIG. 3, a printed circuit board 8
The entire first layer is a dielectric layer 10, and the insulating portion 9 is cut out at the portion to be connected to the power supply pattern 3. The dielectric layer 10 is connected to the ground layer 11 and grounded to form a bypass capacitor.

【0015】[0015]

【発明の効果】以上説明したように本発明はICの電源
端子とバイパスコンデンサとの距離を最短にすることに
よって電源パターンによるインダクタンスを減少したの
でマイクロ波帯以上の周波数の雑音や、不要信号を抑制
するという効果を有する。
As described above, according to the present invention, the inductance due to the power source pattern is reduced by minimizing the distance between the power source terminal of the IC and the bypass capacitor, so that noise of frequencies above the microwave band and unnecessary signals are eliminated. It has the effect of suppressing.

【0016】加えてバイパスコンデンサをプリント基板
に内蔵することにより、電源以外の信号パターンの配線
を容易にできるという効果も有する。
In addition, by incorporating the bypass capacitor in the printed circuit board, there is also an effect that wiring of signal patterns other than the power source can be facilitated.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のバイパスコンデンサの第1の実施例を
示す斜視図である。
FIG. 1 is a perspective view showing a first embodiment of a bypass capacitor of the present invention.

【図2】図1中に示すプリント基板の内部構成を示す断
面図である。
FIG. 2 is a cross-sectional view showing an internal configuration of the printed circuit board shown in FIG.

【図3】本発明のバイパスコンデンサの第2の実施例を
示す斜視図である。
FIG. 3 is a perspective view showing a second embodiment of the bypass capacitor of the present invention.

【図4】図3中に示すプリント基板の内部構成を示す断
面図である。
FIG. 4 is a cross-sectional view showing an internal configuration of the printed circuit board shown in FIG.

【図5】従来のバイパスコンデンサの構成を示す斜視図
である。
FIG. 5 is a perspective view showing a configuration of a conventional bypass capacitor.

【符号の説明】[Explanation of symbols]

1 表面実装型IC 2 ICの電源端子 3 電源パターン 4 プリント基板 5 接地パターン 6 第1層プリント基板 7 第2層プリント基板 8 多層プリント基板 9 絶縁部 10 誘電体層 11 接地層 20 チップコンデンサ 30 誘電体 1 Surface Mount Type IC 2 Power Supply Terminal of IC 3 Power Supply Pattern 4 Printed Circuit Board 5 Ground Pattern 6 First Layer Printed Circuit Board 7 Second Layer Printed Circuit Board 8 Multilayer Printed Circuit Board 9 Insulating Part 10 Dielectric Layer 11 Ground Layer 20 Chip Capacitor 30 Dielectric body

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 多層プリント基板の内部に誘電体を設
け、前記誘電体を前記多層プリント基板表面の電源パタ
ーンと前記多層プリント基坂内部の接地パターンに接続
したことを特徴とするプリント基板内蔵型バイパスコン
デンサ。
1. A printed circuit board built-in type wherein a dielectric is provided inside a multilayer printed circuit board, and the dielectric is connected to a power source pattern on the surface of the multilayer printed circuit board and a ground pattern inside the multilayer printed circuit board. Bypass capacitor.
【請求項2】 前記誘電体は、前記多層プリント基板の
表面層または裏面層と最も近い内層との間のブラインド
ヴィアスルーホール内に形成し、前記ブラインドヴィア
スルーホールの一方は、前記多層プリント基板の電源パ
ターンと接続し、片方は、前記内層の接地パターンに接
続したことを特徴とする請求項1記載のプリント基板内
蔵型バイパスコンデンサ。
2. The dielectric is formed in a blind via through hole between a front surface layer or a back surface layer of the multilayer printed circuit board and a nearest inner layer, and one of the blind via through holes is formed in the multilayer printed circuit board. 2. The bypass capacitor with a built-in printed circuit board according to claim 1, wherein the bypass capacitor is connected to the power supply pattern of the above, and one of them is connected to the ground pattern of the inner layer.
【請求項3】 前記誘電体は、前記多層プリント基板の
内層面に形成したことを特徴とする請求項1記載のプリ
ント基板内蔵型バイパスコンデンサ。
3. The printed circuit board built-in type bypass capacitor according to claim 1, wherein the dielectric is formed on an inner layer surface of the multilayer printed circuit board.
JP7011343A 1995-01-27 1995-01-27 Printed board built-in type bypass capacitor Pending JPH08204341A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7011343A JPH08204341A (en) 1995-01-27 1995-01-27 Printed board built-in type bypass capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7011343A JPH08204341A (en) 1995-01-27 1995-01-27 Printed board built-in type bypass capacitor

Publications (1)

Publication Number Publication Date
JPH08204341A true JPH08204341A (en) 1996-08-09

Family

ID=11775396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7011343A Pending JPH08204341A (en) 1995-01-27 1995-01-27 Printed board built-in type bypass capacitor

Country Status (1)

Country Link
JP (1) JPH08204341A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001298274A (en) * 2001-03-13 2001-10-26 Matsushita Electric Ind Co Ltd Electronic circuit arrangement
US6704208B2 (en) 2001-10-01 2004-03-09 Victor Company Of Japan, Ltd. Printed circuit board and manufacturing method thereof
JP2007103469A (en) * 2005-09-30 2007-04-19 Aica Kogyo Co Ltd Built-in capacitor forming structure of multilayered printed circuit board

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6336078B2 (en) * 1979-08-17 1988-07-19 Nippon Electric Co
JPH0513961A (en) * 1991-06-28 1993-01-22 Toshiba Corp Multilayer wiring board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6336078B2 (en) * 1979-08-17 1988-07-19 Nippon Electric Co
JPH0513961A (en) * 1991-06-28 1993-01-22 Toshiba Corp Multilayer wiring board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001298274A (en) * 2001-03-13 2001-10-26 Matsushita Electric Ind Co Ltd Electronic circuit arrangement
US6704208B2 (en) 2001-10-01 2004-03-09 Victor Company Of Japan, Ltd. Printed circuit board and manufacturing method thereof
JP2007103469A (en) * 2005-09-30 2007-04-19 Aica Kogyo Co Ltd Built-in capacitor forming structure of multilayered printed circuit board

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