JPH05136321A - Lead frame and semiconductor device using same - Google Patents

Lead frame and semiconductor device using same

Info

Publication number
JPH05136321A
JPH05136321A JP29336191A JP29336191A JPH05136321A JP H05136321 A JPH05136321 A JP H05136321A JP 29336191 A JP29336191 A JP 29336191A JP 29336191 A JP29336191 A JP 29336191A JP H05136321 A JPH05136321 A JP H05136321A
Authority
JP
Japan
Prior art keywords
pad
die pad
semiconductor chip
hole
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29336191A
Other languages
Japanese (ja)
Inventor
Atsuo Nouzumi
厚生 能隅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP29336191A priority Critical patent/JPH05136321A/en
Publication of JPH05136321A publication Critical patent/JPH05136321A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

PURPOSE:To make the close contact property of the title lead frame with a sealing resin good by a method wherein a through hole is made in a die pad in a semiconductor-chip mounting region; it is covered with a second pad and a semiconductor chip is mounted on it. CONSTITUTION:A die pad is formed of a two-layer structure composed of the following: a first pad 11a provided with a through hole in a region including a semiconductor-chip mounting region; and a second pad 11b composed of an insulating film which is pasted on its upper layer in such a way that the through hole H in the semiconductor-chip mounting region is covered. A semiconductor chip is mounted on the surface of the second die pad 11b of the die pad; it is sealed with a resin. Consequently, the second die pad 11b is used as the semiconductor-chip mounting region. As a result, in a resin sealing operation, the resin is filled into the through hole H and hardened. Thereby, the close contact property of the title lead frame with the sealing resin is made good.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に係り、特
に、樹脂封止型半導体装置の封止樹脂との密着性の強化
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to enhancement of adhesion of a resin-sealed semiconductor device to a sealing resin.

【0002】[0002]

【従来の技術】IC、LSI等の半導体装置の実装に際
して用いられるリ―ドフレ―ムは、鉄系あるいは銅系等
の金属材料からなる板状体をプレス加工又はエッチング
により所望のパタ―ンに成形することによって形成され
る。
2. Description of the Related Art A lead frame used for mounting a semiconductor device such as an IC and an LSI has a plate-like body made of a metal material such as an iron-based material or a copper-based material, which is formed into a desired pattern by pressing or etching. It is formed by molding.

【0003】通常、リ―ドフレ―ム1は図4に示す如
く、半導体集積回路チップ(以下半導体チップ)を搭載
するダイパッド11と、ダイパッドを取り囲むように配
設せしめられた複数のインナ―リ―ド12とインナ―リ
―ド12を一体的に連結するタイバ―13と、各インナ
―リ―ドに連結せしめられタイバ―の外側に伸張するア
ウタ―リ―ド14と、タイバ―13を両サイドから支持
するサイドバ―15,16と、ダイパッド11を支持す
るサポ―トバ―17とから構成されている。
Usually, the lead frame 1 is, as shown in FIG. 4, a die pad 11 on which a semiconductor integrated circuit chip (hereinafter referred to as a semiconductor chip) is mounted, and a plurality of inner reels arranged so as to surround the die pad. The tie bar 13 that integrally connects the inner lead 12 and the inner lead 12, the outer lead 14 that is connected to each inner lead and extends outside the tie bar, and the tie bar 13 It is composed of side bars 15 and 16 which are supported from the side, and a support bar 17 which supports the die pad 11.

【0004】このようなリ―ドフレ―ムを用いて実装せ
しめられる半導体装置は図5に示す如くであり、リ―ド
フレ―ム1のダイパッド11上に、半導体チップ2を搭
載し、この半導体チップのボンディングパッドとリ―ド
フレ―ムのインナ―リ―ド12とを金線あるいはアルミ
線のボンディングワイヤ3によって結線し、更にこれら
を樹脂やセラミック等の封止材料4で封止した後、タイ
バ―やサイドバ―を切断し、アウタ―リ―ドを所望の形
状に折り曲げて完成せしめられる。
A semiconductor device mounted by using such a lead frame is as shown in FIG. 5, in which the semiconductor chip 2 is mounted on the die pad 11 of the lead frame 1, and this semiconductor chip is mounted. Of the lead frame and the inner lead 12 of the lead frame are connected by a bonding wire 3 of a gold wire or an aluminum wire, which is further sealed with a sealing material 4 such as resin or ceramic, and then the tie bar. -The side bar is cut and the outer lead is bent into the desired shape to complete.

【0005】近年、半導体素子の大型化に伴いそれを支
承するダイパッドも大型になってきている。
[0005] In recent years, with the increase in size of semiconductor devices, the size of the die pad that supports them has also increased.

【0006】従って、樹脂封止領域に対するパッドの占
有率が大きくなり、パッケージ領域内での樹脂の厚さは
薄くなる傾向にあり、封止樹脂とダイパッドとの熱膨張
率の差によりクラックが発生し易く、これが半導体装置
の信頼性低下の原因となっていた。
Therefore, the pad occupancy rate in the resin encapsulation area becomes large, and the thickness of the resin in the package area tends to be thin, and cracks are generated due to the difference in thermal expansion coefficient between the encapsulation resin and the die pad. It is easy to do so, and this has been a cause of deterioration in reliability of the semiconductor device.

【0007】従来、このようなクラック発生防止対策と
してダイパッドの裏面に、パンチングあるいはエッチン
グにより小孔あるいは凹部を形成するいわゆるディンプ
ル加工を施しておき、樹脂をこの小孔あるいは凹部にま
で流し込むことによって、ダイパッドの裏面に確実に樹
脂を固定するという方法がとられている。
Conventionally, as a measure for preventing such cracks, the back surface of the die pad is subjected to so-called dimple processing for forming small holes or recesses by punching or etching, and resin is poured into these small holes or recesses. A method of reliably fixing the resin on the back surface of the die pad is used.

【0008】しかしながら、この方法では、ダイパッド
の表面に影響を与えるため、あまり深い加工をおこなう
ことは出来ず、十分な効果を得ることは困難であった。
However, in this method, since the surface of the die pad is affected, it is not possible to perform deep processing, and it is difficult to obtain a sufficient effect.

【0009】また、貫通孔を形成するとチップ取り付け
用の導体ペーストや半田が裏面まで流れ出し、短絡の原
因となることもあった。
Further, when the through hole is formed, the conductor paste or solder for mounting the chip may flow out to the back surface, which may cause a short circuit.

【0010】[0010]

【発明が解決しようとする課題】このように、高集積化
に際し、封止樹脂との密着性の向上のためにダイパッド
の裏面に、ディンプル加工を行う方法は、ダイパッドの
表面に影響を与えるため、調整が極めて困難であり、十
分な効果を得ることはできなかった。
As described above, the method of performing dimple processing on the back surface of the die pad in order to improve the adhesion with the encapsulating resin at the time of high integration has an influence on the surface of the die pad. However, adjustment was extremely difficult, and a sufficient effect could not be obtained.

【0011】本発明は、前記実情に鑑みてなされたもの
で、高集積化に際し、封止樹脂との密着性が高く、信頼
性の高い半導体装置を提供することを目的とする。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a highly reliable semiconductor device which has high adhesion to a sealing resin when highly integrated.

【0012】[0012]

【課題を解決するための手段】そこで本発明のリードフ
レームでは、ダイパッドを、半導体チップ搭載領域を含
む領域に貫通孔を有する第1のパッドと、この上層に少
なくとも半導体チップ搭載領域上の前記貫通孔を覆うよ
うに貼着された絶縁性フィルムからなる第2のパッドと
の2層構造で構成している。
Therefore, in the lead frame of the present invention, the die pad is composed of a first pad having a through hole in a region including a semiconductor chip mounting region, and the through pad on at least the semiconductor chip mounting region in the upper layer. It has a two-layer structure with a second pad made of an insulating film attached so as to cover the hole.

【0013】また本発明の半導体装置では、半導体チッ
プ搭載領域を含む領域に貫通孔を有する第1のパッド
と、この上層に少なくとも半導体チップ搭載領域上の前
記貫通孔を覆うように貼着された絶縁性フィルムからな
る第2のパッドとの2層構造で構成されたダイパッドの
第2のパッド表面に半導体チップを搭載し、樹脂によっ
て封止したことを特徴とする。
Further, in the semiconductor device of the present invention, a first pad having a through hole in a region including a semiconductor chip mounting region, and an upper layer attached to cover at least the through hole in the semiconductor chip mounting region. A semiconductor chip is mounted on the second pad surface of the die pad having a two-layer structure with the second pad made of an insulating film, and the die pad is sealed with resin.

【0014】[0014]

【作用】上記構造によれば、貫通孔を有するダイパッド
上に積層された絶縁性フィルムからなる第2のパッド
が、半導体チップ搭載領域となるため、樹脂封止に際し
この貫通孔内にも樹脂が充填され、硬化するため、樹脂
との密着性が極めて良好となる。半導体チップは第2の
パッド上に搭載されるため、接着剤が貫通孔に流れ出す
こともなく、半導体チップ搭載部の表面はいかなる影響
を受けることもない。さらに、貫通孔を有するパッドを
インナーリード先端のコイニングと同時にコイニングす
ることにより薄くする等の方法により、全体の厚さを薄
くすることができる。またこのとき、絶縁性フィルムが
貼着されているため機械的強度は維持することができ
る。
According to the above structure, the second pad made of the insulating film laminated on the die pad having the through hole serves as the semiconductor chip mounting area. Since it is filled and cured, the adhesion to the resin becomes extremely good. Since the semiconductor chip is mounted on the second pad, the adhesive does not flow out into the through hole and the surface of the semiconductor chip mounting portion is not affected in any way. Further, the overall thickness can be reduced by a method such as coining the pad having the through hole at the same time as coining the tip of the inner lead so as to reduce the thickness. At this time, since the insulating film is attached, the mechanical strength can be maintained.

【0015】さらに通常のダイパッドに絶縁性フィルム
を貼着すれば良いため製造も容易である。
Further, since it is sufficient to attach an insulating film to a usual die pad, the manufacturing is easy.

【0016】また、貫通孔は半導体チップ搭載領域の裏
面にも形成されているため、半導体チップ搭載領域の外
側に形成された場合に比べ大幅に密着性が向上する。
Further, since the through hole is also formed on the back surface of the semiconductor chip mounting area, the adhesion is significantly improved as compared with the case where it is formed outside the semiconductor chip mounting area.

【0017】[0017]

【実施例】以下、本発明の実施例について、図面を参照
しつつ詳細に説明する。
Embodiments of the present invention will now be described in detail with reference to the drawings.

【0018】本発明実施例のリ―ドフレ―ムは、図1に
示す如く、半導体チップ搭載領域を含む第1のダイパッ
ド11aにスルーホールHを形成するとともにこの表面
にポリイミドフィルムからなる第2のダイパッド11b
を貼着したことを特徴とするもので、樹脂をこの小孔に
まで流し込むことができるようになっている。他部につ
いては図4に示したものと同様の構造を有している。
As shown in FIG. 1, in the lead frame of the embodiment of the present invention, a through hole H is formed in the first die pad 11a including the semiconductor chip mounting area and a second polyimide film is formed on the surface. Die pad 11b
This is characterized in that the resin is attached, and the resin can be poured into the small holes. Other parts have the same structure as that shown in FIG.

【0019】次に、このリ−ドフレ−ムの製造方法およ
びこれを用いた半導体装置の製造方法について説明す
る。
Next, a method for manufacturing this lead frame and a method for manufacturing a semiconductor device using the same will be described.

【0020】まず、図2(a) に示すように、帯状材料を
用いて、通常の如くプレス加工により、第1のダイパッ
ド11aと、第1のダイパッド11aを取り囲むように
配設せしめられた複数のインナ―リ―ド12とインナ―
リ―ド12を一体的に連結するタイバ―13と、各イン
ナ―リ―ドに連結せしめられタイバ―の外側に伸張する
アウタ―リ―ド14と、タイバ―13を両サイドから支
持するサイドバ―15,16と、ダイパッド11を支持
するサポ―トバ―17とからなるリードフレームを形成
する。なお、インナーリード先端と第1のダイパッド1
1aとは打ち抜きに先立ち、コイニングにより薄く形成
される。そして第1のダイパッドの打ち抜きと同時にス
ルーホールHも打ち抜かれる。
First, as shown in FIG. 2 (a), a band-shaped material is used to press the die in the usual manner. Inner lead 12 and inner
A tie bar 13 that integrally connects the leads 12, an outer lead 14 that is connected to each inner lead and extends outside the tie bar, and a side bar that supports the tie bar 13 from both sides. A lead frame composed of -15 and 16 and a support bar 17 for supporting the die pad 11 is formed. The tip of the inner lead and the first die pad 1
Prior to punching, 1a is thinly formed by coining. Then, the through hole H is also punched at the same time as the punching of the first die pad.

【0021】次いで、図2(b) に示すように、第1のダ
イパッドとほぼ同じ形状にポリイミドフィルムをカッテ
ィングし、第2のダイパッド11bを形成する。
Next, as shown in FIG. 2B, a polyimide film is cut into a shape substantially the same as the first die pad to form a second die pad 11b.

【0022】この後さらに必要に応じてメッキ工程等を
経て、リードフレームを形成した後、図2(c) に示すよ
うに、このリードフレームの第1のダイパッド11aの
表面にポリイミド樹脂からなる第2のダイパッド11b
を貼着する。
After this, a lead frame is further formed through a plating process or the like, if necessary, and then, as shown in FIG. 2 (c), the first die pad 11a of the lead frame is covered with a polyimide resin layer. 2 die pad 11b
Affix.

【0023】そして、素子チップ2の搭載、ワイヤボン
ディング、樹脂封止などの工程を経て図2(d) に示すよ
うに半導体装置が完成する。3はワイヤ、4は樹脂パッ
ケージである。
Then, the semiconductor device is completed as shown in FIG. 2D through steps such as mounting of the element chip 2, wire bonding, and resin sealing. 3 is a wire and 4 is a resin package.

【0024】本発明によれば、樹脂封止に際して、スル
ーホール内にも樹脂が充填されて硬化するため、極めて
密着性は良好となる。
According to the present invention, when the resin is sealed, the resin is filled in the through holes and hardened, so that the adhesion is extremely good.

【0025】また、第2のダイパッドの存在により、半
導体チップを搭載する際に接着剤が流れ出すこともな
く、第1のダイパッド裏面に影響を与えるおそれもな
く、信頼性が向上する。
Further, due to the presence of the second die pad, the adhesive does not flow out when the semiconductor chip is mounted, there is no fear of affecting the back surface of the first die pad, and the reliability is improved.

【0026】なお、前記実施例では、第1のダイパッド
全面に円形のスルーホールを多数個形成したが、図3
(a) または(b) に示すように長溝型のスルーホールH1
とするなど,適宜変形可能である。図3(b) に示すよう
にダイパッドの対角線上に沿ってスルーホールを形成し
ているため応力の分散を容易にすることができる。
In the above embodiment, a large number of circular through holes are formed on the entire surface of the first die pad.
As shown in (a) or (b), long groove type through hole H1
It can be modified as appropriate. As shown in FIG. 3B, since the through holes are formed along the diagonal lines of the die pad, the stress can be easily dispersed.

【0027】さらに第2のパッドはチップ搭載領域下の
スルーホールを覆うように形成されていれば、第1のパ
ッドよりも小さくても良いし、大きくても良い。また、
2層のみならず3層以上のパッドを形成しても良いこと
はいうまでもない。さらに本発明は第1のパッドのチッ
プ搭載領域以外にもスルーホールが形成され、これらが
第2のパッドから露呈するようにしてもよい。
Further, the second pad may be smaller or larger than the first pad as long as it is formed so as to cover the through hole under the chip mounting area. Also,
It goes without saying that not only two layers but also three or more layers of pads may be formed. Further, according to the present invention, through holes may be formed in areas other than the chip mounting area of the first pad, and these may be exposed from the second pad.

【0028】また、前記実施例では、スルーホールはプ
レス加工によって形成したが、エッチングによって形成
してもよい。
Further, in the above-mentioned embodiment, the through hole is formed by pressing, but it may be formed by etching.

【0029】また、前記実施例では第1のパッドはコイ
ニングによって薄く形成したが、必ずしも薄くしなくて
も良い。
Further, although the first pad is formed thin by coining in the above-mentioned embodiment, it is not always necessary to make it thin.

【0030】[0030]

【発明の効果】以上説明してきたように、本発明によれ
ば、半導体チップ搭載領域に相当する領域のダイパッド
裏面にスルーホールを形成し、この上を絶縁性フィルム
からなる第2のダイパッドで覆い、この上に半導体チッ
プを搭載するようにしているため、樹脂封止に際しスル
ーホール内にも樹脂が充填され、硬化するため、樹脂と
の密着性が極めて良好で信頼性の高い半導体装置を得る
ことが可能となる。
As described above, according to the present invention, a through hole is formed on the back surface of the die pad in the area corresponding to the semiconductor chip mounting area, and the through hole is covered with the second die pad made of an insulating film. Since the semiconductor chip is mounted on this, the resin is also filled in the through holes when the resin is sealed and the resin is hardened, so that a highly reliable and highly reliable semiconductor device can be obtained. It becomes possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例のリードフレームを示す図FIG. 1 is a diagram showing a lead frame according to an embodiment of the present invention.

【図2】同リードフレームを用いた半導体装置の製造工
程図
FIG. 2 is a manufacturing process diagram of a semiconductor device using the lead frame.

【図3】本発明の他の実施例のリードフレームを示す図FIG. 3 is a diagram showing a lead frame according to another embodiment of the present invention.

【図4】従来例のリードフレームを示す図FIG. 4 is a diagram showing a conventional lead frame.

【図5】従来例の半導体装置を示す図FIG. 5 is a diagram showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 リードフレーム 2 半導体チップ 3 ワイヤ 4 樹脂パッケージ 11 ダイパッド 12 インナ−リ−ド 13 ダムバー 14 アウターリード 15 サイドバー 16 サイドバー 17 サポートバー H スルーホール 11a 第1のダイパッド 11b 第2のダイパッド 1 Lead Frame 2 Semiconductor Chip 3 Wire 4 Resin Package 11 Die Pad 12 Inner Lead 13 Dam Bar 14 Outer Lead 15 Side Bar 16 Side Bar 17 Support Bar H Through Hole 11a First Die Pad 11b Second Die Pad

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップを搭載するためのダイパッ
ドと、前記パッドから所定の間隔をおいて配列されたイ
ンナーリードと、前記インナーリードに連設されたアウ
ターリードとを有するリードフレームにおいて、 前記ダイパッドが、半導体チップ搭載領域を含む領域に
貫通孔を有する第1のパッドと、この上層に少なくとも
前記半導体チップ搭載領域の前記貫通孔を覆うように貼
着された絶縁性フィルムからなり、この表面が半導体チ
ップ搭載面となるように形成された第2のパッドとから
構成されていることを特徴とするリードフレーム。
1. A lead frame having a die pad for mounting a semiconductor chip, an inner lead arranged at a predetermined distance from the pad, and an outer lead connected to the inner lead, wherein the die pad Is composed of a first pad having a through hole in a region including a semiconductor chip mounting region and an insulating film attached to the upper layer so as to cover at least the through hole of the semiconductor chip mounting region, the surface of which is A lead frame, comprising: a second pad formed to be a semiconductor chip mounting surface.
【請求項2】 半導体チップ搭載領域を含む領域に貫通
孔を有する第1のパッドとこの上層に少なくとも前記半
導体チップ搭載領域の前記貫通孔を覆うように貼着され
た絶縁性フィルムからなる第2のパッドとから構成さ
れ、半導体チップを搭載するためのダイパッドと、 前記パッドから所定の間隔をおいて配列されたインナー
リードと、前記インナーリードに連設されたアウターリ
ードとを有するリードフレームと、 前記第2のパッド上に搭載された半導体チップとを具備
し、 前記ダイパッドおよび前記半導体チップを覆う封止樹脂
とを含むことを特徴とする半導体装置。
2. A second pad comprising a first pad having a through hole in a region including a semiconductor chip mounting region and an insulating film attached to an upper layer of the first pad so as to cover at least the through hole of the semiconductor chip mounting region. A lead frame having a die pad for mounting a semiconductor chip, an inner lead arranged at a predetermined distance from the pad, and an outer lead connected to the inner lead. A semiconductor device, comprising: a semiconductor chip mounted on the second pad; and a sealing resin covering the die pad and the semiconductor chip.
JP29336191A 1991-11-08 1991-11-08 Lead frame and semiconductor device using same Pending JPH05136321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29336191A JPH05136321A (en) 1991-11-08 1991-11-08 Lead frame and semiconductor device using same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29336191A JPH05136321A (en) 1991-11-08 1991-11-08 Lead frame and semiconductor device using same

Publications (1)

Publication Number Publication Date
JPH05136321A true JPH05136321A (en) 1993-06-01

Family

ID=17793798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29336191A Pending JPH05136321A (en) 1991-11-08 1991-11-08 Lead frame and semiconductor device using same

Country Status (1)

Country Link
JP (1) JPH05136321A (en)

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