JPH0513570A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0513570A JPH0513570A JP16486491A JP16486491A JPH0513570A JP H0513570 A JPH0513570 A JP H0513570A JP 16486491 A JP16486491 A JP 16486491A JP 16486491 A JP16486491 A JP 16486491A JP H0513570 A JPH0513570 A JP H0513570A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- scribe line
- different
- semiconductor
- axis direction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Dicing (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に多品種で少量生産に適する半導体装置の製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device which is suitable for small-quantity production of a wide variety of products.
【0002】[0002]
【従来の技術】従来の半導体装置の製造方法において
は、半導体素子が形成されるチップの大きさは、面積に
して1mm2 程度のものから200〜300mm2 程度
の品種のものまであり、1枚の半導体ウェハ(以下単に
ウェハという)上に1つの品種のみx,y方向ともそれ
ぞれ同一間隔のスクライブ線で区画して形成する方法が
主にとられてきた。また、実験や試作に於て、複数品種
の半導体素子を同一基板に形成する事はあるが、この場
合x,y方向のスクライブ線でチップに分割できる様
に、一番大きなチップサイズに統一されていた。しかし
ながらこの方法は不経済であるので量産には適用されて
いない。2. Description of the Related Art In the conventional method of manufacturing a semiconductor device, the size of a chip on which a semiconductor element is formed ranges from about 1 mm 2 in area to about 200 to 300 mm 2 in variety, and one chip A semiconductor wafer (hereinafter, simply referred to as "wafer") has been mainly formed by dividing only one kind of product into scribe lines having the same intervals in the x and y directions. Also, in experiments and prototypes, there are cases where multiple types of semiconductor elements are formed on the same substrate. In this case, they are unified into the largest chip size so that they can be divided into chips by scribe lines in the x and y directions. Was there. However, this method is uneconomical and has not been applied to mass production.
【0003】[0003]
【発明が解決しようとする課題】従来の半導体装置の製
造方法では、ウェハ径が3インチ,4インチの小型ライ
ンで面積にして1mm2 程度の小型チップを製造する場
合、ウェハ当り2000個程度製造されるものが、ウェ
ハの6インチ,8インチと大型化にともない、ウェハ当
り8000〜10000個も製造されることになる。従
ってチップサイズが小さく、かつ少量の半導体装置を製
造する時には、所要や生産能力に関わりなく、このよう
に不必要に大量な半導体装置を製造することになり、在
庫過剰および長期間保存による半導体装置の信頼性低下
をまねくという問題点があった。According to the conventional method of manufacturing a semiconductor device, when a small chip having an area of about 1 mm 2 is manufactured with a small line having a wafer diameter of 3 inches or 4 inches, about 2000 pieces are manufactured per wafer. As the size of the wafer is increased to 6 inches and 8 inches, 8000 to 10000 wafers are manufactured per wafer. Therefore, when manufacturing a small amount of semiconductor device with a small chip size, an unnecessarily large amount of such semiconductor device is manufactured regardless of the required capacity or the production capacity. However, there was a problem in that the reliability of
【0004】[0004]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、1枚の半導体基板上にチップサイズの異なる
品種の半導体素子を間隔の異なるスクライブ線で区分し
て設けるものである。According to the method of manufacturing a semiconductor device of the present invention, semiconductor elements of different types having different chip sizes are provided on one semiconductor substrate by dividing them with scribe lines having different intervals.
【0005】[0005]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図1は本発明の第1の実施例を説明するた
めのウェハの上面図、図2はその工程図である。Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a top view of a wafer for explaining a first embodiment of the present invention, and FIG. 2 is a process drawing thereof.
【0006】不純物拡散や配線形成等の半導体素子形成
工程においては、1枚のマスクにチップサイズの異なる
素子パターンを区別して設けたコンタクト方式用のマス
クを用いるか、または異なる素子パターンを有する複数
の縮小投影露光用のレチクルを用い、図1に示すような
スクライブ線で区画された半導体素子を形成する。すな
わちウェハ1には、オリエンテーションフラット2に平
行で間隔の異なる第1及び第2のX軸方向スクライブ線
X1 ,X2 と、このX軸方向スクライブ線に直交する第
1のY軸方向スクライブ線Y1 とにより区画され、チッ
プ面積がS1 とS2 の2種類の半導体素子を形成する。In a semiconductor element forming process such as impurity diffusion or wiring formation, a contact mask provided by distinguishing element patterns having different chip sizes is used for one mask, or a plurality of elements having different element patterns are used. A reticle for reduction projection exposure is used to form a semiconductor element partitioned by scribe lines as shown in FIG. That is, the wafer 1 is provided with first and second X-axis direction scribe lines X 1 and X 2 which are parallel to the orientation flat 2 and have different intervals, and a first Y-axis direction scribe line orthogonal to the X-axis direction scribe lines. Two types of semiconductor elements having a chip area of S 1 and S 2 are formed by being partitioned by Y 1 .
【0007】半導体素子が形成されたウェハ1は、特性
チェック工程を経たのち、ペレッタイズ工程でペレット
に分割され、組立工程に送られる。The wafer 1 on which the semiconductor elements are formed is subjected to a characteristic check process, then divided into pellets in a pelletizing process, and sent to an assembly process.
【0008】このように第1の実施例においては、チッ
プサイズの異なる2種類の半導体素子を形成している
が、X軸方向のスクライブ線の間隔が異なっているだけ
のため、スクライブ工程は従来とほとんど変ることはな
い。As described above, in the first embodiment, two types of semiconductor elements having different chip sizes are formed. However, since the distance between the scribe lines in the X-axis direction is different, the scribing process is conventionally performed. There is almost no change.
【0009】尚、上記実施例においては、X軸方向のス
クライブ線の間隔を変えた場合について説明したが、更
にY軸方向のスクライブ線の間隔を変えることにより、
2種類以上のチップサイズを有する半導体素子を同一ウ
ェハ上に形成することができる。In the above embodiment, the case where the distance between the scribe lines in the X-axis direction is changed has been described. However, by changing the distance between the scribe lines in the Y-axis direction,
Semiconductor devices having two or more types of chip sizes can be formed on the same wafer.
【0010】図2は本発明の第2の実施例を説明するた
めのウェハの上面図である。この第2の実施例では間隔
の異なる2種類のX軸方向スクライブ線と、間隔が異な
りかつ不連続の2種類のY軸方向スクライブ線とにより
2種類の半導体素子を同一ウェハ1A上に形成した場合
である。FIG. 2 is a top view of a wafer for explaining the second embodiment of the present invention. In the second embodiment, two types of semiconductor elements are formed on the same wafer 1A by two types of X-axis direction scribe lines having different intervals and two types of discontinuous Y-axis direction scribe lines having different intervals. This is the case.
【0011】すなわちウェハ1AのA−A線の下部に、
第1のX軸方向スクライブ線X1 と第1のY軸方向スク
ライブ線Y1 とで区画され、チップ面積がS1 の半導体
素子を形成し、A−A線の上部には、第1のX軸方向ス
クライブ線X1 と間隔の異なる第3のX軸方向スクライ
ブ線X3 と第1のY軸方向スクライブ線Y1 と間隔の異
なる第2のY軸方向スクライブ線Y2 とで区画され、チ
ップ面積がS3 の半導体素子を形成する。That is, below the line AA of the wafer 1A,
Partitioned by the first to the X-axis direction scribe line X 1 first a Y-axis direction scribe line Y 1, the chip area to form a semiconductor element S 1, the upper part of the A-A line, first It is defined by the X-axis direction scribe line X 1 and the third X-axis direction scribe line X 3 and the first Y-axis direction scribe line Y 1 different second, and spacing of the Y-axis direction scribe line Y 2 having different intervals , A semiconductor element having a chip area of S 3 is formed.
【0012】このように構成されたウェハ1Aの場合
は、A−A線からウェハ1Aを2分割されば、スクライ
ブ工程はほぼ従来と同様になる。尚、ウェハ1AのA−
A線にそってスクライブ用の緩衝領域を設けておけば、
ウェハ1Aを2分割しなくてもよい。In the case of the wafer 1A thus constructed, if the wafer 1A is divided into two from the line AA, the scribing process becomes almost the same as the conventional one. Incidentally, A- of the wafer 1A
If you provide a buffer area for scribe along the line A,
The wafer 1A does not have to be divided into two.
【0013】更に不連続な複数のスクライブ線により複
数種の半導体素子を形成した場合は、それらスクライブ
線にレーザビームにより溝を形成しペレッタイズを行う
ことにより、チップサイズの異った複数の半導体素子を
容易に分割することができる。Further, when a plurality of types of semiconductor elements are formed by a plurality of discontinuous scribe lines, a groove is formed on the scribe lines by a laser beam and pelletizing is performed, so that a plurality of semiconductor elements having different chip sizes are formed. Can be easily divided.
【0014】尚、同一ウェハ上に形成されるチップサイ
ズの異なる半導体素子は、その製造工程、特に不純物拡
散工程や熱処理工程がほぼ同一であることが望ましい。It is desirable that the semiconductor devices formed on the same wafer and having different chip sizes have substantially the same manufacturing process, especially the impurity diffusion process and the heat treatment process.
【0015】[0015]
【発明の効果】以上説明したように本発明は、スクライ
ブ線の間隔を変えてチップサイズの異なる半導体素子を
同一ウェハ内に2種以上形成することによって、小型の
半導体装置を大口径のウェハで製造する場合にも在庫過
剰にならず、しかも同一期間、同一生産能力の生産ライ
ンで、多品種少量生産を可能にできるという効果を有す
る。As described above, according to the present invention, two or more kinds of semiconductor elements having different chip sizes are formed in the same wafer by changing the distance between the scribe lines, so that a small semiconductor device can be formed on a large diameter wafer. Even in the case of manufacturing, there is an effect that it is possible to carry out small-lot production of a wide variety of products on a production line having the same production capacity for the same period without causing excess inventory.
【図1】本発明の第1の実施例を説明するためのウェハ
の上面図。FIG. 1 is a top view of a wafer for explaining a first embodiment of the present invention.
【図2】本発明の第2の実施例を説明するためのウェハ
の上面図。FIG. 2 is a top view of a wafer for explaining a second embodiment of the present invention.
【図3】実施例を説明するための工程図。FIG. 3 is a process drawing for explaining the embodiment.
1,1A ウェハ 2 オリエンテーションフラット X1 〜X3 X軸方向スクライブ線 Y1 〜Y2 Y軸方向スクライブ線1,1A Wafer 2 Orientation flat X 1 to X 3 X-axis direction scribe line Y 1 to Y 2 Y-axis direction scribe line
Claims (2)
この第1のスクライブ線に直交するY軸方向の複数の第
2のスクライブ線とにより区画される半導体素子を半導
体基板上に形成する半導体装置の製造方法において、少
くとも前記第1のスクライブ線は複数の異なる間隔で形
成されることを特徴とする半導体装置の製造方法。1. A semiconductor element is formed on a semiconductor substrate by a plurality of first scribe lines in the X-axis direction and a plurality of second scribe lines in the Y-axis direction orthogonal to the first scribe lines. The method of manufacturing a semiconductor device according to claim 1, wherein at least the first scribe lines are formed at a plurality of different intervals.
スクライブ線から構成されている請求項1記載の半導体
装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein at least the second scribe line is composed of a discontinuous scribe line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16486491A JPH0513570A (en) | 1991-07-05 | 1991-07-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16486491A JPH0513570A (en) | 1991-07-05 | 1991-07-05 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0513570A true JPH0513570A (en) | 1993-01-22 |
Family
ID=15801374
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16486491A Pending JPH0513570A (en) | 1991-07-05 | 1991-07-05 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0513570A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0736900A2 (en) * | 1995-04-03 | 1996-10-09 | Xerox Corporation | Replacing semiconductor chips in a full-width chip array |
JP2008041158A (en) * | 2006-08-04 | 2008-02-21 | Victor Co Of Japan Ltd | Optical device and manufacturing method of the optical device |
KR20150114423A (en) | 2014-04-01 | 2015-10-12 | 세이코 인스트루 가부시키가이샤 | Semiconductor wafer |
JPWO2013179765A1 (en) * | 2012-05-30 | 2016-01-18 | オリンパス株式会社 | Imaging device manufacturing method and semiconductor device manufacturing method |
JPWO2013179767A1 (en) * | 2012-05-30 | 2016-01-18 | オリンパス株式会社 | Imaging device manufacturing method and semiconductor device manufacturing method |
WO2020021666A1 (en) * | 2018-07-25 | 2020-01-30 | 株式会社Fuji | Determination device and chip installation apparatus equipped with same |
JP2021020389A (en) * | 2019-07-29 | 2021-02-18 | 三星ダイヤモンド工業株式会社 | Method for parting brittle material substrate |
-
1991
- 1991-07-05 JP JP16486491A patent/JPH0513570A/en active Pending
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0736900A2 (en) * | 1995-04-03 | 1996-10-09 | Xerox Corporation | Replacing semiconductor chips in a full-width chip array |
EP0736900A3 (en) * | 1995-04-03 | 1999-08-25 | Xerox Corporation | Replacing semiconductor chips in a full-width chip array |
US6165813A (en) * | 1995-04-03 | 2000-12-26 | Xerox Corporation | Replacing semiconductor chips in a full-width chip array |
JP2008041158A (en) * | 2006-08-04 | 2008-02-21 | Victor Co Of Japan Ltd | Optical device and manufacturing method of the optical device |
JPWO2013179765A1 (en) * | 2012-05-30 | 2016-01-18 | オリンパス株式会社 | Imaging device manufacturing method and semiconductor device manufacturing method |
JPWO2013179767A1 (en) * | 2012-05-30 | 2016-01-18 | オリンパス株式会社 | Imaging device manufacturing method and semiconductor device manufacturing method |
US9698195B2 (en) | 2012-05-30 | 2017-07-04 | Olympus Corporation | Method for producing image pickup apparatus and method for producing semiconductor apparatus |
KR20150114423A (en) | 2014-04-01 | 2015-10-12 | 세이코 인스트루 가부시키가이샤 | Semiconductor wafer |
WO2020021666A1 (en) * | 2018-07-25 | 2020-01-30 | 株式会社Fuji | Determination device and chip installation apparatus equipped with same |
JPWO2020021666A1 (en) * | 2018-07-25 | 2021-02-15 | 株式会社Fuji | Determining device and chip mounting device equipped with it |
JP2021020389A (en) * | 2019-07-29 | 2021-02-18 | 三星ダイヤモンド工業株式会社 | Method for parting brittle material substrate |
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