JPH05134894A - Built-in microcode debugging circuit - Google Patents

Abstract

PURPOSE:To stop operation with an arbitrary microcode address and to externally control a random logic part by controlling a system clock with respect to the random clock part corresponding to the comparison result of a comparator CONSTITUTION:This circuit is provided with a comparator 8 comparing the output of a program counter 1 with an externally inputtable built-in microcode address, and a clock control circuit 9 controlling the system clock for a random logic part 5, and a selector 15 switching the input of the externally inputtable microcode and the built-in microcode and inputting the selected microcode in the random logic part 5. Thus, by setting an arbitrarily settable stop microaddress terminal 7, the operation of an LSI can be stopped with the arbitrary microcode address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a built-in microcode debug circuit, that is, a circuit for facilitating debugging of microcode in an integrated circuit containing a control microcode ROM. is there.

[0002]

2. Description of the Related Art FIG. 7 shows a simple structure of an LSI having a control microcode ROM which has been used conventionally. In the figure, 1 is a program counter, 2 is an output of the program counter 1, an address bus having an m-bit width, 3 is a built-in microcode ROM that receives the address bus 2, 4 is an output of the built-in microcode ROM 3. There is a data bus having a width of n bits, and 5 is a random logic part controlled according to a built-in microcode,
Reference numeral 6 is a system clock input terminal.

Next, the operation will be described. The system clock is sent from the system clock input terminal 6 to the random logic unit 5, and inside thereof, data and the like are taken in according to the timing of the system clock.
When the LSI starts operating, the program counter 1 performs a counting operation, and the address bus 2 changes its value according to the operation. The value of the address bus 2 is input as the address of the built-in microcode ROM 3, and the data corresponding to this address value is output to the data bus 4. This data is decoded by a microdecoding circuit (not shown) in the random logic unit 5, and then an instruction, that is, a microcode is executed according to the timing of the system clock.

[0004]

Since the conventional LSI device having the control microcode ROM built therein is configured as described above, the operation is stopped at an arbitrary microcode address during the microcode analysis. in case of,
It is necessary to stop the system clock midway. Further, even if the operation is stopped at an arbitrary microcode address and the microcode is input from the outside to control the random logic part, this is impossible.

The present invention has been made in order to solve the above-mentioned problems of the conventional ones, and the operation can be stopped at an arbitrary microcode address without controlling the system clock, and its state can be maintained. The purpose is to obtain a built-in microcode debug circuit that can control the random logic part by inputting microcode from the outside.

[0006]

A built-in microcode debug circuit according to the present invention includes a comparator which receives an output of a program counter and a built-in microcode address inputted from the outside, and a system clock for a random logic section. And a clock control circuit for controlling.

Also, the built-in microcode debug circuit according to the present invention is a clock control for controlling the system clock for the comparator, which receives the output of the program counter and the built-in microcode address input from the outside as input. It is provided with a circuit and a selector for switching the input of the microcode inputted from the outside and the built-in microcode to input to the random logic section.

The built-in microcode debug circuit according to the present invention has a serial-parallel data converter for at least one of the input of a built-in microcode address input from the outside and the input of a microcode input from the outside. Be prepared.

[0009]

In the built-in microcode debug circuit according to the present invention, the operation of the LSI can be stopped at an arbitrary microcode address by setting the stop microaddress terminal that can be arbitrarily set.

In the built-in microcode debug circuit according to the present invention, the operation of the LSI can be stopped at an arbitrary microcode address by setting the stop microaddress terminal that can be arbitrarily set, and the external microcode input port can be used. Any arbitrary microcode can be executed.

Further, in the built-in microcode debug circuit according to the present invention, at least one of the input of the built-in microcode address and the input of the microcode which can be input from the outside is performed by the serial-parallel data converter.
One pin enables serial input.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a built-in microcode debug circuit according to one embodiment of the present invention. In the figure, 1 is the program counter, 2 is the output of the program counter 1, m
An address bus having a bit width, 3 is a built-in microcode ROM, 4 is an output of the built-in microcode ROM 3, a data bus having an n-bit width, 5 is a random logic part controlled according to the built-in microcode, 6 is a system clock input terminal, 7 is a stop micro address setting terminal for setting a stop micro address from the outside, 8 is a comparator which receives the output of the program counter 1 and an internal micro code address input from the outside, Reference numeral 9 is a clock control circuit for controlling the system clock supplied to the random logic unit 5 according to the output of the comparator 8, 10 is a debug setting terminal for setting a debug mode from the outside, and 11 is a debug clock input from the outside. Input terminal, 12 is a comparator output, and 13 is a clock control circuit 9 Force, 23 is a logic synthesis output of the clock control circuit 9.

Next, the operation will be described. In FIG. 1, the system clock is sent from the system clock input terminal 6 to the clock control circuit 9. When the LSI starts operating, the program counter 1 performs a counting operation and outputs the value to the address bus 2. When this output coincides with the value set at the stop micro address setting terminal 7, the comparator 8 outputs the coincidence signal 12, and the signal 23 logically synthesized with the signal at the debug setting terminal 10 in the clock control circuit 9 becomes the program counter. Disable 1 count.

An example of the structure of this clock control circuit is shown in FIG. In the figure, 20 is a first AND element,
Reference numeral 21 is a second AND element, and 22 is an OR element. Figure 6
5 shows a timing chart of the nodes a to g shown in FIG.

When debugging the built-in microcode using the built-in microcode debug circuit of this embodiment, the debug setting terminal 10 is set to the debug mode. For example, in the configuration of FIG. 5, the debug setting terminal 10 is set to H level.

When the program counter 1 is in the count unenable state, the comparator output 12 outputs the coincidence signal and the state before the microaddress set by the stop microaddress setting terminal 7 is one state before the random logic section. The system clock 13 leading to the random logic unit 5 is stopped while the above is executed.
The output of the built-in microcode ROM 3 continues to output the microcode data corresponding to the microaddress set by the stop microaddress setting terminal 7 to the data bus 4. To execute this, the clock from the debug clock input terminal 11 is used. Input for one cycle, the microcode corresponding to the microaddress set by the stop microaddress setting terminal 7 will be
The SI operation will be retained.

Next, FIG. 2 shows a built-in microcode debug circuit according to another embodiment of the present invention. In FIG.
1 is a program counter, 2 is an output of the program counter 1, an address bus having a width of m bits, 3 is a built-in microcode ROM, 4 is a built-in microcode RO
M3 output, data bus with n-bit width, 5 random logic part, 6 system clock input terminal, 7
Is a stop micro address setting terminal for setting a stop micro address from the outside, 8 is a comparator, 9 is a clock control circuit, 10 is a debug setting terminal for setting a debug mode from the outside, and 11 is a debug clock from the outside. Debug clock input terminal for inputting, 12 is comparator output, 13 is output of clock control circuit 9, 23 is logic synthesis output of clock control circuit 9, and 14 is microcode input port for inputting microcode from outside , 15 is a selector, 16 is a selector switch of the selector 15, and 17 is an n-bit wide data bus output from the selector 15.

In FIG. 2, after the same operation as in FIG. 1 described above, the microcode to be added is set from the outside through the microcode input port 14. Next, the selector 15 is set through the changeover switch 16 so that the set microcode becomes the output of the selector 15. At this time, the data of the set microcode is output to the data bus 17. When the clock is input again from the debug clock input terminal 11 for one cycle, the operation of the LSI is retained while the set microcode is being executed.

FIG. 3 shows still another embodiment of the present invention.
In the figure, 18 is a serial-parallel data converter.

The operation in FIG. 3 is similar to that of the embodiment in FIG. However, since the stop micro address can be serially input from the outside, there is an effect that the number of pins of the LSI can be reduced.

FIG. 4 shows still another embodiment of the present invention.
In the figure, reference numeral 19 is a serial-parallel data converter that exists between at least one of the stop micro address setting terminal 7 and the comparator 8 or between the microcode input port 14 and the selector 15.

The operation in FIG. 4 is similar to that of the embodiment in FIG. However, since the microcode to be added can be serially input from the outside, there is an effect that the number of pins of the LSI can be reduced.

[0023]

As described above, according to the built-in microcode debug circuit of the present invention, the circuit is configured so that the operation of the LSI can be stopped or the additional microcode can be executed at an arbitrary microcode address. The built-in microcode can be debugged without stopping the system clock, and by utilizing the external microcode, it is possible to analyze random logic that could not be analyzed only by the built-in microcode.

The use of the serial-parallel data converter has the effect of reducing the number of external pins.

[Brief description of drawings]

FIG. 1 is a diagram showing a built-in microcode debug circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a built-in microcode debug circuit according to an embodiment of the present invention.

FIG. 3 is a diagram showing a built-in microcode debug circuit according to an embodiment of the present invention.

FIG. 4 is a diagram showing a built-in microcode debug circuit according to an embodiment of the present invention.

FIG. 5 is a diagram showing a configuration example of a clock control circuit according to the present invention.

FIG. 6 is a timing chart for one configuration example of the clock control circuit according to the present invention.

FIG. 7 is a diagram showing a simple configuration example of an LSI having a control microcode ROM which has been used conventionally.

[Explanation of symbols]

 1 Program counter 2 Address bus (m bit) 3 Built-in microcode ROM 4 Data bus (n bit) 5 Random logic part 6 System clock input terminal 7 Stop micro address setting terminal 8 Comparator 9 Clock control circuit 10 Debug setting terminal 11 Debug Clock input terminal 12 Comparator output 13 Clock control circuit output 14 Microcode input port 15 Selector 16 Changeover switch 17 Data bus (n bit) 18 Serial-parallel data converter 19 Serial-parallel data converter 20 First AND element 21 Second AND element 22 OR element 23 Logic synthesis output

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[Procedure amendment]

[Submission date] August 3, 1992

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[0001]

BACKGROUND OF THE INVENTION This invention is in the braking patronage microcode integrated circuit ROM is incorporated, to a circuit for the easily so debugging microcode.

[Procedure Amendment 5]

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[Correction target item name] 0006

[Correction method] Change

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[0006]

A built-in microcode debug circuit according to the present invention includes a comparator which receives an output of a program counter and a built-in microcode address which can be input from the outside, and a system clock for a random logic section. And a clock control circuit for controlling.

[Procedure correction 6]

[Document name to be amended] Statement

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[Correction method] Change

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Further, the built-in microcode debug circuit according to the present invention includes a comparator which receives the output of the program counter and a built-in microcode address which can be input from the outside, and a clock control which controls the system clock for the random logic section. It is provided with a circuit and a selector for switching between the input of a microcode that can be input from the outside and the built-in microcode and inputting to the random logic unit.

[Procedure Amendment 7]

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Further, the built-in microcode debug circuit according to the present invention has a serial-parallel data converter for at least one of the input of a built-in microcode address input from the outside and the input of a microcode that can be input from the outside. Be prepared.

[Procedure Amendment 8]

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[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a built-in microcode debug circuit according to one embodiment of the present invention. In the figure, 1 is the program counter, 2 is the output of the program counter 1, m
An address bus having a bit width, 3 is a built-in microcode ROM, 4 is an output of the built-in microcode ROM 3, a data bus having an n-bit width, 5 is a random logic part controlled according to the built-in microcode, 6 is a system clock input terminal, 7 is a stop micro address setting terminal for setting a stop micro address from the outside, 8 is a comparator which receives the output of the program counter 1 and a built-in micro code address which can be input from the outside, Reference numeral 9 is a clock control circuit for controlling the system clock supplied to the random logic unit 5 according to the output of the comparator 8, 10 is a debug setting terminal for setting a debug mode from the outside, and 11 is a debug input terminal which can be input from the outside. clock clock input terminal, 12 is a comparator output, 13 is a clock control circuit The output of 23 is a logic synthesis output of the clock control circuit 9.

[Procedure Amendment 9]

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Next, FIG. 2 shows a built-in microcode debug circuit according to another embodiment of the present invention. In FIG.
1 is a program counter, 2 is an output of the program counter 1, an address bus having a width of m bits, 3 is a built-in microcode ROM, 4 is a built-in microcode RO
M3 output, data bus with n-bit width, 5 random logic part, 6 system clock input terminal, 7
Is a stop micro address setting terminal for setting a stop micro address from the outside, 8 is a comparator, 9 is a clock control circuit, 10 is a debug setting terminal for setting a debug mode from the outside, and 11 is a debug clock from the outside. A debug clock input terminal for inputting, 12 is a comparator output, 13 is an output of the clock control circuit 9, 23 is a logic synthesis output of the clock control circuit 9, 14 is a microcode input port to which microcode can be input from the outside, Reference numeral 15 is a selector, 16 is a selector switch of the selector 15, and 17 is an n-bit wide data bus output from the selector 15.

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[Figure 5]

Claims (3)

[Claims] 1. A comparator which receives an output of a program counter and a built-in microcode address inputted from the outside, and a system clock control which controls a system clock for a random logic unit according to a comparison result of the comparator. And a built-in microcode debug circuit. 2. A comparator which receives an output of a program counter and a built-in microcode address inputted from the outside, and a system clock control which controls a system clock for a random logic unit according to a comparison result of the comparator. A built-in microcode debug circuit comprising a circuit and a selector for switching between a microcode input from the outside and a built-in microcode to input to the random logic unit. 3. At least one of the input of a built-in microcode address input from the outside and the input of a microcode input from the outside is serial-connected.
The built-in microcode debug circuit according to claim 1 or 2, further comprising a parallel data converter.