JPH0513470A - Charge coupled device - Google Patents

Charge coupled device

Info

Publication number
JPH0513470A
JPH0513470A JP3183783A JP18378391A JPH0513470A JP H0513470 A JPH0513470 A JP H0513470A JP 3183783 A JP3183783 A JP 3183783A JP 18378391 A JP18378391 A JP 18378391A JP H0513470 A JPH0513470 A JP H0513470A
Authority
JP
Japan
Prior art keywords
region
charge transfer
charge
type
transfer region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3183783A
Other languages
Japanese (ja)
Other versions
JP3048011B2 (en
Inventor
Yasutaka Nakashiba
康▲隆▼ 中柴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3183783A priority Critical patent/JP3048011B2/en
Publication of JPH0513470A publication Critical patent/JPH0513470A/en
Application granted granted Critical
Publication of JP3048011B2 publication Critical patent/JP3048011B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To enable a charge coupled device to be enhanced in fringe electrical field and transfer efficiency by a method wherein a low impurity concentration region is provided at least at the center under a charge transfer region. CONSTITUTION:A P-type well 2 is formed inside an N-type semiconductor substrate 1, and an N-type charge transfer region 3 is formed inside the P-type well 2. An N<->-type region 8 lower than the charge transfer region 3 in impurity concentration is formed between the P-type well 2 and the charge transfer region 3, and a transfer electrode 7 is formed on the charge transfer region 3 through the intermediary of a gate insulating film 6. By this setup, a depletion layer under the charge transfer region is made to extend enough toward the inside of the substrate, whereby an intense fringe electric field can be induced. Therefore, by this constitution, transfer efficiency of a charge coupled device can be enhanced without deteriorating in charge transfer performance per unit area.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は固体撮像素子等において
用いられる電荷結合素子に関し、特に埋め込みチャネル
型の電荷結合素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge coupled device used in a solid-state image pickup device and the like, and more particularly to a buried channel type charge coupled device.

【0002】[0002]

【従来の技術】図5の(a)は従来例の電荷結合素子を
用いた固体撮像素子の断面図であり、図5の(b)はそ
のZ−Z′線断面の不純物プロファイルである。同図に
おいて、1はn型半導体基板、2はn型半導体基板上に
形成されたp型ウェル、3はp型ウェルの表面領域内に
形成されたn型の電荷転送領域、4は、同じくp型ウェ
ルの表面領域内に形成されたn型の光電変換領域、5
は、電荷転送領域3と光電変換領域4とを分離するため
にこれらの領域間に形成されたp+型領域、6はゲート
絶縁膜、7は多結晶シリコンからなる転送電極である。
2. Description of the Related Art FIG. 5 (a) is a sectional view of a solid-state image pickup device using a conventional charge-coupled device, and FIG. 5 (b) is an impurity profile taken along the line ZZ '. In the figure, 1 is an n-type semiconductor substrate, 2 is a p-type well formed on an n-type semiconductor substrate, 3 is an n-type charge transfer region formed in the surface region of the p-type well, and 4 is the same. n-type photoelectric conversion region formed in the surface region of the p-type well, 5
Is a p + type region formed between these regions to separate the charge transfer region 3 and the photoelectric conversion region 4, 6 is a gate insulating film, and 7 is a transfer electrode made of polycrystalline silicon.

【0003】図では転送電極7を1個のみ示したにすぎ
ないが実際には電荷結合素子を構成するために、転送電
極は、紙面に垂直に延びる電荷転送領域3上に多数並べ
られている。
Although only one transfer electrode 7 is shown in the figure, in order to actually form a charge-coupled device, a large number of transfer electrodes are arranged on the charge transfer region 3 extending perpendicularly to the paper surface. .

【0004】而して、電荷結合素子は、例えば固体撮像
素子の高画素化、小型化に伴ってその領域も徐々に縮小
化されつつある。しかし、縮小化されても最大転送可能
電荷量を削減することはできない場合が多いので、従来
は、電荷転送領域3の接合深さを浅くすることにより、
電荷転送能力の向上に努めてきた。
The area of the charge-coupled device has been gradually reduced as the number of pixels and the size of the solid-state image sensor are increased. However, even if the size is reduced, it is often impossible to reduce the maximum transferable charge amount. Therefore, conventionally, by making the junction depth of the charge transfer region 3 shallow,
We have tried to improve the charge transfer capability.

【0005】[0005]

【発明が解決しようとする課題】上述した従来の電荷結
合素子では、小型化による電荷転送能力の低下を電荷転
送領域のp型ウェルとの接合の深さを浅くすることによ
りカバーしてきたので、例えばHDTV対応固体撮像素
子のように超高画素化、超小型化がなされると、電荷転
送領域の接合深さが極めて浅くなり、電荷転送に重要な
位置を占めるフリンジ電界強度が減少し、転送効率の劣
化が増大するという欠点があった。
In the conventional charge-coupled device described above, the decrease in the charge transfer capability due to the miniaturization has been covered by making the junction depth with the p-type well in the charge transfer region shallow. For example, when an ultra-high pixel count and an ultra-miniaturization are performed in a solid-state image sensor compatible with HDTV, the junction depth of the charge transfer region becomes extremely shallow, and the fringe electric field strength occupying an important position for charge transfer is reduced, resulting in a transfer. There is a drawback that efficiency deterioration is increased.

【0006】[0006]

【課題を解決するための手段】本発明の電荷結合素子
は、第1導電型の半導体層と、前記半導体層の表面領域
内に形成された第2導電型の電荷転送領域と、前記電荷
転送領域の下面全体または下面中央部に形成された、前
記電荷転送領域よりも不純物濃度の低い低濃度第2導電
型半導体領域または前記半導体層よりも不純物濃度の低
い低濃度第1導電型半導体領域と、前記電荷転送領域上
に絶縁膜を介して形成された複数の転送電極と、を有す
るものである。
A charge-coupled device according to the present invention comprises a first-conductivity-type semiconductor layer, a second-conductivity-type charge transfer region formed in a surface region of the semiconductor layer, and the charge-transfer device. A low-concentration second conductivity type semiconductor region having an impurity concentration lower than that of the charge transfer region or a low-concentration first conductivity type semiconductor region having an impurity concentration lower than that of the semiconductor layer, which is formed over the entire lower surface of the region or in the central portion of the lower surface; A plurality of transfer electrodes formed on the charge transfer region via an insulating film.

【0007】[0007]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。図1の(a)は本発明の第1の実施例を用
いた固体撮像素子の断面図であり、図1の(b)はその
X−X′線断面の不純物プロファイルである。同図にお
いて、1はn型半導体基板、2はn型半導体基板上に形
成されたp型ウェル、3はp型ウェルの表面領域内に形
成されたn型の電荷転送領域、4は、同じくp型ウェル
の表面領域内に形成されたn型の光電変換領域、5は、
電荷転送領域3と光電変換領域4とを分離するためにこ
れらの領域間に形成されたp+ 型領域、6はゲート絶縁
膜、7は多結晶シリコンからなる転送電極、8は電荷転
送領域3の下面全面に形成されたこの領域より不純物濃
度の低いn- 型領域である。
Embodiments of the present invention will now be described with reference to the drawings. FIG. 1A is a sectional view of a solid-state image sensor using the first embodiment of the present invention, and FIG. 1B is an impurity profile of the XX 'line section. In the figure, 1 is an n-type semiconductor substrate, 2 is a p-type well formed on an n-type semiconductor substrate, 3 is an n-type charge transfer region formed in the surface region of the p-type well, and 4 is the same. The n-type photoelectric conversion regions 5 formed in the surface region of the p-type well are
A p + type region formed between these regions to separate the charge transfer region 3 and the photoelectric conversion region 4, 6 is a gate insulating film, 7 is a transfer electrode made of polycrystalline silicon, and 8 is a charge transfer region 3 Is an n -type region having a lower impurity concentration than this region formed on the entire lower surface of.

【0008】本実施例の電荷結合素子は、上記の構成を
有しているので、電荷結合素子が小型化され、電荷転送
領域3のp型ウェル2との接合の深さが極めて浅くなさ
れた場合においても、電荷転送時に転送電極下の空乏層
を基板内部に向けて十分に延ばすことができるので、電
荷転送に重要な役割を演ずる強いフリンジ電界を生じさ
せることができる。
Since the charge-coupled device of this embodiment has the above-mentioned structure, the charge-coupled device is downsized, and the depth of the junction with the p-type well 2 in the charge transfer region 3 is made extremely shallow. Also in this case, since the depletion layer under the transfer electrode can be sufficiently extended toward the inside of the substrate during charge transfer, a strong fringe electric field that plays an important role in charge transfer can be generated.

【0009】ここで、不純物濃度を比較するに、従来例
では、図5の(b)に示されるように、p型ウェルの不
純物濃度が1×1016cm-3、電荷転送領域3の不純物濃
度が8×1016cm-3であったのに対し、本実施例ではp
ウェル3の不純物濃度が1×1016cm-3、電荷転送領域
の不純物濃度が1×1017cm-3、n- 型領域8の不純物
濃度が5×1015cm-3に形成されている。ここで、ゲー
ト絶縁膜6の膜厚、チャネル長、チャネル幅が同一であ
るものとすると、本実施例では、単位面積当たりの電荷
転送能力は従来例とほぼ同等であるが、電荷転送電極下
のフリンジ電界が高められているので、転送効率の向上
が図られている。
Here, as a comparison of the impurity concentrations, in the conventional example, as shown in FIG. 5B, the impurity concentration of the p-type well is 1 × 10 16 cm −3 , and the impurity of the charge transfer region 3 is While the concentration was 8 × 10 16 cm −3 , in this example p
The well 3 has an impurity concentration of 1 × 10 16 cm −3 , the charge transfer region has an impurity concentration of 1 × 10 17 cm −3 , and the n type region 8 has an impurity concentration of 5 × 10 15 cm −3 . . Here, assuming that the gate insulating film 6 has the same film thickness, channel length, and channel width, in this embodiment, the charge transfer capacity per unit area is almost the same as that of the conventional example, but the charge transfer electrode Since the fringe electric field is increased, the transfer efficiency is improved.

【0010】図2の(a)は本発明の第2の実施例を用
いた固体撮像素子の断面図であり、図2の(b)はその
Y−Y′線断面の不純物プロファイルである。図2の
(a)において、図1の(a)に示された第1の実施例
の部分と同等の部分には同一の参照番号が付されている
ので重複した説明は省略する。
FIG. 2A is a sectional view of a solid-state image pickup device using the second embodiment of the present invention, and FIG. 2B is an impurity profile of the section taken along the line YY '. In FIG. 2A, the same parts as those of the first embodiment shown in FIG. 1A are designated by the same reference numerals, and a duplicate description will be omitted.

【0011】本実施例の第1の実施例と相違する点は、
第1の実施例のn- 型領域8に代えて電荷転送領域3の
下面にp- 型領域9が形成されている点である。本実施
例では、上記構成をとることにより、電荷転送時に転送
電極下の空乏層を基板内部に向けて十分に延ばすことが
できるので、先の実施例と同様の効果を期待することが
できる。
The difference between this embodiment and the first embodiment is that
The p type region 9 is formed on the lower surface of the charge transfer region 3 in place of the n type region 8 of the first embodiment. In the present embodiment, with the above configuration, the depletion layer under the transfer electrode can be sufficiently extended toward the inside of the substrate during charge transfer, so that the same effect as the previous embodiment can be expected.

【0012】図3、図4は、それぞれ本発明の第3、第
4の実施例を示す断面図である。第3、第4の実施例と
先の第1または第2の実施例と相違する点は、第1また
は第2の実施例において電荷転送領域3の下面全体に設
けられていたn- 型領域8またはp- 型領域9が第3、
第4の実施例においては電荷転送領域の中央部のみに限
定されて設けられている点である。第3、第4の実施例
では、上記の構成により、転送電極中央部の、フリンジ
電界が最も弱くなる箇所の空乏層を基板内部に向けて十
分に延ばして、ここでのフリンジ電界の強化を図ること
ができるため、第1、第2の実施例と同様の効果を期待
することができる。
FIG. 3 and FIG. 4 are sectional views showing the third and fourth embodiments of the present invention, respectively. The difference between the third and fourth embodiments and the first or second embodiment is that the n type region provided on the entire lower surface of the charge transfer region 3 in the first or second embodiment. 8 or p - type region 9 is the third,
In the fourth embodiment, it is provided only in the central portion of the charge transfer region. In the third and fourth embodiments, with the above configuration, the depletion layer at the center of the transfer electrode where the fringe electric field is weakest is sufficiently extended toward the inside of the substrate to enhance the fringe electric field here. Since it can be achieved, the same effects as those of the first and second embodiments can be expected.

【0013】[0013]

【発明の効果】以上説明したように、本発明は、埋め込
みチャネル型電荷結合素子において、電荷転送領域下の
少なくとも中央部分に低不純物濃度領域を設けたもので
あるので、素子の小型化に対応して電荷転送能力を確保
するために電荷転送領域の接合深さが浅くなされた場合
であっても、転送電極下の空乏層を基板内部に向けて十
分に延ばすことができる。従って、本発明によれば、単
位面積当たりの電荷転送能力を弱めることなく、電荷転
送に重要な役割を担うフリンジ電界を強化するとがで
き、転送効率の改善を図ることができる。
As described above, according to the present invention, in the buried channel type charge coupled device, the low impurity concentration region is provided at least in the central portion under the charge transfer region, so that the device can be miniaturized. Then, even when the junction depth of the charge transfer region is made shallow to secure the charge transfer capability, the depletion layer under the transfer electrode can be sufficiently extended toward the inside of the substrate. Therefore, according to the present invention, the fringe electric field that plays an important role in charge transfer can be strengthened without weakening the charge transfer capacity per unit area, and the transfer efficiency can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示す断面図とそのX−
X′線断面の不純物プロファイル図。
FIG. 1 is a sectional view showing a first embodiment of the present invention and its X-
The impurity profile figure of a X'line cross section.

【図2】本発明の第2の実施例を示す断面図とそのY−
Y′線断面の不純物プロファイル図。
FIG. 2 is a sectional view showing the second embodiment of the present invention and its Y- section.
The impurity profile figure of a Y'line cross section.

【図3】本発明の第3の実施例を示す断面図。FIG. 3 is a sectional view showing a third embodiment of the present invention.

【図4】本発明の第4の実施例を示す断面図。FIG. 4 is a sectional view showing a fourth embodiment of the present invention.

【図5】従来例の断面図とそのZ−Z′線断面の不純物
プロファイル図。
FIG. 5 is a cross-sectional view of a conventional example and an impurity profile diagram of the cross section along the line ZZ ′.

【符号の説明】[Explanation of symbols]

1…n型半導体基板 2…p型ウェル 3…電荷転送領域 4…光電変換領域 5…素子分離領域となるp+ 型領域 6…ゲート絶縁膜 7…転送電極 8…n- 型領域 9…p- 型領域DESCRIPTION OF SYMBOLS 1 ... n-type semiconductor substrate 2 ... p-type well 3 ... charge transfer region 4 ... photoelectric conversion region 5 ... p + type region 6 serving as an element isolation region 6 ... gate insulating film 7 ... transfer electrode 8 ... n type region 9 ... p - type region

Claims (1)

【特許請求の範囲】 【請求項1】 第1導電型の半導体層の表面領域内に設
けられた第2導電型の電荷転送領域と、前記電荷転送領
域上に絶縁膜を介して設けられた複数の電荷転送電極
と、を備える電荷結合素子において、 前記電荷転送領域下の少なくとも中央部分には前記電荷
転送領域の不純物濃度より低い不純物濃度の第2導電型
低不純物濃度領域または前記半導体層の不純物濃度より
低い不純物濃度の第1導電型低不純物濃度領域が形成さ
れていることを特徴とする電荷結合素子。
Claim: What is claimed is: 1. A second conductivity type charge transfer region provided in a surface region of a first conductivity type semiconductor layer, and an insulating film provided on the charge transfer region. In a charge coupled device including a plurality of charge transfer electrodes, at least a central portion below the charge transfer region has a second conductivity type low impurity concentration region having an impurity concentration lower than that of the charge transfer region or the semiconductor layer. A charge-coupled device comprising a first conductivity type low impurity concentration region having an impurity concentration lower than that of an impurity concentration.
JP3183783A 1991-06-28 1991-06-28 Charge-coupled device Expired - Fee Related JP3048011B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3183783A JP3048011B2 (en) 1991-06-28 1991-06-28 Charge-coupled device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3183783A JP3048011B2 (en) 1991-06-28 1991-06-28 Charge-coupled device

Publications (2)

Publication Number Publication Date
JPH0513470A true JPH0513470A (en) 1993-01-22
JP3048011B2 JP3048011B2 (en) 2000-06-05

Family

ID=16141864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3183783A Expired - Fee Related JP3048011B2 (en) 1991-06-28 1991-06-28 Charge-coupled device

Country Status (1)

Country Link
JP (1) JP3048011B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08274293A (en) * 1995-03-31 1996-10-18 Nec Corp Solid-state sensing device
JPH09266296A (en) * 1996-03-28 1997-10-07 Nec Corp Solid-state image sensing device
JP2002151676A (en) * 2000-03-17 2002-05-24 Nikon Corp Image pickup device, its manufacturing method, alignment device, aligner, abberation measuring instrument, and method of manufacturing the device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08274293A (en) * 1995-03-31 1996-10-18 Nec Corp Solid-state sensing device
JPH09266296A (en) * 1996-03-28 1997-10-07 Nec Corp Solid-state image sensing device
JP2002151676A (en) * 2000-03-17 2002-05-24 Nikon Corp Image pickup device, its manufacturing method, alignment device, aligner, abberation measuring instrument, and method of manufacturing the device

Also Published As

Publication number Publication date
JP3048011B2 (en) 2000-06-05

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