JPS6312162A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the sensitivity of a CCD image pickup device remarkably and to improve resolution, by forming a CCD in a long recess part, which is formed in a high resistance semiconductor layer in one direction. CONSTITUTION:A recess part, which has a width W and a depth H, is formed approximately vertically from the surface of a p-type semiconductor substrate 101 having a high resistance value. First polysilicon 103 and second polysilicon 104 are formed through an insulating film 102. A p<+> region 105 is formed as a channel stop directly beneath the recess part phi1 pulses are applied to the first polysilicon 103, and phi2 pulses are applied to the second polysilicon. Thus charge transfer is carried out in the longitudinal direction of the recess part. When the channel stop 105 is used, two charge transfer region 106 and 107 can be utilized. when the channel stop is not formed, one charge transfer region 109 is utilized. In this way, a plurality of transfer gate electrodes are provided on the surface of the long recess part, which is formed in the highly resistive semiconductor layer in one direction. Therefore the maximum charge transfer quantity of the CCD, which is formed at the side well of the recess part, depends on the depth H of the recess part.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device using charge transfer capable of handling high density and a method for manufacturing the same.

Conventional technology COD (Charge Coupled Device) is a typical example of conventional semiconductor devices that utilize charge transfer.
(vice) Press) Among them, the spread of CCD type imaging devices has been remarkable in recent years. As shown in FIG. 9, the CCD type imaging device is composed of a light receiving section 903 consisting of a photoelectric conversion region 901 and a vertical CCD section 902, a horizontal CJCD section 904, and an output circuit 905. FIG. 10 shows an enlarged view of the light-receiving portion 903, showing the n-region 9 formed on the surface of the p-substrate 906.
07 constitutes a photoelectric conversion region 903 of a pn photodiode, and a high resistance n- region 908 constitutes a transfer gate electrode 909.
Together, they constitute a vertical CCD section 902.

Problems to be Solved by the Invention However, with the above configuration, it is not easy to simultaneously improve sensitivity, resolution, and dynamic range, which are the basic performances of an imaging device.

FIG. 11 shows the changes in line width, chip area, and cell area with respect to the capacity of dynamic RAM (hereinafter referred to as DRAM), which plays a leading role in semiconductor technology. What can be seen from Figure 11 is that the degree of progress in microfabrication technology corresponding to the chip area of a CCD imaging device is large; for example, the % inch light receiving area (area) is 4Mb DRAM.
If we consider the cell area of a 4 Mb DRAM as the pixel area, it can be seen that the number of pixels in the % inch CCD imaging device can be up to 2000 x 2000 (pieces).

However, the sensitivity of the imaging device depends on the aperture ratio (i.e., the area occupation ratio of the total area of the photoelectric conversion region 901 to the light receiving portion 903), and on the other hand, the dynamic range depends on the vertical C
It depends on the channel width (i.e., the width of the high resistance n-region 908) which determines the maximum charge transfer amount of the 0D 902. Furthermore,
The resolution depends on the number of pixels, and an increase in the number of pixels is caused by a pixel isolation region (such as the channel stop region 910 in Figure 1o).
Therefore, given the area of the light-receiving portion 903, the optimal values of sensitivity, resolution, and dynamic range are almost determined, and these basic performances cannot be further improved. The problem was that there was no

The present invention has focused on these points, and aims to provide a semiconductor device and a method for manufacturing the same that can improve sensitivity and resolution without impairing dynamic range performance.

Means for Solving the Problems The present invention has a plurality of transfer gate electrodes on the surface of a recess long in one direction, which is formed in a high-resistance semiconductor layer, with an insulating film interposed therebetween. A semiconductor device in which a charge transfer region is formed in a semiconductor layer and a method for manufacturing the same.

Effect Since the present invention forms a charge transfer region in the semiconductor layer under the sidewall of the recess with the above-described structure, the channel width that determines the amount of large charge transfer corresponds to the depth of the recess. As a result, CCD
The area required for the vertical COD, which is related to the dynamic range of the imaging device, is now comparable to that of the pixel separation area9, making it possible to significantly improve performance in terms of resolution and resolution.

Embodiment FIG. 1 shows a structural diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 1(a) is a plan view, and FIG. 'Cross-sectional view, the same figure (C) is the same figure e)
(Dc-c' sectional view, the same figure (d) is the D-D' sectional view of the same figure (8-), the same figure (e) is the same figure (2L) (7)
K-1' sectional view, the same figure (f) is F-F' of the same figure (d)
The energy band diagram in the main operating state along the cross section (C). Figure (g) is a sectional view taken along line DD' in Figure (a) when this embodiment is partially modified. ) is a drive pulse diagram.

In FIG. 1, a recess with a width W and a depth H is formed almost perpendicularly from the surface of a high-resistance p-type semiconductor substrate 101, and an insulating film 101 is
The first polysilicon 1Q3° and the second polysilicon 104 are formed through the polysilicon 2 and the second polysilicon 104. Note that a channel stop p region 105 is formed directly below the recess. 106 and 107 are charge transfer regions that appear in the main operating state, as shown in Fig. 1(f).
corresponds to the surface channel portion 108 of.

FIG. 1(g) corresponds to the case where the channel stop p-region 105 is not formed, and 109 represents the charge transfer region in this case.

The operation of the semiconductor device of this embodiment configured as described above will be described below.

1) are the driving pulses of this embodiment. For example, by applying a φ1 pulse to the first polysilicon 103 and a φ2 pulse to the second polysilicon 7,
Charge transfer occurs in the longitudinal direction of the recess. Figure 1(d)
When a channel stop 105 is used as shown in FIG. 1(g), two charge transfer regions 106 and 107 can be used.
When no channel stop is formed, as in the case of FIG. 1, one charge transfer region 109 can be used.

As described above, according to this embodiment, by providing a plurality of transfer gate electrodes via an insulating film on the surface of a recess long in one direction formed in a high-resistance semiconductor layer, the COD formed on the side wall of the recess is The maximum charge transfer amount depends on the recess depth H. On the other hand, the width W of the concave portion is approximately 0.8 μm if a complementary process is used for a 4 Mb DRAM9, and the occupied area required for COD formation is extremely small.

In addition, in this example, the p' region 1 of the channel stop
Instead of 06, a thick insulating film may be formed in the corresponding portion.

FIG. 2 shows a structural diagram of a semiconductor device according to a second embodiment of the present invention, in which e) is a plan view and (b) is a plan view.
2L), the same figure (C) is a CC' cross-sectional view of the same figure (a-), the same figure (d) is the same figure (2L) D-D
t7) Energy band in main operating state along F-F' cross-section It is a diagram.

In FIG. 2, a recess with a width W and a depth H is formed almost perpendicularly from the surface of a high-resistance n-type semiconductor 202 on a p-substrate 201 (
At this time, the bottom of the recess may reach the p-substrate 201. )
Then, a first polysilicon 103 and a second polysilicon 104 are formed with an insulating film 203 in between, as in FIG. In addition, there is a channel stop p+ region 20 directly below the recess.
4 is formed. 205 and 206 are charge transfer regions that appear in the main operating state, and correspond to the buried channel portion 207 in FIG. 2(f).

The operation of this embodiment is similar to that of the first embodiment.

As described above, according to this embodiment, by making the high-resistance semiconductor layer for forming the charge transfer region n-type, a buried channel is formed and the effects of crystal defects on the surface of the recess can be avoided. The output and can transfer efficiency is improved, and noise is reduced.

FIG. 3 shows a structural diagram of a semiconductor device according to a third embodiment of the present invention, where e) is a plan view, and FIG.
2L) BB' cross-sectional view, the same figure (C) is C of the same figure (a)
-C' sectional view, the same figure (d) is a DD' sectional view of the same figure e), and the same figure (6) is the EE' sectional view of the same figure e).

In FIG. 3, the width W is approximately perpendicular to the surface of the p-substrate 301.
, a high-resistance n-type semiconductor layer 302 is formed with a recessed portion having a depth H.
After forming around the recess, p″-region 3 of the channel stop
Form 03. Thereafter, a first polysilicon layer 103 and a second polysilicon layer 104 are formed with an insulating film 304 interposed therebetween. Reference numerals 305 and 306 indicate charge transfer regions that appear in the main operating state and serve as buried channels. The operation of this embodiment is the same as that of the first embodiment. The difference between the second embodiment and this embodiment is the method of forming a high-resistance n-type semiconductor layer, which can be used depending on the application and process. I can do things.

FIG. 4 shows a structural diagram of a semiconductor device according to a fourth embodiment of the present invention, in which (a) is a plan view, and (b) is a cross-sectional view taken along line B in the figure (&). , the same figure (C) is C of the same figure (2L)
-C' sectional view, the same figure (d) is D -D' of the same figure (2L)
The cross-sectional view (6) is the E-E' cross-sectional view of the figure (2L);
2L) CC' cross-sectional view of the same figure (FIG.
-G' sectional view. Φ) in the figure is a drive pulse diagram.

4e) to (e), a recess with a width W and a depth H is formed almost perpendicularly from the surface of the p-substrate 401, and after forming a high-resistance n-type semiconductor layer 402 around the recess, the first channel A stop p+ region 403 is formed.

On the other hand, on the surface of the p-substrate 401, there is a p-substrate as a photoelectric conversion region.
An n+ region 404 is formed to form an n junction, and then a first polysilicon layer 406 is formed via an insulating film 405.
, a second polysilicon 407 is formed. p+ region 41
0 is a channel stop for pixel separation.

In addition, as shown in FIG. 4 (fl, (g)), the area w x u.

After forming a recessed portion with a depth h, an n+ hollow region 408 may be formed to serve as a photoelectric conversion region. (P+ region 409 (1, channel stop for pixel isolation) The operation of the semiconductor device of this embodiment configured as above will be explained. FIG. 4) is the driving pulse of this embodiment, For example, by applying a φ1 pulse to the first polysilicon 406 and a φ2 pulse to the second polysilicon 40, the φ1. φ
With a VH pulse of 2, the photoelectrically converted and accumulated signal charge in the n region 404 (or 408) is transferred to the charge transfer region 411 of the n region 402, and with a V pulse, the charge is transferred in the longitudinal direction of the recess. sf;).

As described above, according to this embodiment, when a 4Mb DRAM process is used (see FIG. 11), the width X of the reading ratio gate region 412 and the CCD section is only about 4 μm. If a two-dimensional imaging device is constructed by repeating the above steps horizontally and vertically, then the COD with an inch-inch light-receiving area has an aperture ratio of about 8Q%, and the aperture ratio of a CCD with an A-inch light-receiving area is about 78%. , the width of the element isolation region is 0.8 μm
, the channel length of the read gate region was set to 1.6 μm.

) This is approximately 3.5 compared to the current COD aperture ratio of 22
~4 times as many. Therefore, if the current number of pixels of the CCD remains unchanged, the sensitivity can be increased four times, and if the sensitivity remains unchanged, the number of pixels can be increased approximately 2.5 times. In other words, for a 500X500 element in % inch COD, 800X800 while maintaining sensitivity.
This means that an element can be constructed. Also, % inch COD
If you maintain the sensitivity and make 1 inch CCII, 1
This has a great effect, as an element of 600×1600 can be obtained.

FIG. 6 shows a structural diagram of a semiconductor device according to a fifth embodiment of the present invention, in which (+a) is a plan view, and (b) is a sectional view taken along line BB' in (e) of the same figure. , the same figure (C) is C of the same figure (a)
-C' sectional view, the same figure (d) is D -D' of the same figure (2L)
Cross-sectional view, Figure (e) is an e-e' cross-sectional view of Figure (2L), Figure (0 is an actual diagram showing the silicon single crystal part, Figure k) is an actual diagram showing the silicon polycrystal part. It is a diagram.

In FIG. 5, a high resistance n-type semiconductor 502, a p shadow region 6o3 (this constitutes a readout gate region), and an n region 504 are formed on a p substrate 601.
From the surface, approximately perpendicularly, the width W1. A first recessed portion having a depth Hl is formed, while a second recessed portion having a depth m W2 +H2 is formed orthogonally to the first recessed portion. Note that a channel stop p+ hollow region 506 is formed directly below the first recess. After forming an insulating film 506 in the recess, a first polysilicon film 507 is formed.
゜508, form the second polysilicon 509, 510, transfer game)! constitute the poles. However, first polysilicon 508 and second polysilicon 510 are also components of the read gate region. In addition, 511.511' is
This is the charge transfer region that appears in the main operation state. When the voltage applied to the transfer gate electrode is large, E511,611'
It is also possible that they will merge into one.

The action of the untrue example is j・=, the fourth implementation reli and the giant J.

There is a difference of 1 inch between this embodiment and the fourth embodiment, and since the read gate region of this embodiment is also formed on the side wall of the recess, higher density can be achieved. Using a process equivalent to 4Mb DRAM,
If the width of the recess is 0.8 μm, the aperture ratio of % inch CCI: is 89%, and the aperture ratio of V2 inch CCD is 87%, which is an improvement of 9% compared to the fourth embodiment.

Moreover, the process of this embodiment is simplified compared to the fourth embodiment 11.

FIG. 6 shows a method of manufacturing the semiconductor device of the fifth embodiment shown in FIG.

(1) As shown in FIG. 6(a), a high resistance ON region 5o2 (impurity density N (1o15c:
n−') is formed by vapor phase growth, etc., and then p region 503 (1015 (N (10”)), n+ region 504
(1o"<N<1o") is formed by ablation, vapor phase growth, ion implantation, or the like. 2. Ken area 504
After forming p region 503 first, p region 503 may be formed by ion implantation.

(2) As shown in FIG. 6(b), an oxide film 601 (thickness 1 to 1000 mm) and a nitride film 602 (1000 mm thick <20 OA) are formed by thermal oxidation and CVD on the surface of the NT region 5040.
Formed by n method.

(3) As shown in FIG. 6(C), a photoresist film 603 is formed by a normal photolithography technique.

(4) As shown in FIG. 6(d), the nitride film of p602, the oxide film of 601, and then the n+ region 503 of 504 are etched by plasma etching, sputter etching, chemical etching, etc.
The p region of 502 and the n region of 502 are removed by directional etching so that the main surface and the wall surface are substantially perpendicular. Further, as a means for directional etching, alkaline etching, plasma etching, or the like is used.

(5) As shown in FIG. 6(e), an oxide film 604 is formed in the region cut in FIG. 6(d) by thermal oxidation or the like.

(6) As shown in Figure 6 (0), after forming the photoresist 605 using the photolithography technique described in (4), the oxide film 604 at the bottom of the incision is removed by the directional etching described in (4). Remove.

(7) After removing the photoresist 605 as shown in FIG. 6 (g-1), in the step (6), a p region (N) 1o20 c of 606 is added to the area where the oxide film 604 was removed.
, -5) are formed by diffusion or ion implantation. Thereafter, an oxide film 604' is formed by thermal oxidation or the like.

At this time, the GG' sectional view in Figure 6 (g-1) is shown in Figure 6 (g-1).
-2).

(8) As shown in FIG. 6), a photoresist film 607 is formed by a conventional photolithography technique.

(9) As shown in FIG. 6(1), using the step (4), the n-region 502 is removed halfway through by directional etching so that the main surface and wall surface are substantially perpendicular.

(10) As shown in FIG. 6(j-1), an oxide film 608 is formed in the region cut in FIG. 6(i) by thermal oxidation or the like. A sectional view taken along line J-J' in FIG. 6 (j-1) is shown in FIG. 6 (C-2).

(11) Figure 6 (k-1), (k-2), (k
-3) (However, the K-K' sectional view of the same figure (k-1) is the same figure (k-2), and the L = L' sectional view of the same figure (k-1) is the same figure (k-3) ), a first polysilicon layer 09 is embedded in the cut portion corresponding to the n region 502. For example, after coating the entire surface with polyimide, forming a photoresist, patterning it, etching the polyimide in the area where the first polysilicon layer 09 is to be buried, and then applying the first polysilicon layer 09 by sputtering or CVD. It is a good idea to embed.

(12) Figure 6 (β-1), (β-2), (7!-3)
As shown in FIG. 3, the first polysilicon layer 09' is again formed to have the thickness of the p region 503. The steps may be similar to those shown in (11). After this, the oxide film 61 is formed by thermal oxidation or the like.
form 0.

(13) Figure 6 (m-1), (m-2), (m
As shown in -3), the second polysilicon layer 11 is embedded in the remaining cut portion using the step (11).

(14) Figure 6 (n-1'), (n-2), (n
As shown in FIG. 5(-3), a second poly7-lico 7611' is again formed to the thickness of the p-region 503, and then polyimide is applied as an insulator over the entire surface by thermal oxidation or the like.
The cap imaging devices shown in 2L) to (6) can be manufactured.

Furthermore, as the photoelectric conversion section of the CCD image pickup device shown in FIG. 6, a p-type n photodiode as shown in section S in FIG. 7 may be formed. 701 is one area (N (10”
cm-'), 702 is the p+ region N> 1o19c
m-5), 703 is a metal electrode.

Also, S I T (5tat
(abbreviation for icInduction Transistor)
A phototransistor can also be formed. 801 is the p+ region of the gate 802 is the n region of the source, 803
804 is a source electrode, and 804 is a gate electrode.

Effects of the Invention As explained above, according to the present invention, by forming a COD in the concave portion, a sufficient dynamic range can be obtained with a small occupied area in the light receiving part, thereby significantly improving the sensitivity and resolution of the CCD imaging device. Improvements are possible and have great practical effects.

FIG. 1 shows a structural diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 1(a) is a plan view, FIG. The same figure (C) is a c-c' sectional view of the same figure (a), the same figure (d) is the same figure (a) OD-D
' Cross-sectional view, Figure (6) is a cross-sectional view of E-E' in Figure (2L), Figure (f) is an energy band diagram of the main operating state along the F-F' cross-section of Figure (d). , FIG. 3(g) is a sectional view taken along the line DD' in FIG. 1(a) when the present embodiment is partially modified. (in the figure) is a drive pulse diagram.

FIG. 2 shows a structural diagram of a semiconductor device according to a second embodiment of the present invention, in which e) is a plan view and (b) is a plan view.
BB' sectional view of a), the same figure (C) is CC of the same figure e)
' sectional view, the same figure ((1) is the DD' cross-sectional view of the same figure (a), the same figure (e) is the E-E' cross-sectional view of the same figure (a), the same figure (
r) is an energy band diagram of the main operating state along the FF' cross section in FIG. 2(d).

FIG. 3 shows a structural diagram of a semiconductor device according to a third embodiment of the present invention, in which (a) is a plan view, and (b) is a cross section taken along line B-B' in (&) of the same figure. The figure (C) is a sectional view taken along the line CC' in the figure (a), and the figure (d) is the cross-sectional view taken along the line D-D' in the figure (a).
The cross-sectional view (e) is a cross-sectional view taken along the line E-E' of the figure (&).

FIG. 4 shows a structural diagram of a semiconductor device according to a fourth embodiment of the invention. The same figure (C) is the same figure (IL
), the same figure (d) is a cross-sectional view of D in the same figure (2L).
-D' sectional view, the same figure (θ) is E-E' of the same figure (IL)
The cross-sectional view (f) is a cross-sectional view taken along line c-c' of (a) in the case where this embodiment is partially modified, and (g) is the cross-sectional view (
It is a (1,-G' sectional view of f). The same figure (h) is a drive pulse diagram.

FIG. 5 shows a structural diagram of a semiconductor device according to a sixth embodiment of the present invention, in which (a) is a plan view, and (b) is a B-B' of the same figure (?L). Cross-sectional view, the same figure (C) is the same figure (a)
C-C' sectional view of , the same figure (d) is D-D of the same figure (2L)
' Cross-sectional view, Figure (6) is a cross-sectional view e-e' of Figure (a), Figure (f) is a solid view showing the silicon single crystal part,
Figure Cg) is a solid diagram showing a silicon polycrystalline portion.

6(fa-) to (n) are diagrams showing a method for manufacturing a semiconductor device of the fifth embodiment, FIG. 7 is a block diagram of an embodiment having a p-type n photodiode, and FIG. 8 is SIT photo
FIG. 9 is a block diagram of a conventional COD imaging device, FIG. 10 is a sectional view of a pixel in FIG. 9, and FIG. 11 is a graph showing the correspondence between DRAM and imaging device. .

101.201.301.401.501 ・-・・p
Base semiconductor substrate, 102 , 203 , 304 , 405
゜506... Insulating film, 103 Old... First polysilicon, 104... Second polysilicon,
1o6゜107.205.206.305.306.4
11°511.511'...Charge transfer region.

Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure (h) % 4IΣI Figure 5 Figure 6 Figure 6 Figure 6 (J-1 (j-2 +
[7J”, Qf7on733 No. 814 Fig. 9

Claims (6)

[Claims] (1) A plurality of transfer gate electrodes are formed on the surface of a recess long in one direction formed in a high-resistance semiconductor layer via an insulating film, and a charge transfer region is formed in the semiconductor layer around the recess in the main operating state. A semiconductor device characterized by: (2) A patent claim characterized in that a blocking separation region for the charge transfer region is formed in the semiconductor layer directly under the recess, and two charge transfer regions are formed in the semiconductor layer under the sidewall of the recess in the main operating state. The semiconductor device according to scope (1). (3) A semiconductor according to claim (1), characterized in that a plurality of photoelectric conversion regions are provided on the surface of the high-resistance semiconductor layer, and a readout gate region is provided between the charge transfer region and the charge transfer region. Device. (4) The semiconductor device according to claim (3), wherein the photoelectric conversion region has a second recess. (5) A first step of forming a high resistance semiconductor layer of a second conductivity type, a semiconductor layer of a first conductivity type, and a semiconductor layer of a second conductivity type on a semiconductor substrate of a first conductivity type; a second step of forming a recess from the surface of the semiconductor layer of the mold, the side surface being substantially perpendicular to the surface and exposing the high-resistance semiconductor layer; a third step of forming an insulating film on the surface of the recess; a fourth step of forming a transfer gate electrode corresponding to the high-resistance semiconductor layer in the recess. (6) Claim (5) characterized in that the second step of forming the recess includes a step of forming a low resistance region of the first conductivity type after forming the recess reaching the semiconductor substrate. A method for manufacturing a semiconductor device according to section 1.