JPH0513267A - Manufacture of laminated capacitor - Google Patents

Manufacture of laminated capacitor

Info

Publication number
JPH0513267A
JPH0513267A JP16039391A JP16039391A JPH0513267A JP H0513267 A JPH0513267 A JP H0513267A JP 16039391 A JP16039391 A JP 16039391A JP 16039391 A JP16039391 A JP 16039391A JP H0513267 A JPH0513267 A JP H0513267A
Authority
JP
Japan
Prior art keywords
laminated
laminated body
capacitor
body block
grooves
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16039391A
Other languages
Japanese (ja)
Inventor
Yukio Hatanaka
幸雄 畑中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP16039391A priority Critical patent/JPH0513267A/en
Publication of JPH0513267A publication Critical patent/JPH0513267A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a smaller-sized laminated capacitor which is capable of controlling the length of a gap region between external electrodes with high accuracy and providing excellent reliability. CONSTITUTION:There is provided a laminated body block 11 in which a plurality of laminated capacitor parts 17 to 20 are laid out horizontally separated with a specified span. Grooves 21 to 25 are formed on the laminated body capacitor 11 in such a fashion that the laminated capacitors parts 17 to 20 may be divided by using the grooves. Conductive films 21 and 25 for external electrodes are formed all over both main sides of the laminated body block 11. The laminated body block 11 is cut along the sides of the grooves 21 to 25 so that a pair of external electrode-to-external electrode gap regions may be formed by the use of the cut plane. The above processes constitute the manufacturing process of the laminated capacitor according to the present invention.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、積層コンデンサの製造
方法に関し、特に、一対の外部電極間のギャップ領域を
正確に形成し得る工程を備えた積層コンデンサの製造方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer capacitor, and more particularly to a method for manufacturing a multilayer capacitor including a step capable of accurately forming a gap region between a pair of external electrodes.

【0002】[0002]

【従来の技術】図6に、従来の積層コンデンサを断面図
で示す。積層コンデンサ1は、誘電体セラミックスより
なる焼結体2内に複数の内部電極3を誘電体セラミック
層を介して重なり合うように配置した構造を有する。そ
して、焼結体2の両端面には、一対の外部電極4,5が
形成されている。積層コンデンサ1では、内部電極3の
積層数を増大させることにより小型・大容量のコンデン
サを構成することができる。
2. Description of the Related Art FIG. 6 is a sectional view showing a conventional multilayer capacitor. The multilayer capacitor 1 has a structure in which a plurality of internal electrodes 3 are arranged in a sintered body 2 made of a dielectric ceramic so as to overlap each other with a dielectric ceramic layer interposed therebetween. A pair of external electrodes 4 and 5 are formed on both end surfaces of the sintered body 2. In the multilayer capacitor 1, it is possible to configure a small-sized and large-capacity capacitor by increasing the number of laminated internal electrodes 3.

【0003】しかしながら、他の電子部品と同様に、積
層コンデンサ1においても、より一層の小型化が求めら
れており、それに従ってより小さな焼結体2を用いた積
層コンデンサ1が生産されている。しかしながら、より
小さな焼結体2を用いた場合、外部電極4,5間のギャ
ップ領域の長さdが小さくなり、外部電極4,5間で短
絡が生じる恐れがあった。
However, like other electronic components, the multilayer capacitor 1 is required to be further downsized, and accordingly, the multilayer capacitor 1 using the smaller sintered body 2 is produced. However, when the smaller sintered body 2 is used, the length d of the gap region between the external electrodes 4 and 5 becomes small, which may cause a short circuit between the external electrodes 4 and 5.

【0004】上記短絡を防止するには、ギャップ領域の
長さdを正確に制御すればよい。しかしながら、外部電
極4,5の形成は、一般に、ディッピング法により導電
ペーストを塗布・焼き付けることにより行われている。
従って、外部電極4,5の焼結体2の側面へのかぶり部
分4a,5aのかぶり深さを正確に制御することは非常
に困難であった。
In order to prevent the short circuit, the length d of the gap region may be accurately controlled. However, the external electrodes 4 and 5 are generally formed by applying and baking a conductive paste by a dipping method.
Therefore, it is very difficult to accurately control the fog depth of the fog portions 4a and 5a on the side surface of the sintered body 2 of the external electrodes 4 and 5.

【0005】[0005]

【発明が解決しようとする課題】上記のように、従来の
積層コンデンサ1では、外部電極4,5間のギャップ領
域の長さdを正確に制御することができないため、小型
化に限界があった。他方、図7に示す単板型のコンデン
サ6では、誘電体板7にレジストを塗布した後、電極形
成を行い、しかる後、エッチングにより上記レジストを
除去することにより電極8,9間にギャップ領域10
a,10bを正確に形成している。従って、このような
方法を積層コンデンサ1の製造方法を適用すれば、外部
電極4,5間のギャップ領域の長さdを正確に制御し得
るとも考えられる。
As described above, in the conventional multilayer capacitor 1, the length d of the gap region between the external electrodes 4 and 5 cannot be accurately controlled, so there is a limit to miniaturization. It was On the other hand, in the single-plate type capacitor 6 shown in FIG. 7, the dielectric plate 7 is coated with a resist, electrodes are formed, and then the resist is removed by etching to form a gap region between the electrodes 8 and 9. 10
a and 10b are accurately formed. Therefore, it is considered that the length d of the gap region between the external electrodes 4 and 5 can be accurately controlled by applying such a method to the manufacturing method of the multilayer capacitor 1.

【0006】しかしながら、上記のような電極形成方法
を積層コンデンサの製造方法に適用した場合には、焼結
体2が非常に小さいため、高精度にレジストを印刷する
ことができず、従ってギャップ領域の長さdを正確に制
御することはできない。また、レジストの塗布・エッチ
ングに際して用いられる溶剤により、積層コンデンサ、
特に内部電極3に悪影響を与え、信頼性が劣化する恐れ
がある。さらに、所定の部分へのレジスト塗布方法とし
ては、積層コンデンサ1個毎にレジストを塗布する方
法、並びにマザーの積層体にマスクを用いて一度に塗布
する方法が考えられるが、いずれの方法を採用したとし
ても、レジストの塗布に時間及び作業コストがかかり、
積層コンデンサのコストが非常に高くつくという問題も
ある。
However, when the electrode forming method as described above is applied to the method for manufacturing a multilayer capacitor, the sintered body 2 is very small, so that the resist cannot be printed with high precision, and therefore the gap region is formed. It is not possible to precisely control the length d of. Also, depending on the solvent used for coating and etching the resist, the multilayer capacitor,
In particular, the internal electrodes 3 may be adversely affected and the reliability may be deteriorated. Further, as a method of applying a resist to a predetermined portion, a method of applying a resist for each laminated capacitor and a method of applying a resist to a mother laminated body at a time using a mask can be considered, but either method is adopted. Even so, it takes time and work cost to apply the resist,
There is also a problem that the cost of the multilayer capacitor is very high.

【0007】本発明の目的は、外部電極間のギャップ領
域の長さを正確に制御することができ、従って、より一
層小型でかつ信頼性に優れた積層コンデンサを製造し得
る方法を提供することにある。
An object of the present invention is to provide a method capable of accurately controlling the length of the gap region between the external electrodes, and thus manufacturing a smaller and more reliable multilayer capacitor. It is in.

【0008】[0008]

【課題を解決するための手段】本発明の積層コンデンサ
の製造方法は、厚み方向において複数の内部電極が誘電
体セラミック層を介して対向するように配置された複数
の積層コンデンサ部分が少なくとも横方向に所定距離を
隔てて並べられた積層体ブロックを用意する工程と、横
方向に並べられた積層コンデンサ部分を分割するように
前記積層体ブロックに溝を形成し、該溝の第1,第2の
側面にそれぞれ一方電位に接続される内部電極を露出さ
せる工程と、前記積層体ブロックの両主面の全面に外部
電極用の導電膜を形成する工程と、前記積層体ブロック
を前記溝の第1,第2の側面に沿って切断することによ
り、切断面によって一対の外部電極間のギャップ領域が
形成されている積層コンデンサを得る工程とを備えるこ
とを特徴とする。
According to a method of manufacturing a multilayer capacitor of the present invention, a plurality of multilayer capacitor portions in which a plurality of internal electrodes are opposed to each other in a thickness direction with a dielectric ceramic layer therebetween are at least laterally arranged. And a groove is formed in the laminated body block so as to divide the laterally arranged laminated capacitor portion, and the first and second grooves of the groove are formed. Exposing the internal electrodes connected to one of the potentials on the side surfaces of the laminated body block, forming a conductive film for external electrodes on both main surfaces of the laminated body block, and forming the laminated body block in the groove 1, a step of obtaining a multilayer capacitor in which a gap area between a pair of external electrodes is formed by the cut surface by cutting along the first and second side surfaces.

【0009】[0009]

【作用】上記積層体ブロックを得た後に両主面の全面に
外部電極用の導電膜を形成し、上記溝の第1,第2の側
面に沿って切断することにより個々の積層コンデンサ部
分の一対の外部電極が形成されると共に、切断面によっ
て外部電極間のギャップ領域が形成される。従って、上
記溝をある程度正確に形成さえすれば、切断によって形
成される面の積層体ブロックの厚み方向における寸法を
正確に制御することができるため、一対の外部電極間の
ギャップ領域の長さを正確に制御することができる。
After the laminated body block is obtained, conductive films for external electrodes are formed on the entire surfaces of both main surfaces, and cut along the first and second side surfaces of the groove to form individual laminated capacitor portions. A pair of external electrodes are formed, and the cut surface forms a gap region between the external electrodes. Therefore, as long as the groove is formed with a certain degree of accuracy, the dimension of the surface formed by cutting in the thickness direction of the laminated body block can be accurately controlled, so that the length of the gap region between the pair of external electrodes can be reduced. It can be controlled precisely.

【0010】[0010]

【実施例の説明】以下、本発明の一実施例の製造方法を
図面を参照しつつ説明する。まず、図2に示す積層体ブ
ロック11を用意する。積層体ブロック11は、複数枚
のセラミックグリーンシートを内部電極材料を介して積
層し、厚み方向に圧着・焼成することにより構成されて
いる。すなわち、積層体ブロック11内には、それぞれ
複数枚の内部電極12〜16がセラミック層を介して重
なり合うように配置されている。また、複数の内部電極
12〜16は、積層体ブロック11の一方端面11aか
ら他方端面11bに至るように形成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing method according to an embodiment of the present invention will be described below with reference to the drawings. First, the laminated body block 11 shown in FIG. 2 is prepared. The laminated body block 11 is formed by laminating a plurality of ceramic green sheets with an internal electrode material interposed therebetween and press-bonding and firing in the thickness direction. That is, in the laminated body block 11, a plurality of internal electrodes 12 to 16 are arranged so as to overlap each other with the ceramic layers interposed therebetween. Further, the plurality of internal electrodes 12 to 16 are formed so as to extend from the one end surface 11 a of the laminated body block 11 to the other end surface 11 b.

【0011】複数の内部電極12と、複数の内部電極1
3とは、互いに間挿し合うようにセラミック層を介して
積層されており、該複数の内部電極12と複数の内部電
極13とが重なりあっている部分に、第1の積層コンデ
ンサ部分17が構成されている。同様に、複数の外部電
極13と複数の内部電極14とがセラミック層を介して
重なり合っている部分に第2の積層コンデンサ部分18
が、複数の内部電極14と複数の内部電極15とが挟ま
れている部分に第3の積層コンデンサ部分19が、複数
の内部電極15と複数の内部電極16とが重なり合って
いる部分に第4の積層コンデンサ部分20が構成されて
いる。上記積層体ブロック11は、従来より周知のセラ
ミックグリーンシートを利用した積層コンデンサの製造
方法を用いて得ることができる。
A plurality of internal electrodes 12 and a plurality of internal electrodes 1
3 is laminated via a ceramic layer so as to be interleaved with each other, and the first laminated capacitor portion 17 is formed in a portion where the plurality of internal electrodes 12 and the plurality of internal electrodes 13 overlap each other. Has been done. Similarly, the second multilayer capacitor portion 18 is provided at a portion where the plurality of outer electrodes 13 and the plurality of inner electrodes 14 are overlapped with each other with the ceramic layer interposed therebetween.
However, the third multilayer capacitor portion 19 is provided in a portion where the plurality of internal electrodes 14 and the plurality of internal electrodes 15 are sandwiched, and the third multilayer capacitor portion 19 is provided in a portion where the plurality of internal electrodes 15 and the plurality of internal electrodes 16 are overlapped with each other. The multilayer capacitor part 20 of FIG. The laminated body block 11 can be obtained by a conventionally known method for manufacturing a laminated capacitor using a ceramic green sheet.

【0012】次に、図3に示すように、積層体ブロック
11に複数本の溝21〜25を端面11aから端面11
bに至るように形成する。溝21〜23は、積層体ブロ
ック11の上面側から形成されており、他方、溝24,
25は下面側から形成されている。これらの溝21〜2
5は、図2に示した積層コンデンサ部分17〜20間を
分割する幅に形成されており、各溝21〜25の内側面
には、上述した内部電極が露出されている。例えば、溝
24を代表して説明すると、溝24の第1の側面24a
には、第1の積層コンデンサ部分17における内部電極
13が露出され、第2の側面24bには、第2の積層コ
ンデンサ部分18における内部電極13が露出される。
このように、溝21〜25の内側面には、上述した内部
電極が露出されることになるため、第1〜第4の積層コ
ンデンサ部分17〜20において一方電位に接続される
ことになる内部電極が溝21〜25の側面に露出される
ことになる。
Next, as shown in FIG. 3, a plurality of grooves 21 to 25 are formed in the laminate block 11 from the end face 11a to the end face 11.
It is formed so as to reach b. The grooves 21 to 23 are formed from the upper surface side of the laminated body block 11, while the grooves 24,
25 is formed from the lower surface side. These grooves 21-2
5 is formed to have a width that divides the multilayer capacitor portions 17 to 20 shown in FIG. 2, and the above-mentioned internal electrodes are exposed on the inner side surfaces of the grooves 21 to 25. For example, to describe the groove 24 as a representative, the first side surface 24 a of the groove 24 is described.
The internal electrode 13 in the first multilayer capacitor portion 17 is exposed to the inside, and the internal electrode 13 in the second multilayer capacitor portion 18 is exposed to the second side surface 24b.
As described above, since the internal electrodes described above are exposed on the inner side surfaces of the grooves 21 to 25, the internal portions that are connected to one potential in the first to fourth multilayer capacitor portions 17 to 20. The electrodes will be exposed on the side surfaces of the grooves 21 to 25.

【0013】なお、溝21〜25の形成は、ダイシング
・ソーまたはレーザー等を用いることにより、高精度に
行い得る。また、図3から明らかなように、溝21〜2
3が積層体ブロック11の上面側から、溝24,25が
下面側から形成されており、これらは交互に積層体ブロ
ック11の上面側及び下面側から形成されているため、
溝21〜25の形成後に積層体ブロック11を焼成する
場合にあっては積層体ブロック11におけるソリの発生
を抑制することができる。
The grooves 21 to 25 can be formed with high accuracy by using a dicing saw or a laser. Further, as is clear from FIG. 3, the grooves 21 to 2
3 is formed from the upper surface side of the laminated body block 11 and the grooves 24 and 25 are formed from the lower surface side, and these are formed alternately from the upper surface side and the lower surface side of the laminated body block 11,
When the laminated body block 11 is fired after the grooves 21 to 25 are formed, warpage in the laminated body block 11 can be suppressed.

【0014】次に、上述した積層体ブロック11の上面
及び下面の全面に図1に示すように導電膜26,27を
形成する。導電膜26,27は、スパッタ、蒸着または
無電界メッキ等の適宜方法により形成することができ
る。導電膜26,27は、積層体ブロック11の上面及
び下面の全面に形成されるため、上述した溝21〜25
の側面にも形成されることになる。
Next, as shown in FIG. 1, conductive films 26 and 27 are formed on the entire upper surface and lower surface of the laminate block 11 described above. The conductive films 26 and 27 can be formed by an appropriate method such as sputtering, vapor deposition or electroless plating. Since the conductive films 26 and 27 are formed on the entire upper surface and lower surface of the laminated body block 11, the grooves 21 to 25 described above are formed.
Will also be formed on the side surface of.

【0015】次に、図1の一点鎖線Bに沿って積層体ブ
ロック11を切断する。すなわち、積層体ブロック11
を溝21〜25の側面に沿って切断する。なお、溝21
〜25の側面に沿ってとは、図1に示すように溝の側面
上の上記導電膜26,27の表面に沿って、という意味
である。このようにして、図4に示す積層体28を多数
得ることができる。なお、積層体28は、上述した第1
の積層コンデンサ部分17に相当する部分を切断するこ
とより得られたものである。図4の積層体28では、上
記切断によって形成された切断面29,30が露出され
ている。
Next, the laminate block 11 is cut along the chain line B in FIG. That is, the laminated body block 11
Is cut along the side surfaces of the grooves 21 to 25. The groove 21
"Along the side surfaces of .about.25" means along the surfaces of the conductive films 26 and 27 on the side surfaces of the groove as shown in FIG. In this way, many laminated bodies 28 shown in FIG. 4 can be obtained. In addition, the laminated body 28 is the above-mentioned first
It is obtained by cutting a portion corresponding to the laminated capacitor portion 17 of. In the laminated body 28 of FIG. 4, the cut surfaces 29 and 30 formed by the above cutting are exposed.

【0016】次に、図4に示した積層体28を図4の一
点鎖線Xに沿って切断し、個々の積層コンデンサ用積層
体を得、図5に示す積層コンデンサ31を得ることがで
きる。積層コンデンサ31では、焼結体32内におい
て、複数の内部電極33,34がセラミック層を介して
積層されている。この複数の内部電極33は、図2に示
した内部電極12に基づくものであり、複数の内部電極
34は、図2に示した内部電極13に基づくものであ
る。
Next, the laminated body 28 shown in FIG. 4 is cut along the alternate long and short dash line X in FIG. 4 to obtain individual laminated body for laminated capacitor, and the laminated capacitor 31 shown in FIG. 5 can be obtained. In the multilayer capacitor 31, a plurality of internal electrodes 33, 34 are laminated in a sintered body 32 with ceramic layers interposed therebetween. The plurality of internal electrodes 33 are based on the internal electrode 12 shown in FIG. 2, and the plurality of internal electrodes 34 are based on the internal electrode 13 shown in FIG.

【0017】そして、複数の内部電極33は、外部電極
35に電気的に接続されており、複数の内部電極34は
外部電極36に電気的に接続されている。外部電極35
は、図1に示した導電膜26に基づくものであり、外部
電極36は導電膜27に基づくものである。得られた積
層コンデンサ31では、一対の外部電極35,36間の
ギャップ領域の長さdは、前述した図4の切断面29,
30の幅W(図4参照)により決定される。従って、本
実施例の製造方法では、前述した溝21〜25(図1及
び図3参照)の深さを正確に制御しさえすれば、一対の
外部電極35,36間のギャップ領域の長さdを正確に
制御し得ることが分かる。他方、溝21〜25の形成
は、ダイシング・ソーやレーザー等により高精度に行い
得ることは前述した通りである。
The plurality of inner electrodes 33 are electrically connected to the outer electrodes 35, and the plurality of inner electrodes 34 are electrically connected to the outer electrodes 36. External electrode 35
Are based on the conductive film 26 shown in FIG. 1, and the external electrodes 36 are based on the conductive film 27. In the obtained multilayer capacitor 31, the length d of the gap region between the pair of external electrodes 35 and 36 is determined by the above-described cut surface 29 of FIG.
It is determined by the width W of 30 (see FIG. 4). Therefore, according to the manufacturing method of the present embodiment, the length of the gap region between the pair of external electrodes 35 and 36 may be controlled by accurately controlling the depths of the grooves 21 to 25 (see FIGS. 1 and 3). It can be seen that d can be accurately controlled. On the other hand, as described above, the grooves 21 to 25 can be formed with high accuracy by using a dicing saw, a laser, or the like.

【0018】よって、本実施例によれば、積層体ブロッ
ク11の厚みを薄くし、より小型の積層コンデンサ31
を得ようとした場合であっても、外部電極35,36間
のギャップ領域の長さdを高精度に制御することができ
るため、短絡の生じ難い信頼性に優れた小型の積層コン
デンサを得ることができる。
Therefore, according to the present embodiment, the thickness of the laminated body block 11 is reduced and the smaller laminated capacitor 31 is provided.
Even when trying to obtain, since the length d of the gap region between the external electrodes 35 and 36 can be controlled with high accuracy, a small multilayer capacitor which is less likely to cause a short circuit and has excellent reliability is obtained. be able to.

【0019】なお、上述した実施例では、積層体ブロッ
ク11として、図2のA方向にすなわち横方向に複数の
積層コンデンサ部分17〜20が並べられているだけで
なく、端面11aと端面11bとの間においても複数の
積層コンデンサ部分が並べられたものを用意したが、端
面11a,11b間には1個の積層コンデンサ部分が配
置される大きさの積層体ブロックを用いてもよい。その
場合には、図1のように導電膜を形成した後、溝21〜
25に沿って切断するだけで、直ちに個々の積層コンデ
ンサ用の積層体を得ることができる。
In the above-described embodiment, the laminated body block 11 includes not only a plurality of laminated capacitor portions 17 to 20 arranged side by side in the direction A of FIG. 2, that is, the lateral direction, but also an end face 11a and an end face 11b. Although a plurality of laminated capacitor portions are also arranged between the end faces 11a and 11b, a laminated body block having a size in which one laminated capacitor portion is arranged may be used. In that case, after forming the conductive film as shown in FIG.
The laminate for individual multilayer capacitors can be immediately obtained by simply cutting along 25.

【0020】[0020]

【発明の効果】以上のように、本発明によれば、積層体
ブロックに形成された溝の側面に沿って積層体ブロック
を切断することにより、一対の外部電極間のギャップ領
域の寸法が高精度に形成されるため、外部電極間の短絡
を確実に防止することができると共に、より小型であ
り、かつ信頼性に優れた積層コンデンサを得ることがで
きる。
As described above, according to the present invention, by cutting the laminate block along the side surface of the groove formed in the laminate block, the dimension of the gap region between the pair of external electrodes is increased. Since the electrodes are accurately formed, a short circuit between external electrodes can be reliably prevented, and a multilayer capacitor that is smaller and has high reliability can be obtained.

【0021】また、本発明では、上記外部電極間のギャ
ップ領域を正確に形成するために、単に積層体ブロック
に溝を形成しているものに過ぎないため、マスクやレジ
スト材等の高価な材料を必要とせず、しかも能率よく行
い得るため、小型でかつ信頼性に優れた積層コンデンサ
を安価に提供することができる。
Further, in the present invention, since the groove is simply formed in the laminated body block in order to accurately form the gap region between the external electrodes, an expensive material such as a mask or a resist material is used. Since it can be carried out efficiently without the need for a capacitor, it is possible to provide a small-sized and highly reliable multilayer capacitor at low cost.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の製造方法において導電膜が
形成された積層体ブロックを示す正面図。
FIG. 1 is a front view showing a laminated body block on which a conductive film is formed by a manufacturing method according to an embodiment of the present invention.

【図2】実施例で用意される積層体ブロックを示す斜視
図。
FIG. 2 is a perspective view showing a laminated body block prepared in an example.

【図3】積層体ブロックに溝を形成した状態を示す斜視
図。
FIG. 3 is a perspective view showing a state in which a groove is formed in the laminated body block.

【図4】積層体ブロックを溝の側面に切断することによ
って得られた積層体を示す斜視図。
FIG. 4 is a perspective view showing a laminated body obtained by cutting the laminated body block on the side surface of the groove.

【図5】本発明の一実施例により得られた積層コンデン
サを示す斜視図。
FIG. 5 is a perspective view showing a multilayer capacitor obtained according to an example of the present invention.

【図6】従来の積層コンデンサを示す断面図。FIG. 6 is a sectional view showing a conventional multilayer capacitor.

【図7】従来の単板型のコンデンサを示す断面図。FIG. 7 is a cross-sectional view showing a conventional single plate type capacitor.

【符号の説明】[Explanation of symbols]

11…積層体ブロック 12〜16…内部電極 17〜20…第1〜第4の積層コンデンサ部分 21〜25…溝 26,27…導電膜 31…積層コンデンサ 33,34…内部電極 35,36…外部電極 d…外部電極間のギャップ領域の長さ 11 ... Laminated block 12-16 ... Internal electrodes 17-20 ... First to fourth laminated capacitor portions 21-25 ... Grooves 26, 27 ... Conductive film 31 ... Laminated capacitors 33, 34 ... Internal electrodes 35, 36 ... External Electrode d ... Length of gap area between external electrodes

Claims (1)

【特許請求の範囲】 【請求項1】 厚み方向において複数の内部電極が誘電
体セラミック層を介して対向するように配置された複数
の積層コンデンサ部分が、少なくとも横方向に所定距離
を隔てて並べられた積層体ブロックを用意する工程と、 横方向に並べられた前記積層コンデンサ部分を分割する
ように前記積層体ブロックに溝を形成し、該溝の第1,
第2の側面にそれぞれ一方電位に接続されることが予定
されている内部電極を露出させる工程と、 前記積層体ブロックの両主面の全面に、外部電極用の導
電膜を形成する工程と、 前記積層体ブロックを前記溝の第1,第2の側面に沿っ
て切断することにより、切断面によって一対の外部電極
間のギャップ領域が形成された複数個の積層コンデンサ
を得る工程とを備えることを特徴とする、積層コンデン
サの製造方法。
Claim: What is claimed is: 1. A plurality of laminated capacitor portions, wherein a plurality of internal electrodes are arranged so as to face each other with a dielectric ceramic layer interposed therebetween in the thickness direction. And a groove is formed in the laminated body block so as to divide the laminated capacitor portions arranged in the lateral direction, and the first and second grooves of the groove are formed.
Exposing the internal electrodes, which are each expected to be connected to one potential, to the second side surface, and forming a conductive film for external electrodes on both main surfaces of the laminate block. Cutting the laminated body block along the first and second side surfaces of the groove to obtain a plurality of laminated capacitors in which a gap area between a pair of external electrodes is formed by the cut surface. And a method of manufacturing a multilayer capacitor.
JP16039391A 1991-07-01 1991-07-01 Manufacture of laminated capacitor Pending JPH0513267A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16039391A JPH0513267A (en) 1991-07-01 1991-07-01 Manufacture of laminated capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16039391A JPH0513267A (en) 1991-07-01 1991-07-01 Manufacture of laminated capacitor

Publications (1)

Publication Number Publication Date
JPH0513267A true JPH0513267A (en) 1993-01-22

Family

ID=15713989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16039391A Pending JPH0513267A (en) 1991-07-01 1991-07-01 Manufacture of laminated capacitor

Country Status (1)

Country Link
JP (1) JPH0513267A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011029646A (en) * 1999-04-20 2011-02-10 Seagate Technology Llc Electrode patterning for differential pzt activator
KR20190053327A (en) * 2017-11-10 2019-05-20 삼성전기주식회사 Embedded multilayer ceramic electronic component, manufacturing method thereof and print circuit board having embedded multilayer ceramic electronic component

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011029646A (en) * 1999-04-20 2011-02-10 Seagate Technology Llc Electrode patterning for differential pzt activator
KR20190053327A (en) * 2017-11-10 2019-05-20 삼성전기주식회사 Embedded multilayer ceramic electronic component, manufacturing method thereof and print circuit board having embedded multilayer ceramic electronic component

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