JPH05130524A - Timing generator - Google Patents

Abstract

PURPOSE:To reduce a switching noise by providing a shift register which starts an operation based on the input of a reference signal and outputs signals with prescribed width sequentially from plural output terminals based on the input of a clock signal. CONSTITUTION:The operation of the shift register 1 can be started based on the input of the reference signal Sr, and output signals with prescribed pulse width are outputted from the plural output terminals QA-QH based on the clock signal CLK inputted afterward. Meanwhile, signals P outputted from the selected output terminals phic, phiF of the register 1 are supplied to the set side input terminal phiS and the reset side input terminal phiR of an FF circuit 2 as a set signal Ps and a reset signal Pr, respectively. Therefore, a timing pulse signal phiout with desired pulse width can be outputted from the output terminal Po of the FF circuit 2. Change in the rise and fall of the signal P occurs only at the neighboring two pairs of output terminals, which reduces the switching noise.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing generator, and more particularly to generating various timing pulses in a CCD solid-state image pickup device, such as a clamp pulse signal for a clamp circuit and a drive pulse signal for driving a CCD solid-state image pickup device. It is suitable for use in a timing generator.

[0002]

2. Description of the Related Art Conventionally, for example, a synchronous hexadecimal counter has been used as a timing generator in a CCD solid-state image pickup device. The hexadecimal counter is composed of four binary counter, as shown in FIG. 12, based on the input of the clock signal CLK, the respective pulse from the output terminal Q _A to Q _D of the respective binary counter in the hexadecimal counter 21 It outputs output signals with different cycles, and is configured such that when 16 clock pulses are input, the states of the binary counters return to their original states. This Figure 1
2 shows the timing of the clock signal CLK supplied to the hexadecimal counter 21 and the output timing of the pulse signal from each of the output terminals Q _{A to} Q _D based on this clock signal CLK.

The hexadecimal counter 21 counts clock pulses to generate a timing pulse signal supplied to the CCD solid-state image pickup device. For example, a timing pulse signal having a desired pulse width is obtained by setting a high level when 4 is counted and a low level when 9 is counted.

[0004]

In the counter 21, the state of the binary counter related to the first output terminal Q _A changes every time a clock pulse is input, and the state of the binary counter related to the second output terminal Q _B changes. Changes at every input of an even number of clock pulses, and the third output terminal Q _C
The state of the binary counter with respect to the input of four clock pulses changes, and the state of the binary counter with respect to the fourth output terminal Q _D changes with the input of eight clock pulses.

In particular, at the time of input of four and twelve of the clock pulse, the state of the binary counters for the first to third output terminals Q _A to Q _C is changed at a time, further 8
The states of the binary counters with respect to all the output terminals Q _{A to} Q _D change at the time of the input of the 16th and 16th clock pulses.

Therefore, switching noise (through current) generated due to the change of the state of the binary counter is generated.
Becomes large, and this large switching noise is periodically generated. FIG. 13 shows a waveform in which the magnitude of switching noise (through current) is measured using a 4-bit counter as an example. From this figure, it can be seen that a large through current of −5 mA or more is periodically generated.

Since the timing generator for generating the drive pulse for the high resolution CCD solid-state image pickup device is required to have a high operation rate, it is necessary to form the timing generator by a CMOS circuit designed for high speed operation. However, there is a problem that the switching noise increases as the operating rate is increased by the CMOS process.

On the other hand, the CCD solid-state imaging device has a correlated double sampling circuit (hereinafter simply referred to as CDS) in order to suppress KTC noise and 1 / f noise generated from the MOS circuit at the output stage of the CCD solid-state imaging device. Is used,
In this CDS, at the stage of sampling and holding the image pickup signal from the CCD solid-state image pickup device, the switching noise from the counter 21 is superposed on the power source or the like, so that accurate correlated double sampling cannot be performed. is there.

Therefore, conventionally, in order to make it less susceptible to the switching noise from the counter 21, the CC
The counter 21 is stopped in the transfer effective area (screen display area) of the CCD in the D solid-state image pickup device, and the counter 21 is operated in the invalid transfer area (optical black area) of the CCD.

That is, the timing pulse signal from the counter is used as the clamp pulse of the clamp circuit for clamping the optical black. However, even in this case, switching noise from the counter is superimposed on the clamped optical black, and as a result, the black of the actual screen display portion and the optical black are different from each other, and so-called black shift occurs. Problem arises.

Therefore, conventionally, various noise suppression circuits are required in order to suppress the switching noise from the counter 21, and therefore, design is made against fluctuation factors such as substrate wiring capacitance, decoupling capacitance, and manufacturing variation of LSI. It was difficult to realize stable image quality reproduction because the degree of freedom was reduced.

The present invention has been made in view of the above problems, and an object thereof is to reduce switching noise and increase the degree of freedom in designing with respect to process fluctuation factors. The purpose of the present invention is to provide a timing generator that can realize stable reproduction of image quality when used in a CCD solid-state image sensor, for example.

[0013]

The timing generator A of the present invention starts its operation based on the input of the reference signal Sr, and based on the input of the clock signal CLK, a predetermined pulse width t in order from a plurality of output terminals. Of the timing generation circuit 1 for outputting the output signal P of the above, and two selected output terminals (for example, Q _C and Q _F ) among the plurality of output terminals of the timing generation circuit 1.
A flip-flop circuit 2 is provided in which the output signal P from each of the input signals is input as the set signal Ps and the reset signal Pr, and the timing pulse signal Po having the desired pulse width T is output from the output terminal φout.

Then, with this timing generator A, the CCD
When the clamp pulse signal CP supplied to the clamp circuit for clamping the optical black in the solid-state image sensor is created, the reference signal Sr is set to the horizontal blanking (HBL).
The timing pulse signal Po from the flip-flop circuit 2 is used as the clamp pulse signal CP.

Further, the timing generator A is used to fix the CCD.
Multiple vertical transfer pulses V in the body image sensor₁~ V_FourTo
When creating, the reference signal Sr is sent to the CCD solid-state imaging device.
Predetermined from the start of horizontal blanking (HBLK)
Output after the lapse of time.
A plurality of drop circuits 2 are arranged (2A to 2D), and timing is generated.
Of the multiple output terminals of the raw circuit 11, select every two sets
The corresponding output signals from every two sets from the output terminals
Set in a plurality of flip-flop circuits 2A to 2D respectively
Input as signal and reset signal. By this
The flip-flop circuits 2A to 2D respectively
Vertical transfer pulse V with pulse width₁~ V _FourIs output
Will be.

[0016]

According to the above-described configuration of the present invention, the operation is started based on the input of the reference signal Sr, and the output signal P having the predetermined pulse width t is sequentially output from the plurality of output terminals based on the input of the clock signal CLK. Since the timing generating circuit 1 for outputting is provided, one pulse signal P having a predetermined pulse width t is output from each output terminal during the operation period of the timing generating circuit 1. One pulse signal P is sequentially output from each output terminal.

Therefore, changes in the rising and falling of the pulse signal P are related to at most two sets of output terminals, and the switching noise generated with the changes in the pulse signal P is extremely small.

Therefore, the timing pulse signal Po output from the flip-flop circuit 2 is supplied to the clamp circuit for clamping the optical black in the CCD solid-state image sensor, for example.
When used for P, the clamped optical black does not fluctuate due to the switching noise from the timing generation circuit 1, and the black shift on the screen can be prevented.

Further, since the suppression circuit for suppressing the switching noise can be made to have a minimum circuit configuration or can be eliminated, the design freedom with respect to fluctuation factors such as substrate wiring capacitance, decoupling capacitance, and manufacturing variation of LSI. As a result, the image quality can be increased and stable image quality can be reproduced.

Further, a plurality of flip-flop circuits 2 are arranged, and the timing pulse signals output from the respective flip-flop circuits 2A to 2D are used for a plurality of vertical transfer pulses V _{1 to} V ₄ in the CCD solid-state image pickup device, for example. In such a case, switching noise will not be superimposed on the vertical transfer pulses V _{1 to} V ₄ , so that the signal charge accumulated in the light receiving portion of the CCD solid-state image pickup device can be properly transferred in the vertical direction, that is, to the horizontal register side. You can

[0021]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing a timing generator A according to the first embodiment.

As shown in the figure, the timing generator A starts its operation based on the input of the reference signal Sr supplied to the input terminal φB, and operates based on the clock signal CLK supplied to the input terminal CK. Output terminals Q _A , Q _B ...
A timing generation circuit (hereinafter, referred to as a shift register) 1 including, for example, a shift register that outputs the output signal P sequentially from Q _H, and a set side input terminal φS, a reset side input terminal φR, and a clock input terminal as input terminals. φ
And a flip-flop circuit 2 having C and having one output terminal φout.

[0023] Then, a plurality of output terminals Q _A of the shift register 1, Q _B · · · Q _H in, one output terminal that is selected arbitrarily, for example, the output terminal Q _C and the set side input of the flip-flop circuit 2 and the terminal φS is electrically connected, said plurality of output terminals Q _a, Q _B ··· Q in _H, optionally selected output terminal in the subsequent stage side of the output terminal Q _C, for example, the output terminal Q _F And the reset side input terminal φR of the flip-flop circuit 2 are electrically connected.

That is, the output signal from the selected one output terminal Q _{C of} the shift register 1 is the set signal Ps.
Is supplied to the flip-flop circuit 2, and the output signal from the other selected output terminal Q _{F of} the shift register 1 is supplied to the flip-flop circuit 2 as the reset signal Pr. The same signal as the clock signal CLK input to the shift register 1 is supplied to the clock input terminal φC of the flip-flop circuit 2.

Next, the operation of the timing generator A according to the first embodiment will be described with reference to the timing chart of FIG.

First, the shift is performed based on the input of the reference signal Sr.
Register 1 starts operation and the clock input after that
Based on the input of each clock pulse Pc of the clock signal CLK.
Number of output terminals Q_A, Q_B... Q_HOutput signal in order from
Output P. In the illustrated example, 1 after the reference signal Sr is input.
Output terminal Q based on the input of the second clock pulse Pc _A
Outputs an output signal P having a predetermined pulse width t from
It The pulse width t of this output signal P is
Set the length to the pulse period tc of the pulse pulse Pc.
It

Then, based on the input of the second clock pulse Pc, an output signal P having the above pulse width t is output from the output terminal Q _B , and then the third, fourth, ...
The output signal P having the pulse width t is output from the corresponding output terminals Q _C , Q _D, ... Based on the input of the clock pulse Pc. That is, each output terminal Q _A , Q _B ...
The output signals P having the same waveform, which are delayed from each other by the pulse period tc of the clock pulse Pc, are output from Q _H.

Then, the last eighth clock pulse P
An output signal P having the pulse width t is output from the output terminal Q _H of the final stage based on the input of c, and the output signal P is supplied to the first stage of the shift register 1 as a stop signal Ss as shown in FIG. Then, the operation of the shift register 1 is stopped.

On the other hand, the set-side input terminal φS and the reset-side input terminal φR of the flip-flop circuit 2 have third and sixth output terminals Q _C and Q of the shift register 1, respectively.
Since the output signal P output from the _F is supplied as respective set signal Ps and a reset signal Pr, from the output terminal φout of the flip-flop circuit 2, supplied during, for example, the rise of the output signal P from the output terminal Q _C, the output The timing pulse signal Po that falls when the output signal P is supplied from the terminal Q _F is taken out.

Therefore, this timing pulse signal Po
Is output at a timing delayed by 2 clocks from the input of the reference signal Sr, and its pulse width T has a length corresponding to three pulse widths t of the output signal P (that is, 3 clocks). Become.

From this, when it is desired to change the output timing of the timing pulse signal Po output from the flip-flop circuit 2, the output terminal of the shift register 1 connected to the set-side input terminal φS of the flip-flop circuit 2 is desired. If it is desired to change the pulse width T in accordance with the output timing of, the output terminal of the shift register 1 connected to the reset side input terminal φR of the flip-flop circuit 2 should be selected according to the desired pulse width. Good.

Next, one specific example of the timing generator A according to the first embodiment will be described with reference to FIGS.
The same reference numerals are given to those corresponding to FIG.

In FIG. 3, the shift register 1 is
Nine D flip-flops DFF1 to DFF9 are connected in multiple stages, and the flip-flop circuit 2 has an SR
It is composed of flip-flops.

D flip-flops DFF1 to DFF9
Is supplied with the reset signal Sr to the respective clear terminals CLR _{1 to} CLR ₉ , and the first-stage D flip-flop DFF1
The clock signal CLK is supplied to each of the clock terminals C _{2 to} C ₉ except for.

The fixed potential Vcc is supplied to the D terminal D ₁ of the first-stage D flip-flop DFF1, and its clock terminal C ₁ is output signal P ₉ from the inverted Q terminal XQ ₉ of the final-stage D flip-flop DFF9. The inversion signal (inverted by the inversion circuit 3) is supplied. The output signal P ₉ from the inverted Q terminal XQ ₁ of the first-stage D flip-flop DFF1 is supplied to the enable terminals EN of the second-stage D flip-flop DFF2 and the subsequent stages.

The second-stage D flip-flop DFF2 is D
Inversion Q of the final stage D flip-flop DFF9 is applied to the terminal D _2.
Output signal P ₉ from the terminal XQ ₉ is supplied, the inverted Q
Output signal P ₂ from the terminal XQ ₂ is supplied to the D terminal D ₃ of the third stage D flip-flop DFF3.

After the third-stage D flip-flop DFF3, the wirings have the same connection relation, and the Q terminal Q ₃ of the third-stage D flip-flop DFF3 and the D terminal D _{4 of the} fourth-stage D flip-flop DFF4 are connected. And so on
8th stage D flip-flop DFF
4, DFF5 ... DFF8 Q terminals Q ₄ , Q ₅ ...
・ Q ₈ is 5th stage, 6th stage ... 9th stage (final stage) D
The flip-flops DFF5, DFF6 ... DFF9 are connected to the respective D terminals D ₅ , D ₆ ... D ₉ .

Further, in this example, the Q terminal Q ₃ of the third-stage D flip-flop DFF3 and the set side input terminal φS of the SR flip-flop 2 are connected, and the Q-terminal Q _{6 of the} sixth-stage D flip-flop DFF6 is connected. And the reset side input terminal φR of the SR flip-flop 2 are connected. The clock signal CLK is also supplied to the clock input terminal φC of the SR flip-flop 2.

Here, the reset signal Sr is as shown in FIG.
As shown in FIG.
A reset composed of the lip flop DFF0 and the OR circuit 4.
Output from the input signal generation circuit 5. That is, this D flip
D terminal D of the pro-flop DFF0₀Is the horizontal synchronization signal H
D is supplied and clock terminal C₀To the clock signal C
LK is supplied. Also, one input terminal of the OR circuit 4
Is supplied with a horizontal sync signal HD, and the other input terminal
Inversion Q terminal XQ of D flip-flop DFF0 ₀from
The output signal Rr is supplied.

Therefore, as shown in the timing chart of FIG. 6, when the horizontal synchronizing signal HD falls and becomes horizontal blanking (HBLK), the potential of the output terminal φo of the OR circuit 4 changes from high level to low level. Since the output signal Rr from the inverted Q terminal XQ ₀ of the D flip-flop DFF0 rises at the next rising of the clock signal CLK, the potential of the output terminal φo of the OR circuit 4 also becomes high level. As a result, from the output terminal φo of the OR circuit 4, at the start of horizontal blanking (HBLK), the reset signal Sr that is at a low level for the pulse period tc of the clock signal CLK is output.

Next, the 9-stage D flip-flop DF
The operation of the shift register 1 including F1 to DFF9 and the flip-flop circuit 2 including an SR flip-flop will be described with reference to the timing chart of FIG.

First, at t1, based on the fall of the reset signal Sr, the inverted Q terminals XQ of the first-stage, second-stage and final-stage D flip-flops DFF1, DFF2 and DFF9.
The potentials of ₁ , XQ ₂ and XQ ₉ become high level. At this time, each of the second and subsequent D flip-flops DFF2 to DF
The potential of the enable terminal EN of F9 becomes high level,
Each of the second and subsequent D flip-flops DFF2 to DFF9
The input permission state of the clock signal CLK is entered.

Then, at the next time t2, the reset signal Sr rises to start the operation of the shift register 1. That is, when the clock signal CLK rises at the same time as the rising of the reset signal Sr, the potential of the inversion Q terminal XQ ₂ of the second-stage D flip-flop DFF2 becomes low level and the Q-terminal Q of the third-stage D flip-flop DFF3. The potential of ₃ becomes high level.

At the next time t3, since the clock signal CLK rises again, the potential of the Q terminal Q ₃ of the third-stage D flip-flop DFF3 becomes low level, and at the same time,
The Q terminal Q ₄ of the fourth-stage D flip-flop DFF4 becomes high level.

That is, based on the fall of the reset signal Sr, the pulse signal P ₂ having the pulse width t of the pulse period tc of the clock signal CLK is output from the inversion Q terminal XQ ₂ of the second-stage D flip-flop DFF2. Immediately after that, this time, the pulse signal P ₃ having the same pulse width t is output from the Q terminal Q ₃ of the third-stage D flip-flop DFF3.

Similarly, hereafter, t4, t5 ... t7
, 4th stage, 5th stage ... 8th stage D flip
Each Q terminal of the flops DFF4, DFF5 ... DFF8
Q_Four, Q_Five... Q₈Sequentially from the same pulse width t
Loose signal P_Four, P_Five... P ₈Is output.

Then, the eighth stage D flip-flop DFF
When the pulse signal P ₈ output from the Q terminal Q _{8 of} No. ₈ is input to the D terminal D ₉ of the final stage D flip-flop DFF9, the potential of the inverting Q terminal XQ ₉ of the final stage D flip-flop DFF9 falls. , This inverted Q terminal X
Output signal P ₉ from Q ₉ is supplied to the first stage D flip-flop DFF1 as a stop signal, the operation of the shift register 1 is stopped.

This is the final stage D flip-flop DFF.
By the potential of the inverting Q terminal XQ ₉ goes low at 9, a clock terminal C ₁ of the first-stage D flip-flop DFF1 goes high, thereby, the potential of the inverting Q terminal XQ ₁ of the first-stage D flip-flop DFF1 is low This is because the level is reached and the signal supply to the enable terminals EN of the D flip-flops DFF2 to DFF9 in the second and subsequent stages is stopped.

During the operation of the shift register 1,
Since the third stage D pulse signal P ₃ from the Q terminal Q ₃ of the flip-flop DFF3 it is supplied as a set signal Ps to the SR flip-flop 2, the pulse signal P
_{When 3} (Ps) is supplied, the potential of the output terminal φout of the SR flip-flop 2 rises.

Thereafter, the fourth and fifth D flip flow
Next D-flip on the 6th stage separated by DFF4 and DFF5.
Q terminal Q in the pro-flop DFF6₆Pulse signal from
Issue P ₆Sends the reset signal Pr to the SR flip-flop 2.
The pulse signal P₆(Pr)
, The output terminal φout of the SR flip-flop 2
Potential drops.

Therefore, from the output terminal φout of the SR flip-flop 2, the third-stage D flip-flop DFF3
Rises when the pulse signal P ₃ (Ps) is output from
The pulse signal P from the sixth-stage D flip-flop DFF6
_The timing pulse signal Po that falls when ₆ (Pr) is output is output.

In this case, this timing pulse signal Po
The pulse width T of the
The pulse signal P from the flip-flops DFF2 to DFF8₂
~ P ₈The length of three pulse widths t in
Lock length).

In this example, the timing pulse signal P
When you want to change the output timing and pulse width T of o
Is the Q terminal Q of the D flip-flops DFF2 to DFF8.
₂~ Q ₈Middle, SR flip-flop 2 set side input end
Output of one Q terminal connected to slave φS to desired output timing
D flip-flop DF
Q terminal Q of F2-DFF8₂~ Q₈Middle, reset side input
Connect one Q terminal connected to terminal φR to the desired pulse width T
You can select it according to.

According to the first embodiment, the operation is started based on the input of the reference signal Sr, and the output terminals Q _A , Q _B ... Q _{H are} sequentially operated based on the input of the clock signal CLK. since the provided shift register 1 outputs an output signal P of a predetermined pulse width t, during operation of the shift register 1, from the output terminals Q _a, Q _B ··· Q _H is
One pulse signal P having a predetermined pulse width t is output, and one pulse signal P is sequentially output from each output terminal Q _A , Q _B ... Q _H.

Therefore, changes in the rising and falling of the pulse signal P are at most only for two adjacent sets of output terminals, and the switching noise generated with the changes in the pulse signal P is extremely small. ..

FIG. 7 is a waveform diagram in which the magnitude of switching noise (through current) is measured by taking a 4-bit shift register as an example. The maximum through current is -1.2 mA.
It is a through current of a certain degree. From this waveform diagram, it can be seen that the magnitude of the shoot-through current is very small as compared with the case of the 4-bit counter shown in FIG.

The timing generator A shown in FIG. 1 produces a clamp pulse signal CP which is supplied to a clamp circuit (the principle of which is shown in FIG. 8) for clamping optical black in the CCD solid-state image pickup device. If you want to
As shown in, the timing pulse signal from the flip-flop circuit 2 is output based on the input of the reference signal Sr at the same time as the start of the horizontal blanking (HBLK) period in the horizontal synchronizing signal HD. Po may be used as the clamp pulse signal CP. In FIG. 9, Vout represents the output signal from the CCD solid-state image sensor, and particularly the period tb represents the period during which optical black is being output.

In this case, since the switching noise from the shift register 1 is very small, the clamped optical black does not change due to the switching noise, and the black shift on the screen can be prevented. ..

Further, since the suppression circuit for suppressing the switching noise can be made to have a minimum circuit configuration or can be eliminated, the design freedom with respect to the variation factors such as the board wiring capacitance, the decoupling capacitance, and the manufacturing variation of the LSI is provided. As a result, the image quality can be increased and stable image quality can be reproduced.

Next, using the timing generator A, a plurality of vertical transfer pulses V ₁ in the CCD solid-state image pickup device are obtained.
~ V ₄ about the second embodiment for creating V ₄
Will be described with reference to. The same reference numerals are given to those corresponding to FIG.

[0061] In this second embodiment, since a plurality of pulse signals is required (vertical transfer pulse) V ₁ ~V ₄ as its output, the number of which corresponds to the vertical transfer pulses V ₁ ~V ₄ required Flip-flop circuits 2A to 2D are provided,
It is connected to the shift register 11 as a timing generation circuit.

Here, an example in which vertical transfer of the CCD solid-state image pickup device is performed by four-phase driving will be described. As the vertical transfer pulse, as shown in FIG. pulse V ₁ ~V ₄ is required. Therefore, as described above, four flip-flop circuits 2 are also provided.

When the signal charges transferred from the respective light receiving portions of the CCD solid-state image pickup device to the corresponding vertical registers are transferred in the vertical direction, that is, to the horizontal register side, the vertical transfer pulses V _{1 to} V ₄ The output waveform is set as shown in FIG.

At this time, the output waveform from the flip-flop circuit 2 has a convex pulse waveform from low level to high level and from high level to low level, as shown in FIGS. 2 and 4. Therefore, in order to obtain the downwardly convex pulse waveforms V ₁ and V _2, as shown in FIG. 11, in particular, the first and second flip-flop circuits 2
Inversion circuits 12 and 13 are connected to the subsequent stages of A and 2B, respectively.

Then, the set side input terminals φS _{1 to} φS ₄ and the reset side of each flip-flop circuit 2A to 2D are set so that the output timing and the pulse width correspond to the output waveform of each vertical transfer pulse V _{1 to} V _4. Input terminal φR ₁ ~ φ
Output terminals Q _{A to} Q of the shift register 1 connected to R ₄
Choose two pairs of _K as appropriate.

The reset signal Sr in the second embodiment is used.
Is different from that of the first embodiment. That is, when the timing generator A shown in FIG. 1 is used for generating a clamp pulse, it is supplied to the timing generator of the second embodiment based on the output of the stop signal Ss of the shift register 1 constituting the timing generation circuit. Reset signal Srb is generated, and the reset signal Srb is supplied to the input terminal φB of the shift register 11.

Therefore, the reset signal Srb used in the second embodiment has a timing delayed by a certain time from the start of the horizontal blanking period. This is usually because each vertical transfer pulse V ₁ in the CCD solid-state image sensor is
This is because V ₄ is output after a fixed time has elapsed from the output of the clamp pulse signal CP.

The reset signal Srb can be generated by using the same circuit configuration as the reset signal generating circuit 5 shown in FIG. 5, and in the circuit of FIG.
Instead of D, the stop signal Ss from the shift register 1 may be used.

Then, the vertical transfer pulse V₁~ V_Fourof
A first flip-flop circuit corresponding to each output waveform
2A set side input terminal φS₁And reset side input terminal
φR ₁And the two output terminals Q of the shift register 11_COver
And Q_FTo each of the second flip-flop circuit 2B
Set side input terminal φS₂And reset side input terminal φR
₂And two output terminals Q_EAnd Q_HConnect each.

Further, the third flip-flop circuit 2C
Set side input terminal φS₃And reset side input terminal φR₃
And two output terminals Q_BAnd Q_GConnect each to the 4th
Set side input terminal φS of the flip-flop circuit 2D_FourOver
And reset side input terminal φR_FourAnd two output terminals Q_DOver
And Q_IConnect each. By connecting like this
Output terminals for the flip-flop circuits 2A to 2D
Child φ₁~ Φ_FourFrom the corresponding vertical transfer pulse output.
Timing pulse signal V according to force waveform₁~ V _FourIs output
Will be done.

According to the second embodiment, since the switching noise from the shift register 11 is very small, the switching noise is not superposed on the vertical transfer pulses V _{1 to} V ₄ and the CCD solid-state image pickup device. It is possible to favorably transfer the signal charge accumulated in the light receiving portion of the above in the vertical direction, that is, to the horizontal register side.

[0072]

According to the timing generator of the present invention, the timing switching noise can be reduced and the degree of freedom in designing with respect to the process variation factor can be increased. In this case, stable image quality reproduction can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a timing generator according to a first embodiment.

FIG. 2 is a timing chart showing the operation of the timing generator according to the first embodiment.

FIG. 3 is a circuit diagram showing a specific example of the timing generator according to the first embodiment.

FIG. 4 is a timing chart showing the operation of the specific example shown in FIG.

FIG. 5 is a circuit diagram showing an example of a reset signal generation circuit.

FIG. 6 is a timing chart showing the operation of the reset signal generation circuit shown in FIG.

FIG. 7 is a waveform diagram showing the magnitude of a through current in a 4-bit shift register.

FIG. 8 is a principle diagram showing a clamp circuit.

FIG. 9 is a timing chart showing the output timing of a clamp pulse signal.

FIG. 10 is a block diagram showing a timing generator according to a second embodiment.

FIG. 11 is a timing chart showing the output timing of a vertical transfer pulse.

FIG. 12 is a timing chart showing the operation of a hexadecimal counter used in the conventional timing generator.

FIG. 13 is a waveform diagram showing the magnitude of shoot-through current in a 4-bit counter.

[Explanation of symbols]

 A timing generator 1 shift register 2 flip-flop circuit

Claims (3)

[Claims] 1. An operation is started based on an input of a reference signal,
A timing generation circuit that sequentially outputs an output signal of a predetermined pulse width from a plurality of output terminals based on the input of a clock signal; and a timing generation circuit that outputs two sets of output terminals selected from the plurality of output terminals of the timing generation circuit. A timing generator comprising a flip-flop circuit to which output signals are respectively input as a set signal and a reset signal, and a timing pulse signal having a desired pulse width is output from an output terminal. 2. The reference signal is output at the start of horizontal blanking in a CCD solid-state imaging device, and the timing pulse signal is a clamp pulse signal for clamping optical black in a clamp circuit. The timing generator according to claim 1. 3. The reference signal is output after a lapse of a predetermined time from the start of horizontal blanking in a CCD solid-state image pickup device, wherein a plurality of the flip-flop circuits are arranged and a plurality of the timing generating circuits are provided. Corresponding output signals of two sets from the output terminals selected for each two sets of the output terminals are input to the plurality of flip-flop circuits as set signals and reset signals, respectively, and from the respective flip-flop circuits. The timing generator according to claim 1, wherein a vertical transfer pulse having a desired pulse width is output.