JP4367972B2 - Charge storage control correction circuit and linear sensor chip - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a charge accumulation control correction circuit suitable for application to charge accumulation control of a solid-state imaging device (CCD: Charge Coupled Device), for example.
[0002]
[Prior art]
Conventionally, there has been a timing generation circuit that generates a pulse signal necessary for driving charge accumulation or transfer in a CCD. This timing generation circuit is, for example, a circuit that generates various pulse signals of a read gate ROG pulse and a CCD analog shift register pulse (two-phase drive method) at a predetermined timing.
[0003]
FIG. 8 shows a timing chart of the signal reading operation from the CCD linear sensor in the conventional timing generation circuit. In FIG. 8, CK is a clock, INTG is a control signal for accumulation control, and ROG is a signal for reading from the CCD linear sensor, and is generated based on the clock CK and the control signal INTG.
[0004]
FIG. 8 shows a signal reading operation from the CCD linear sensor when the control signal INTG is at a high level for two clocks. The control signal INTG becomes low level after the high level input accumulation time 20 for two clocks. The read signal ROG is high level for two clocks together with the control signal INTG. When the control signal INTG is low level, the read signal ROG is low level for one clock and high level for one clock. The low level for one clock and the high level for one clock of the read signal ROG are the accumulation operation time 21 in the CCD, and the accumulation and reading are completed. Thereafter, the read signal ROG becomes low level for 8 clocks and then returns to high level.
[0005]
[Problems to be solved by the invention]
However, in the conventional timing generation circuit, when charge accumulation control is performed on a CCD or the like, if an accumulation command for less than a certain time is input to the CCD, the CCD may malfunction. That is, in order to perform a normal signal reading operation with a CCD or the like, a pulse having a time longer than twice the shortest clock cycle is required. In FIG. 8, when the input accumulation time 20 of the control signal INTG is at a high level for two clocks, the CCD normally performs the accumulation and reading operations like the accumulation operation time 21 in the CCD of the read signal ROG. When the input accumulation time 20 of the control signal INTG is 1 clock which is 2 clocks or less, the readout signal ROG cannot be normally generated, and there is a disadvantage that the signal charge is not correctly read out from the CCD. .
[0006]
When such a CCD is used, as a system, the accumulation time can be freely controlled by an accumulation command from an external microcontroller (hereinafter referred to as a microcomputer) according to the amount of light received by the light receiving portion of the CCD. When the amount of light is large, it is necessary to control the microcomputer so that an accumulation command with an input accumulation time 20 of the control signal INTG of 2 clocks or less is not input, There is an inconvenience that it is necessary to set an optical system provided in front of the light receiving unit of the CCD.
[0007]
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to provide a charge accumulation control correction circuit that supplies a control signal that allows a CCD to operate normally even when the amount of light is large, without requiring external settings. Is.
[0008]
In order to solve the above problems and achieve the object of the present invention, the electrical storage control correction circuit of the present invention is generated based on the control signal and the reference clock, and is stored and stored in the charge storage unit . A charge accumulation control correction circuit for supplying an output control signal for taking out a charge , wherein the control signal and the reference clock are input to generate an intermediate control signal; the control signal and the intermediate control signal are input; A logic operation circuit that outputs an output control signal having a predetermined clock width is provided. When the control signal is less than the time required for the charge accumulation and charge extraction operations in the charge accumulation unit, the charge accumulation unit normally performs the charge accumulation and charge extraction operations in the shortest time. is characterized in that outputs the output control signal extends the control signal.
The linear sensor chip of the present invention is a linear sensor chip in which at least a charge accumulation control correction circuit as described above is provided on the chip.
[0009]
Such a charge accumulation control correction circuit according to the present invention operates as follows.
The charge accumulation control correction circuit of the present invention, the control signal and the charge accumulation unit which operates by an output control signal generated with respect to the reference clock, the output for taking out the accumulated charge by accumulating the reference clock and the charge Operates to supply control signals. The latch receives the control signal and the reference clock, and receives the control signal and the reference clock to generate an intermediate control signal. The logic operation circuit receives the control signal and the intermediate control signal and outputs an output control signal of a predetermined clock .
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, a drive circuit system of a CCD linear sensor to which the charge accumulation control correction circuit of this embodiment is applied will be described with reference to FIG. In FIG. 7, the drive circuit system of the CCD linear sensor is for the drive circuit 12 for generating a control signal necessary for driving charge accumulation or transfer to the CCD, and for the control signal to perform charge accumulation and charge extraction operations in the CCD. Charge storage control correction circuit 13 that corrects the control signal in the shortest time for the CCD to normally perform charge storage and charge extraction operations when the time is less than the time required for the charge, and charge storage by the corrected output control signal And a CCD linear sensor 14 for performing charge extraction operation.
[0011]
The drive circuit 12 is a circuit that generates various pulse signals at predetermined timing, such as vertical 4-phase clock pulses, horizontal 2-phase clock pulses, and field drive field shift pulses. The charge accumulation control correction circuit 13 corrects various timing pulse signals supplied from the drive circuit 12, but in the present embodiment, the control signal is representative of these various timing pulse signals for charge accumulation and charge extraction in the CCD. An example will be shown in which the control signal is corrected to the shortest time for the CCD to normally perform charge accumulation and charge extraction when the time is less than the time required for operation. The CCD linear sensor 14 receives light, accumulates charges, and converts it into an electrical signal with linear characteristics. The CCD linear sensor 14 requires output control signals for two clocks or four clocks depending on its structure and driving method in order to perform charge accumulation and charge extraction operations. For example, the CCD linear sensor 14 includes a CCD analog shift register operated by two-phase clock pulses φ1 / φ2, a ROG gate operated by a read signal ROG pulse, a linearly arranged sensor array, and a CCD analog shift register. Has a buffer to store the output. Then, the control signal INTG starts the accumulation operation in two clock (or 4 clocks) from the rise, also read signal ROG (output to end the accumulation operation after fall of the control signal INTG in two clock (or 4 clocks) A control signal INTG ′) is supplied.
[0012]
The charge accumulation control correction circuit of this embodiment applied to such a CCD linear sensor drive circuit system will be described in detail below.
First, FIG. 1 describes a charge accumulation control correction circuit that outputs a control signal for two clocks in order to perform charge accumulation and charge extraction operations.
In FIG. 1, the charge accumulation control correction circuit of this embodiment holds a control signal INTG by a control signal input terminal 1 to which a control signal INTG is supplied, a clock terminal 2 to which a clock CK1 is supplied, and a clock CK1. The latch 3 that outputs the output signal Q1 from the output terminal Q, the latch 4 that holds the output signal Q1 by the clock CK1 and outputs the inverted output signal XQ2 from the output terminal XQ, and the output signal Q1 and the inverted output signal XQ2 An AND gate 5 that outputs a logical sum and outputs an AND output A1, an OR gate 6 that outputs a logical product of the control signal INTG and the AND output A1 and outputs an OR output O1, and the OR output O1 is held by the clock CK1. And a latch 8 for outputting an output control signal INTG ′ from the output terminal Q.
[0013]
Next, the connection relationship of the charge accumulation control correction circuit of this embodiment will be described. The control signal input terminal 1 is connected to the input terminal D of the latch 3, and the clock terminal 2 is connected to the clock terminal CK of the latch 3. The output terminal Q of the latch 3 is connected to the input terminal D of the latch 4, and the clock terminal 2 is connected to the clock terminal CK of the latch 4. The inversion output terminal XQ of the latch 4 is connected to one input terminal of the AND gate 5, and the output terminal Q of the latch 3 is connected to the other input terminal of the AND gate 5. The output terminal of the AND gate 5 is connected to one input terminal of the OR gate 6, and the control signal input terminal 1 is connected to the other input terminal of the OR gate 6. The output terminal of the OR gate 6 is connected to the input terminal D of the latch 7, and the clock terminal 2 is connected to the clock terminal CK of the latch 7. The output terminal Q of the latch 7 is connected to the control signal output terminal 8.
[0014]
The operation of the charge accumulation control correction circuit of this embodiment configured as described above will be described with reference to the timing charts of FIGS.
First, FIG. 2 shows a timing chart when 2 clocks are output by the control signal of 1 clock according to this embodiment. In FIG. 2, a clock CK 1 obtained by inverting the clock CK is supplied to the clock terminal 2. Then, the control signal INTG that becomes high level by one clock from the falling edge of the clock CK 1 is supplied to the control signal input terminal 1. The latch 3 latches the high level of the control signal INTG when the clock CK1 is at the high level to the low level corresponding to one clock of the clock CK1, and outputs the output signal Q1.
[0015]
The output signal Q1 is supplied to the input terminal D of the latch 4. The latch 4 latches the high level of the output signal Q1 when the clock CK1 is high level to the low level corresponding to one clock of the clock CK1, and outputs the inverted output signal XQ2.
[0016]
The inverted output signal XQ2 is supplied to one input terminal of the AND gate 5, and the output signal Q1 is supplied to the other input terminal of the AND gate 5. The AND gate 5 gates when the output signal Q1 and the inverted output signal XQ2 are both at the high level, and outputs an AND output A1.
[0017]
The AND output A1 is supplied to one input terminal of the OR gate 6, and the control signal INTG is supplied to the other input terminal of the OR gate 6. The OR gate 6 gates when the control signal INTG or the AND output A1 is at a high level and outputs an OR output O1.
[0018]
The OR output O1 is supplied to the input terminal D of the latch 7. The latch 7 latches the high level of the OR output O1 when the clock CK1 is high to the low level corresponding to two clocks of the clock CK1, and outputs the output control signal INTG ′ for two clocks. Thus, even when a control signal for one clock is input, an output control signal for two clocks with the shortest accumulation time can be obtained.
[0019]
Next, FIG. 3 shows a timing chart when 2 clocks are output by the 2-clock control signal of this embodiment. In FIG. 3, a clock CK <b> 1 obtained by inverting the clock CK is supplied to the clock terminal 2. Then, the control signal INTG that becomes high level for two clocks from the fall of the clock CK1 is supplied to the control signal input terminal 1. The latch 3 latches the high level of the control signal INTG when the clock CK1 is at the high level to the low level for two clocks of the clock CK1, and outputs the output signal Q1.
[0020]
The output signal Q1 is supplied to the input terminal D of the latch 4. The latch 4 latches the high level of the output signal Q1 when the clock CK1 is high level to a low level corresponding to two clocks of the clock CK1, and outputs the inverted output signal XQ2.
[0021]
The inverted output signal XQ2 is supplied to one input terminal of the AND gate 5, and the output signal Q1 is supplied to the other input terminal of the AND gate 5. The AND gate 5 gates when the output signal Q1 and the inverted output signal XQ2 are both at the high level, and outputs an AND output A1.
[0022]
The AND output A1 is supplied to one input terminal of the OR gate 6, and the control signal INTG is supplied to the other input terminal of the OR gate 6. The OR gate 6 gates when the control signal INTG or the AND output A1 is at a high level and outputs an OR output O1.
[0023]
The OR output O1 is supplied to the input terminal D of the latch 7. The latch 7 latches the high level of the OR output O1 when the clock CK1 is high to the low level corresponding to two clocks of the clock CK1, and outputs the output control signal INTG ′ for two clocks. As a result, when a control signal for two clocks is input, an output control signal for two clocks with the shortest accumulation time can be obtained.
By doing so, the read operation can be made normal even if it is attempted to reduce the charge accumulation to 2 clocks or less when the amount of light is large on a system equipped with a CCD. In this case, the output signal is large because the amount of light is large.
[0024]
Next, FIG. 4 illustrates another charge accumulation control correction circuit of this embodiment that outputs a control signal for four clocks in order to perform charge accumulation and charge extraction operations. Here, components corresponding to those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.
In FIG. 4, another charge accumulation control correction circuit of this embodiment includes a control signal input terminal 1 to which a control signal INTG is supplied, a clock terminal 2 to which a clock CK1 is supplied, and a control signal INTG by the clock CK1. The latch 3 that holds and outputs the output signal Q1 from the output terminal Q, the latch 4 that holds the output signal Q1 by the clock CK1 and outputs the inverted output signal XQ2 from the output terminal XQ, and the output signal Q1 and the inverted output signal XQ2 AND gate 5 that outputs AND output A1 and latch 9 that holds AND output A1 by clock CK1 and outputs output signal Q3 from output terminal Q, and holds output signal Q3 by clock CK1 The latch 10 that outputs the output signal Q4 from the output terminal Q, and the logic of the AND output A1, the output signal Q3, and the output signal Q4 An OR gate 11 that takes the product and outputs an OR output O2, an OR gate 6 that outputs a logical product of the control signal INTG and the OR output O2, and outputs an OR output O1, and an output terminal that holds the OR output O1 by the clock CK1 And a latch 8 for outputting an output control signal INTG ′ from Q.
[0025]
Next, the connection relationship of the charge accumulation control correction circuit of this embodiment will be described. The control signal input terminal 1 is connected to the input terminal D of the latch 3, and the clock terminal 2 is connected to the clock terminal CK of the latch 3. The output terminal Q of the latch 3 is connected to the input terminal D of the latch 4, and the clock terminal 2 is connected to the clock terminal CK of the latch 4. The inversion output terminal XQ of the latch 4 is connected to one input terminal of the AND gate 5, and the output terminal Q of the latch 3 is connected to the other input terminal of the AND gate 5. The output terminal of the AND gate 5 is connected to the input terminal D of the latch 9, and the clock terminal 2 is connected to the clock terminal CK of the latch 9. The output terminal Q of the latch 9 is connected to the input terminal D of the latch 10, and the clock terminal 2 is connected to the clock terminal CK of the latch 10. The output terminal of the AND gate 5 is connected to the first input terminal of the OR gate 11, the output terminal Q of the latch 9 is connected to the second input terminal of the OR gate 11, and the output terminal Q of the latch 10 is the third input terminal of the OR gate 11. Connected to the input terminal. The output terminal of the OR gate 11 is connected to one input terminal of the OR gate 6, and the control signal input terminal 1 is connected to the other input terminal of the OR gate 6. The output terminal of the OR gate 6 is connected to the input terminal D of the latch 7, and the clock terminal 2 is connected to the clock terminal CK of the latch 7. The output terminal Q of the latch 7 is connected to the control signal output terminal 8.
[0026]
The operation of another charge accumulation control correction circuit of this embodiment configured as described above will be described with reference to the timing charts of FIGS.
First, FIG. 5 shows a timing chart when 4 clocks are output by the control signal of 1 clock according to this embodiment. In FIG. 5, a clock CK 1 obtained by inverting the clock CK is supplied to the clock terminal 2. Then, the control signal INTG that becomes high level by one clock from the falling edge of the clock CK 1 is supplied to the control signal input terminal 1. The latch 3 latches the high level of the control signal INTG when the clock CK1 is at the high level to the low level corresponding to one clock of the clock CK1, and outputs the output signal Q1.
[0027]
The output signal Q1 is supplied to the input terminal D of the latch 4. The latch 4 latches the high level of the output signal Q1 when the clock CK1 is high level to the low level corresponding to one clock of the clock CK1, and outputs the inverted output signal XQ2.
[0028]
The inverted output signal XQ2 is supplied to one input terminal of the AND gate 5, and the output signal Q1 is supplied to the other input terminal of the AND gate 5. The AND gate 5 gates when the output signal Q1 and the inverted output signal XQ2 are both at the high level, and outputs an AND output A1.
[0029]
The AND output A1 is supplied to the input terminal D of the latch 9. The latch 9 latches the high level of the control signal INTG when the clock CK1 is at the high level to the low level corresponding to one clock of the clock CK1, and outputs the output signal Q3. The output signal Q3 is supplied to the input terminal D of the latch 10. The latch 10 latches the high level of the control signal INTG when the clock CK1 is at the high level to the low level for one clock of the clock CK1, and outputs the output signal Q4.
[0030]
The AND output A1, the output signal Q3, and the output signal Q4 are supplied to the first input terminal, the second input terminal, and the third input terminal of the OR gate 11, respectively. The OR gate 11 gates when the AND output A1, the output signal Q3, and the output signal Q4 are at a high level, and outputs an OR output O2. The OR output O2 is supplied to one input terminal of the OR gate 6, and the control signal INTG is supplied to the other input terminal of the OR gate 6. The OR gate 6 gates when the control signal INTG or the OR output O2 is at a high level and outputs an OR output O1.
[0031]
The OR output O1 is supplied to the input terminal D of the latch 4. The latch 7 latches the high level of the OR output O1 when the clock CK1 is high to the low level corresponding to four clocks of the clock CK1, and outputs the output control signal INTG ′ for four clocks. Thus, even when a control signal for one clock is input, an output control signal for four clocks with the shortest accumulation time can be obtained.
[0032]
Next, FIG. 6 shows a timing chart when 4 clocks are output by the 4-clock control signal of this embodiment. In FIG. 6, a clock CK <b> 1 obtained by inverting the clock CK is supplied to the clock terminal 2. Then, a control signal INTG that becomes a high level for 4 clocks from the fall of the clock CK1 is supplied to the control signal input terminal 1. The latch 3 latches the high level of the control signal INTG when the clock CK1 is at the high level to the low level for four clocks of the clock CK1, and outputs the output signal Q1.
[0033]
The output signal Q1 is supplied to the input terminal D of the latch 4. The latch 4 latches the high level of the output signal Q1 when the clock CK1 is high level to the low level corresponding to four clocks of the clock CK1, and outputs the inverted output signal XQ2.
[0034]
The inverted output signal XQ2 is supplied to one input terminal of the AND gate 5, and the output signal Q1 is supplied to the other input terminal of the AND gate 5. The AND gate 5 gates when the output signal Q1 and the inverted output signal XQ2 are both at the high level, and outputs an AND output A1.
[0035]
The AND output A1 is supplied to the input terminal D of the latch 9. The latch 9 latches the high level of the control signal INTG when the clock CK1 is at the high level to the low level corresponding to one clock of the clock CK1, and outputs the output signal Q3. The output signal Q3 is supplied to the input terminal D of the latch 10. The latch 10 latches the high level of the control signal INTG when the clock CK1 is at the high level to the low level for one clock of the clock CK1, and outputs the output signal Q4.
[0036]
The AND output A1, the output signal Q3, and the output signal Q4 are supplied to the first input terminal, the second input terminal, and the third input terminal of the OR gate 11, respectively. The OR gate 11 gates when the AND output A1, the output signal Q3, and the output signal Q4 are at a high level, and outputs an OR output O2. The OR output O2 is supplied to one input terminal of the OR gate 6, and the control signal INTG is supplied to the other input terminal of the OR gate 6. The OR gate 6 gates when the control signal INTG or the OR output O2 is at a high level and outputs an OR output O1.
[0037]
The OR output O1 is supplied to the input terminal D of the latch 4. The latch 7 latches the high level of the OR output O1 when the clock CK1 is high to the low level corresponding to four clocks of the clock CK1, and outputs the output control signal INTG ′ for four clocks. As a result, when a control signal for 4 clocks is input, an output control signal for 4 clocks with the shortest accumulation time can be obtained.
[0038]
As described above, according to the above-described embodiment, it is not necessary to control the shortest accumulation time from the outside, and the system can be designed.
[0039]
Further, the structure is not limited to the control signal for 2 clocks or 4 clocks shown in the charge storage control correction circuit of the present embodiment described above, and the structure of the CCD linear sensor 14 for performing charge storage and charge extraction operations. Any output control signal corresponding to the clock having the shortest accumulation time depending on the driving method may be used.
[0040]
【The invention's effect】
The charge accumulation control correction circuit according to the present invention supplies the reference clock and a control signal for accumulating the charge and taking out the accumulated charge to the charge accumulating unit that operates according to the control signal generated with respect to the reference clock. A charge storage unit that normally performs charge storage and charge extraction operations when the control signal is less than the time required for charge storage and charge extraction operations in the charge storage unit; The above control signal is corrected in the shortest possible time, so even if the control signal is less than the time required for charge accumulation and charge extraction operations, no external setting is required, Even if the signal is large, it is possible to supply a control signal that allows the CCD to operate normally, and to make the charge reading operation from the charge storage unit normal. There is an effect that.
[0041]
In the charge accumulation control correction circuit according to the present invention, since the charge accumulation unit is a solid-state imaging device that receives light, accumulates the charge, and converts it into an electric signal, the structure and driving of the solid-state imaging device are described above. By the method, even when the control signal is less than the time required for the charge accumulation and charge extraction operations in the charge accumulation unit, the charge reading operation from the charge accumulation unit can be performed normally. Play.
[0042]
In the charge accumulation control correction circuit according to the present invention, the time required for the charge accumulation and charge extraction operations in the charge accumulation unit is twice as long as the reference clock. The output control signal for two clocks of the shortest accumulation time in the unit can be obtained.
[0043]
In the charge accumulation control correction circuit according to the present invention, since the time required for the charge accumulation and charge extraction operations in the charge accumulation section is four times the reference clock, The output control signal for 4 clocks of the shortest accumulation time in the unit can be obtained.
[0044]
In addition, since the charge accumulation control correction circuit according to the present invention can be on-chip on the linear sensor chip in the above description, there is no need for an external IC, and the cost merit can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a charge accumulation control correction circuit (2-clock output) according to an embodiment of the present invention.
FIG. 2 is a timing chart showing an operation when two clocks are output by a control signal of one clock according to one embodiment of the present invention.
FIG. 3 is a timing chart showing an operation when 2 clocks are output by a 2-clock control signal according to one embodiment of the present invention;
FIG. 4 is a block diagram showing a configuration of another charge accumulation control correction circuit (4-clock output) according to an embodiment of the present invention;
FIG. 5 is a timing chart showing an operation when 4 clocks are output by a control signal of 1 clock according to one embodiment of the present invention;
FIG. 6 is a timing chart showing an operation when 4 clocks are output by a 4-clock control signal according to one embodiment of the present invention;
FIG. 7 is a diagram showing a drive circuit system for a CCD linear sensor applied to an embodiment of the present invention.
FIG. 8 is a timing chart of a signal reading operation from a conventional CCD linear sensor (in the case of accumulation control input for 2 clocks).
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Control signal input terminal, 2 ... Clock terminal, 3 ... Latch, 4 ... Latch, 5 ... AND gate, 6 ... OR gate, 7 ... Latch, 8 ... Control signal output terminal, 9 ... Latch, 10 ... Latch, 11 ... OR gate, 12 ... drive circuit, 13 ... charge accumulation control correction circuit, 14 ... CCD linear sensor, INTG ... control signal, CK1 ... clock, INTG '... output control signal

Claims (4)

A charge accumulation control correction circuit that is generated based on a control signal and a reference clock and supplies an output control signal for accumulating charges and extracting the accumulated charges to a charge accumulating unit;
The control signal and the reference clock are input,
A latch for receiving the control signal and the reference clock and generating an intermediate control signal;
Wherein said control signal intermediate control signal is input, a logical operation circuit for outputting an output control signal having a predetermined clock width, comprising,
When the control signal is less than the time required for the charge accumulation and charge extraction operations in the charge accumulation unit, the shortest time for the charge accumulation unit to normally perform the charge accumulation and charge extraction operations A charge accumulation control correction circuit which outputs the output control signal obtained by expanding the control signal . The latch is
A first latch that receives the control signal and the reference clock and outputs a first intermediate control signal delayed by a half clock from the control signal;
A second latch that receives the first intermediate control signal and the reference clock, and outputs a second intermediate control signal that is delayed by one clock from the first intermediate control signal and inverted;
The logical operation circuit is:
A first arithmetic unit that takes a logical product of the first intermediate control signal and the second intermediate control signal;
A second arithmetic unit that outputs a logical sum of the control signal and the logical product;
The charge accumulation control correction circuit according to claim 1, wherein the charge accumulation control correction circuit is provided. A linear sensor chip having at least a charge accumulation control correction circuit on the chip,
The charge accumulation control correction circuit includes:
A latch that receives the control signal and the reference clock and generates an intermediate control signal;
Wherein said control signal intermediate control signal is input, and a logic operation circuit for outputting the output control signal of the predetermined clock,
When the control signal is less than the time required for the charge accumulation and charge extraction operations in the charge accumulation unit, the shortest time for the charge accumulation unit to normally perform the charge accumulation and charge extraction operations A linear sensor chip that outputs the output control signal obtained by extending the control signal . The latch is
A first latch that receives the control signal and the reference clock and outputs a first intermediate control signal delayed by a half clock from the control signal;
A second latch that receives the first intermediate control signal and the reference clock and outputs a second intermediate control signal that is delayed by one clock and inverted from the first intermediate control signal;
The logical operation circuit is:
A first arithmetic unit that takes a logical product of the first intermediate control signal and the second intermediate control signal;
The linear sensor chip according to claim 3, further comprising a second arithmetic unit that outputs a logical sum of the control signal and the logical product.

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