JP2003092709A - Method for driving solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption and enhanced S/N of a solid-state imaging device. SOLUTION: A vertical electric charge transfer register transfers signal electric charges converted from light by optical sensors receiving the light and laid out on a semiconductor substrate in a matrix shape to a vertical electric charge transfer register by each column of the optical sensors and to a horizontal electric charge transfer register by each row of the optical sensors. A floating diffusion section converts the transferred signal electric charges into a voltage and an output circuit outputs it at a low impedance as a video signal. When the output of the video signal is intermittent like a long time exposure mode, each transfer register is stopped for periods when no video signal is outputted, resetting of the floating diffusion section is stopped and the operation of the output circuit is also stopped. Thus, the power consumption can be reduced and suppression of generated heat results in suppressing noise.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a solid-state image pickup device.

[0002]

2. Description of the Related Art FIG. 7 is a schematic plan view of an essential part showing an example of a conventional general solid-state image pickup device. As shown in FIG.
The conventional solid-state imaging device 102 includes a large number of optical sensors 106 and a vertical charge transfer register 10 on a semiconductor substrate 104.
8. The horizontal charge transfer register 110 and the like are provided. The optical sensors 106 are arranged in a matrix, and the vertical charge transfer registers 108 are the optical sensors 10.
Each of the six columns extends along the column of the optical sensor 106. The horizontal charge transfer register 110 extends on one end side of the vertical charge transfer register 108 orthogonal to the vertical charge transfer register 108, that is, in the row direction of the photosensor 106, and performs charge-voltage conversion at its output end. Floating diffusion unit 112 (FD unit 11
2) is provided. The video signal generated by the FD unit 112 is output to the outside of the solid-state imaging device 102 through the output circuit 113 with low impedance. In addition, the FD unit 112
A reset gate 114 is provided close to
Unnecessary charges accumulated in the D section 112 are reset gate 11
4 to the reset drain (not shown). A vertical transfer clock 116 is supplied to the vertical charge transfer register 108, a horizontal transfer clock 118 is supplied to the horizontal charge transfer register 110, and a reset gate 11 is supplied.
4 are supplied with reset clocks 120, respectively.

Next, a method of driving the solid-state image pickup device 102 having the above structure will be described. FIG. 8 is a timing chart showing a driving method of the solid-state imaging device 102 of FIG. First, the signal charges received by the photosensors 106 are generated by applying a vertical transfer clock having a voltage (HH) higher than that at the time of transfer to the vertical charge transfer registers 108 at the same time by applying the vertical transfer clocks to the vertical charge transfer registers 108. It is read to the charge transfer register 108. In FIG. 7, the signal charge of each photosensor 106 is read to the vertical charge transfer register 108 adjacent to the left side of each photosensor 106.

After that, a vertical transfer clock 116 whose voltage level is switched between an original high level (H) and a low level (L) is supplied to the vertical charge transfer register 108, which drives the vertical charge transfer register 108. Then, as described above, the signal charges read from the optical sensor 106 are sequentially transferred to the horizontal charge transfer register 110. Then, the horizontal charge transfer register 110
Is driven by the horizontal transfer clock 118, and every time the signal charge for one row of the photosensor is supplied from the vertical charge transfer register 108, the signal charge for one row of the photosensor is sequentially transferred to the FD section 112. .

As a result, the horizontal charge transfer register 110
The signal charges supplied to the FD section 112 from the FD section 112 are
Is sequentially converted into a voltage by the output circuit 1 as a video signal.
13 and the output circuit 113 outputs this to the outside with low impedance. Further, the reset clock 120 is supplied to the reset gate 114 at the same cycle as the horizontal transfer clock 118, and the horizontal charge transfer register 1
Every time the FD unit 112 converts the signal charge supplied from 10 into a voltage and outputs the voltage, the unnecessary signal charge of the FD unit 112 is discarded to the reset drain.

This operation is performed by the read pulse 122.
To the vertical charge transfer register 108 and the signal charges read out to the vertical charge transfer register 108 are repeated until they are all transferred by the vertical charge transfer register 108 and the horizontal charge transfer register 110. Then, the video signal 126 is output from the output circuit 113 while the read signal charges are being transferred to the vertical charge transfer register 108, that is, in the image output period 124 shown in FIG. When the image output period 124 ends, the video signal is no longer output from the output circuit 113 because the transfer of the signal charge read to the vertical charge transfer register 108 is completed.

When a moving image is photographed by the solid-state image pickup device 102, the next read pulse is supplied to the vertical charge transfer register 108 immediately after the image output period is completed, and the signal charge is read out from the photosensor 106, so that The operation like is repeated again. On the other hand, when a moving image is captured in the long-time exposure mode, the read pulse 122
122 for supplying the charge to the vertical charge transfer register 108
A has a length corresponding to a plurality of frames, and the video signal of one frame is not output in each original period of one frame, but is output in each period of a plurality of frames. Therefore, as shown in FIG. 8, the image output period 124 is intermittent, and after the image output period 124 ends, no video signal is output for a while. Further, in the still image shooting mode, when shooting is performed once and the image output period 124 ends, thereafter, no video signal is output until the next shooting is performed.

However, even in the long-time exposure mode or the still image shooting mode, the vertical charge transfer register 108 and the horizontal charge transfer register 11 are set after the image output period 124 ends.
0 and the reset gate 114 are continuously supplied with the vertical transfer clock 116, the horizontal transfer clock 118, and the reset clock 120 as shown in FIG. 8, and the vertical charge transfer register 108, the horizontal charge transfer register 110, In addition, the reset gate 114 is in operation. Further, the output circuit 113 is also constantly operating, and therefore, the constant power supply current Id is constant in the output circuit 1.
It flows through 13. The horizontal transfer clock 11
8 is temporarily stopped during the blanking period at the timing of the end of the image output period 124, but this blanking period is short, and the horizontal transfer clock 11 as a whole.
8 is always supplied to the horizontal charge transfer register 110.

[0009]

By the way, especially in a semiconductor device incorporated in an electronic device using a battery as a power source, the reduction of power consumption is always an important issue, and a solid state incorporated in a battery-operated video camera or the like. There is also a strong demand for low power consumption of image pickup devices. However, as described above, in the case of the long-time exposure mode or the still image shooting mode, the conventional solid-state image sensor 102 has the vertical charge transfer register 108 even after the image output period 124 ends and even when the video signal is not output. , Horizontal charge transfer register 11
0, the reset gate 114, and the output circuit 113 are in the operating state, and power is wasted. Therefore, there is room for improvement in this respect. Further, when power is consumed, the temperature of the solid-state image sensor 102 inevitably rises, but when the temperature of the solid-state image sensor 102 rises, noise components such as dark current noise mixed in the video signal increase, and the image quality deteriorates. Invite.

The present invention has been made to solve such a problem, and an object thereof is to provide a method for driving a solid-state image sensor, which achieves low power consumption of the solid-state image sensor and improvement of the SN ratio. To do.

[0011]

In order to achieve the above object, the present invention provides a plurality of optical sensors that receive light and generate signal charges, and the signal charges generated by the optical sensors when driven by a transfer clock. A method for driving a solid-state imaging device, which is configured by forming a charge transfer register for transfer on a semiconductor substrate, and generates and outputs a video signal based on the signal charge transferred by the charge transfer register. The supply of the transfer clock to the charge transfer register is stopped during a period in which the solid-state imaging device does not output the video signal.

That is, in the solid-state image pickup device driving method of the present invention, the supply of the transfer clock to the charge transfer register is stopped during the period other than the image output period during which the video signal is output. Does not work,
Therefore, the power consumption of the solid-state imaging device can be reduced as a whole. Further, as a result, the temperature rise of the solid-state image sensor is suppressed, so that noise components such as dark current noise mixed in the video signal can be reduced, the SN ratio is improved, and good image quality can be obtained.

Further, according to the present invention, a plurality of photosensors that receive light to generate signal charges, a charge transfer register that transfers the signal charges generated by the photosensors, and the signal charges transferred by the charge transfer register. And a method for driving a solid-state imaging device configured by forming an output circuit for outputting a video signal generated on the basis of low impedance on a semiconductor substrate, wherein the solid-state imaging device does not output the video signal. In, the power supply to the output circuit is stopped. That is, in the method for driving a solid-state image sensor according to the present invention, the power supply to the output circuit is stopped during the period when the video signal is not output. The power consumption of the device can be reduced as a whole. Further, as a result, the temperature rise of the solid-state image sensor is suppressed, so that noise components such as dark current noise mixed in the video signal can be reduced, the SN ratio is improved, and good image quality can be obtained.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a timing chart showing an example of a method for driving a solid-state image sensor according to the present invention, FIG. 2 is a schematic plan view of essential parts showing a solid-state image sensor driven by the method for driving a solid-state image sensor according to an embodiment, and FIG. It is a circuit diagram which shows in detail the output circuit which comprises the solid-state image sensor of FIG. 2 and 3, the same elements as those in FIG. 7 are designated by the same reference numerals, and the description thereof will be omitted here.

It is assumed that the solid-state image pickup device 2 shown in FIG. 2 is incorporated in a video camera as an example. The difference from the solid-state image pickup device shown in FIG. 7 is that the output circuit is replaced and a vertical transfer clock and a horizontal transfer clock are used. , And that the reset clock is changed.

First, the output circuit 4 will be described in detail with reference to FIG. The output circuit 4 comprises a three-stage source follower circuit 6, and each source follower circuit 6 includes a transistor 6A and a constant current circuit 8 including a transistor 6B.
It is composed of and. The drains of the transistors 6A of the source follower circuits 6 are commonly connected, and are connected to the power supply Vdd via the switching element 10 that can be turned on / off by a control signal. The gate of the transistor 6A of the source follower circuit 6 in the first stage is the FD section 11
2, the gates of the source follower circuits 6 in the second and final stages are connected to the sources of the transistors 6A in the previous stage.

The drain of the transistor 6B constituting the constant current circuit 8 of each stage is the transistor 6 of each stage.
It is connected to the source of A, the sources are commonly connected, and are connected to the ground via the resistor 12. The gates of the transistors 6B are all connected to the voltage source 14.

The video signal generated in the FD section 112 is output from the source of the final stage transistor 6A through the output circuit 4 as described above with a resistance impedance.
As shown in FIG. 3, the reset gate 114 is composed of the transistor 16, the source of which is connected to the FD section 112 and the drain of which is connected to the reset drain, that is, the power supply 18. The reset clock 20 is supplied to the gate of the transistor 16.

Next, the operation of the solid-state image pickup device 2 driven based on the driving method of the present invention will be described. First,
The signal charge received by each photosensor 106 is dealt with by applying the vertical transfer clock 22 having a voltage (HH) higher than that at the time of transfer to each vertical charge transfer register 108 as a read pulse 24 at the timing T1. Read out to the vertical charge transfer register 108.
After that, the vertical transfer clock 22 whose voltage level is switched between the original high level (H) and the low level (L) is supplied to the vertical charge transfer register 108, whereby the vertical charge transfer register 108 is driven and the above-described vertical charge transfer register 108 is driven. As described above, the signal charges read from the optical sensor 106 are sequentially transferred to the horizontal charge transfer register 110. Then, the horizontal charge transfer register 110 is driven by the horizontal transfer clock 26, and every time the signal charge for one row of the photosensor is supplied from the vertical charge transfer register 108, the signal charge for one row of the photosensor is sequentially fed. Part 1
Transfer to 12.

As a result, the horizontal charge transfer register 110
The signal charges supplied to the FD section 112 from the FD section 112 are
Is sequentially converted into a voltage by the output circuit 4 as a video signal.
Is output to the outside with low impedance. Further, the reset clock 20 is supplied to the reset gate 114 at the same cycle as the horizontal transfer clock 26, and every time the FD unit 112 converts the signal charge supplied from the horizontal charge transfer register 110 into a voltage and outputs the voltage, The signal charge of the FD section 112 that is no longer needed is discarded to the reset drain.

In such an operation, the read pulse 24 is supplied to the vertical charge transfer register 108 and the signal charges read out to the vertical charge transfer register 108 are supplied to the vertical charge transfer register 108 and the horizontal charge transfer register 1.
Repeated until all are transferred by 10. The video signal 126 is output from the output circuit 4 while the read signal charges are being transferred to the vertical charge transfer register 108, that is, in the image output period 124 shown in FIG.

When the image output period 124 ends at the timing T2, the video signal 126 is no longer output from the output circuit 4 because the transfer of the signal charges read to the vertical charge transfer register 108 is completed. When a moving image is captured by the solid-state image sensor 2, the next read pulse 24 is supplied to the vertical charge transfer register 108 immediately after the image output period is completed, and the signal charge is read from the optical sensor 106, as described above. Although such an operation is repeated again, here, it is assumed that moving image shooting or still image shooting in the long-time exposure mode is performed.

In this embodiment, the image output period 1
After the end of 24, the vertical charge transfer register 108, the horizontal charge transfer register 110, and the reset gate 114 are supplied until the next read pulse 24 is supplied to the vertical charge transfer register 108 at timing T3.
As shown in FIG. 1, the vertical transfer clock 116,
Horizontal transfer clock 26 and reset clock 20
Do not supply. Therefore, during the period from timing T2 to T3, the vertical charge transfer register 108, the horizontal charge transfer register 110, and the reset gate 114 stop their operations except for the sweep-out transfer period 28 described later. Further, during this period, the switching element 10 (FIG. 3) is turned off under the control of the control signal 30, the power supply to the output circuit 4 is stopped, and the operation of the output circuit 4 is stopped. Therefore, during this period, the power supply current Id becomes zero.

Thereafter, in the present embodiment, the next signal charge is read at the timing T3, but when the period in which the video signal is not output ends, the sweep transfer period 28 prior to the signal charge read is completed. 1, the vertical charge transfer register 108, the horizontal charge transfer register 110, and the reset gate 11 as shown in FIG.
4 to the vertical transfer clock 116, the horizontal transfer clock 26, and the reset clock 20, respectively.
As a result, after timing T2, unnecessary charges that have accumulated in the vertical charge transfer register 108 and the horizontal charge transfer register 110 and cause dark signals, smears, and the like are swept out from the vertical charge transfer register 108 and the next signal charge It can be prepared for reading. Since the transfer in the sweep-out transfer period 28 is intended to sweep out unnecessary charges as described above, each clock, particularly the vertical transfer clock 22, is set to have a shorter cycle than usual and is transferred to the vertical charge transfer register 108 at high speed. , Sweep-out transfer period 2
8 can be shortened.

As described above, in this embodiment, the vertical transfer clock 116 and the horizontal transfer clock 2 are excluded in the periods other than the image output period 124 except for the sweep-out transfer period 28.
6 and the supply of the reset clock transfer clock are stopped, the vertical charge transfer register 108,
Horizontal charge transfer register 110, reset gate 114
Does not operate, and therefore the power consumption of the solid-state imaging device 2 can be reduced as a whole. Further, as a result, the temperature rise of the solid-state imaging device 2 is suppressed, so that noise components such as dark current noise mixed in the video signal can be reduced, and the SN ratio is improved to obtain good image quality.

Further, in this embodiment, the image output period 1
Since the power supply to the output circuit 4 is stopped in a period other than 24, the output circuit 4 does not operate during this period, so that the power consumption of the solid-state imaging device 2 can be reduced as a whole. Further, as a result, the temperature rise of the solid-state imaging device 2 is suppressed, so that noise components such as dark current noise mixed in the video signal can be reduced, and the SN ratio is improved to obtain good image quality.

In this case, all the operations of the vertical charge transfer register 108, the horizontal charge transfer register 110, and the output circuit 4 are stopped in the periods other than the image output period 124. It is also effective to stop only one or two operations to reduce power consumption and improve the SN ratio. Further, when the operation of the vertical charge transfer register 108 is stopped, the vertical transfer clock 116 may be fixed to either high level or low level, but it may be set to low level (L) from the viewpoint of suppressing dark signals. preferable.
When stopping the operation of the horizontal charge transfer register 110,
The horizontal transfer clock 26 may be fixed at either a high level or a low level, but from the viewpoint of discharging charges, it is preferably set to the same level as the level immediately before receiving the signal charges from the vertical charge transfer register 108. When the operation of the reset gate 114 is stopped, the reset clock 20 may be fixed to either a high level or a low level, but it is preferably set to the high level from the viewpoint of discharging charges. At this time, in order to prevent backflow of charges from the FD section 112 to the horizontal charge transfer register 110, a switching element is provided between the reset gate 114 and the power supply 18 (FIG. 3) to connect the reset gate 114 and the power supply 18. It is also effective to eliminate the above or set the voltage of the power supply 18 to 0V.

When stopping the operation of the output circuit 4,
Although the switching element 10 is turned off in the present embodiment, the switching element 10 is not used and the power supply VDD
It is also possible to adopt a method of stopping the operation of the output circuit 4 by switching the voltage of 0 to 0V.

Next, a second embodiment of the present invention will be described. The second embodiment differs from the above embodiments in the configuration of the output circuit. FIG. 4 is a circuit diagram showing an output circuit that constitutes the solid-state imaging device of the second embodiment. In the figure, the same elements as those in FIG. 3 are designated by the same reference numerals, and description thereof will be omitted here.

In the output circuit 32 shown in FIG. 4, a switching element 34 is provided instead of the switching element 10. The drains of the transistors in each stage of the output circuit 32 are all connected to the common terminal 36 of the switching element 34, and one switching terminal 38 of the switching element 34 is connected.
Is the ground, and the other switching terminal 40 is the power supply VD
Connected to D.

In the second embodiment, the control signal 42 is supplied to the switching element 34 in the image output period 124 (FIG. 1) so that the common terminal 36 and the switching terminal 40 are provided.
And the source follower circuit 6
Power is supplied to the source follower circuit 6 while the common terminal 36 and the switching terminal 38 are connected to each other in a period other than the image output period 124, and the power supply to each source follower circuit 6 is stopped. Connect the 6A drain to ground. Therefore, even when the output circuit 32 of the second embodiment is used, the same effect as when the output circuit 4 is used can be obtained. Furthermore, the output circuit 3
In No. 2, since the drain of each transistor 6A is connected to the ground during non-operation, the operation can be more surely stopped.

Next, a third embodiment of the present invention will be described. FIG. 5 is a circuit diagram showing an output circuit that constitutes the solid-state imaging device of the third embodiment. In the figure, the same elements as those in FIG. 3 are designated by the same reference numerals, and description thereof will be omitted here. Output circuit 4 shown in FIG.
In FIG. 4, instead of inserting the switching element 10 on the power supply side like the output circuit 4, the switching element 46 is inserted on the ground side. Therefore, this output circuit 44
Also in the above, the power consumption in the output circuit 44 can be reduced by turning on the switching element 46 only in the image output period 124 (FIG. 1), and the same effect as in the case of the first embodiment can be obtained. You can

Next, a fourth embodiment of the present invention will be described. FIG. 6 is a circuit diagram showing an output circuit that constitutes the solid-state imaging device of the fourth embodiment. In the figure, the same elements as those in FIG. 3 are designated by the same reference numerals, and description thereof will be omitted here. Output circuit 4 shown in FIG.
In No. 8, on / off control of the entire power supply is not performed, and power supply is stopped only in the final stage. That is, in the output circuit 48, the source follower circuit 50 at the final stage is an open source, and the constant current circuit 8 is removed. A constant current circuit 54 is externally connected to the final stage output terminal 52.

The constant current circuit 54, as shown in FIG.
It is composed of a transistor 56, a power supply 58, a resistor 60, and a switching element 62. The collector of the transistor 56 is the source (output terminal 52) of the transistor that constitutes the final source follower circuit 6.
The emitter is at one end of the resistor 60 and the base is the power source 58.
The resistor 60 is connected to the ground through the switching element 46.

Then, in the image output period 124 (FIG. 1), the control signal 64 is supplied to turn on the switching element 62,
The constant current circuit 54 is operated. As a result, the source follower circuit 50 at the final stage operates, and the video signal 126 is output from the output circuit 48. On the other hand, in the periods other than the image output period 124, the switching element 62 is turned off and the operation of the constant current circuit 54 is stopped. As a result, the source follower circuit 50 at the final stage stops operating. Therefore, even when this output circuit 48 is used, the operation of the source follower circuit 50 at the final stage, which consumes the most power among the three stages of source follower circuits constituting the output circuit 48, is performed except during the image output period 124. It can be stopped for a certain period, and power consumption can be reduced.

[0036]

As described above, in the solid-state image pickup device driving method of the present invention, the supply of the transfer clock to the charge transfer register is stopped during the period other than the image output period during which the video signal is output. , The charge transfer register does not operate, and therefore the power consumption of the solid-state image sensor can be reduced as a whole. Further, as a result, the temperature rise of the solid-state image sensor is suppressed, so that noise components such as dark current noise mixed in the video signal can be reduced,
The SN ratio is improved and good image quality is obtained.

In the method for driving the solid-state image pickup device of the present invention, since the power supply to the output circuit is stopped during the period when the video signal is not output, the output circuit does not operate in the period other than the image output period, Therefore, the power consumption of the solid-state imaging device can be reduced as a whole. Further, as a result, the temperature rise of the solid-state image sensor is suppressed, so that noise components such as dark current noise mixed in the video signal can be reduced, the SN ratio is improved, and good image quality can be obtained.

[Brief description of drawings]

FIG. 1 is a timing chart showing an example of a method for driving a solid-state image sensor according to the present invention.

FIG. 2 is a main part schematic plan view showing a solid-state imaging device driven by the method for driving a solid-state imaging device according to the embodiment.

FIG. 3 is a circuit diagram showing in detail an output circuit that constitutes the solid-state image sensor of FIG.

FIG. 4 is a circuit diagram showing another example of an output circuit that constitutes a solid-state image sensor driven by the method of driving the solid-state image sensor according to the embodiment.

FIG. 5 is a circuit diagram showing still another example of the output circuit that constitutes the solid-state imaging device driven by the method of driving the solid-state imaging device according to the embodiment.

FIG. 6 is a circuit diagram showing still another example of the output circuit configuring the solid-state image sensor driven by the method for driving the solid-state image sensor according to the embodiment.

FIG. 7 is a main part schematic plan view showing an example of a conventional general solid-state imaging device.

8 is a timing chart showing a method for driving the solid-state image sensor of FIG.

[Explanation of symbols]

2 ... Solid-state image sensor, 4, 32, 44, 48 ... Output circuit, 6, 50 ... Source follower circuit, 10, 34,
46, 62 ... Switching element, 12, 60 ... Resistor, 14 ... Constant voltage source, 16, 56 ... Transistor, 20 ... Reset clock, 22 ... Vertical transfer clock, 24 ... Read pulse, 26 ... ... horizontal transfer clock, 106 ... photosensor, 108 ... vertical charge transfer register, 110 ... horizontal charge transfer register, 11
2 ... Floating diffusion part (FD part),
114 ... Reset gate.

Claims (6)

[Claims] 1. A plurality of photosensors that receive light to generate signal charges and a charge transfer register that is driven by a transfer clock and transfers the signal charges generated by the photosensors are formed on a semiconductor substrate. A method of driving a solid-state imaging device configured to generate and output a video signal based on the signal charge transferred by the charge transfer register, wherein the transfer is performed during a period in which the solid-state imaging device does not output the video signal. A method for driving a solid-state imaging device, characterized in that supply of a clock to the charge transfer register is stopped. 2. A transfer clock for sweeping out charges held in the charge transfer register when the period in which the solid-state imaging device does not output the video signal ends is supplied to the charge transfer register. Claim 1
A method for driving the solid-state imaging device according to claim 1. 3. The solid-state imaging device includes a charge-voltage converter that converts the signal charge transferred by the charge transfer register into a voltage, and a signal that is driven by a reset clock and stored in the charge-voltage converter. 2. The solid-state image sensor according to claim 1, further comprising a reset gate for discarding charges, wherein the supply of the reset clock to the reset gate is stopped during a period in which the solid-state image sensor does not output the video signal. Driving method. 4. The photosensors are arranged in a matrix on the semiconductor substrate, and the charge transfer registers are vertical charge transfer registers extending along the photosensor columns for each photosensor column. A period in which the solid-state imaging device does not output the video signal, including a horizontal charge transfer register that receives the signal charges generated by the photosensor from the vertical charge transfer register and sequentially transfers the signal charges for each row of the photosensor. 2. The method for driving a solid-state image pickup device according to claim 1, wherein the supply of the transfer clock to the vertical charge transfer register and the horizontal charge transfer register is stopped in step 2. 5. A plurality of photosensors that receive light to generate a signal charge, a charge transfer register that transfers the signal charge generated by the photosensor, and a charge transfer register that is generated based on the signal charge transferred by the charge transfer register. And a method for driving a solid-state imaging device configured by forming an output circuit for outputting a video signal with low impedance on a semiconductor substrate, wherein the output circuit is in a period in which the solid-state imaging device does not output the video signal. A method for driving a solid-state imaging device, characterized in that the power supply to the device is stopped. 6. The transistor of the final means of the output circuit constitutes an open source circuit, and a constant current circuit is connected to the source of the transistor outside the solid-state image pickup device so that the video signal is supplied from the source of the transistor. 6. The method of driving a solid-state image sensor according to claim 5, wherein the operation of the constant current circuit is stopped during a period when the solid-state image sensor is output and the video signal is not output by the solid-state image sensor.