JPH05129446A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device equipped with a highly reliable multilayer wiring structure which can be easily increased in wiring density and easily subjected to planarization as well as its manufacturing method. CONSTITUTION:A multilayer wiring structure is formed by burying a second wiring layer 9 in an insulating film 6 after coating a recessed section 5 which becomes the gap section of a first wiring layer 4 formed on a semiconductor element and a conductive film 14 which connects the first and second wiring layers 4 to each other in an insulating film 10 coating the layers 4 and 9. By effectively utilizing spaces formed between wiring, the wiring structure can be increased in wiring density and subjected to planarization.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a high-density multilayer wiring structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art In order to improve the degree of freedom in wiring design, reduce the area occupied by wiring, and the like, a wiring metal has a multi-layer structure using an interlayer insulating film to achieve high speed and high integration of semiconductor devices. .. For example, the two-layer wiring is formed as follows. 4 (a) to 4 (c) are cross-sectional views showing process steps when the glass coating film 26 is used as an insulating film between the first wiring layer 23 and the second wiring layer 29. For simplification, the step of forming a transistor is omitted and only the step of forming two wiring layers is shown.

First, as shown in FIG. 4A, an insulating film 22 for electrical insulation is formed on a silicon substrate 21, and a first wiring made of an aluminum alloy film is formed on the insulating film 22. After the layer 23 is formed by the sputtering method, the wiring pattern is formed by leaving the wiring layer 23 only in a region necessary for wiring. Next, as shown in FIG. 4B, the first wiring layer 23
An insulating film 25 is formed on the upper surface by a CVD method, and then a glass coating film 26 is applied to fill the recesses 24 formed between the patterns of the first wiring layer 23. Then, the insulating film 27 is changed to C
It is formed by the VD method and covers the glass coating film 26.

Next, as shown in FIG. 4C, a through hole 28 for electrically connecting the first wiring layer 23 and the second wiring layer 29 is formed with a photolithography method and an etching gas. It is formed by a dry etching method using CHF ₃ , N ₂ and O ₂ . Next, as shown in FIG. 4D, an aluminum alloy film to be the second wiring layer 29 is formed by the sputtering method. However, in order to stabilize the contact resistance of the first wiring layer 23 and the second wiring layer 29, before forming the second wiring layer 29, the through hole 28 of the through hole 28 is formed by a sputter etching method using argon ions. The natural oxide film formed on the bottom, that is, on the surface of the first wiring layer 23 is removed.

Next, as shown in FIG. 4 (e), a pattern of the second wiring layer 29 is formed. Then, plasma CV
The silicon nitride film 30 for protection is formed by the D method, and the formation process of the two-layer wiring is completed.

[0006]

However, in order to increase the number of wires in the above-mentioned conventional wiring structure and manufacturing method, there is a problem that the density of the wiring cannot be increased because the number of wiring layers is simply increased. It was Further, since the insulation film between the first wiring layer 23 and the second wiring layer 29 is not sufficiently flattened, there is a problem that it is difficult to form a multilayer wiring. Further, even if the protective film 30 is formed by the CVD method to protect the surface of the second wiring layer 29, the through hole 28 for connecting the first wiring layer 23 and the second wiring layer 29 is formed. There is also a problem that reliability is deteriorated because the protective film 30 is not sufficiently covered in a portion and the intrusion of impurities from the outside cannot be sufficiently prevented.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above problems and to provide a semiconductor device having a multilayer wiring structure which is easy to achieve high density and flattening and has high reliability, and a manufacturing method thereof. ..

[0008]

In order to solve the above problems, the present invention adopts the following configuration. According to another aspect of the present invention, there is provided a semiconductor device comprising: a first wiring layer formed on a semiconductor element; a first insulating film covering a recess formed between the first wiring layer patterns; A second wiring layer embedded in the insulating film, and the first wiring layer and the second wiring layer.
And a second insulating film for covering the wiring layer and a conductive film embedded in the first and second insulating films and connecting the first and second wiring layers.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor manufacturing apparatus, which includes a step of forming a first wiring layer pattern on a semiconductor element and a surface of a recess between the first wiring layer and the first wiring layer pattern. With a first insulating film, a step of burying a second wiring layer in the recess covered with the first insulating film, and a step of coating the buried second wiring layer with a second insulating film. And a step of forming contact holes for connecting both wiring layers in the first and second insulating films covering the first and second wiring layers, and a step of embedding a conductive film in the contact holes. The basic wiring process is used to form a multilayer wiring structure.

[0010]

According to the structure of the invention of claim 1, the second wiring layer and the first wiring layer are embedded in the recesses which are the gaps between the wiring patterns of the first wiring layer. Since they are connected to each other, it is possible to achieve high density and flattening of the wiring by effectively utilizing the space between the wirings.
Further, since the difference in height between the first wiring layer and the second wiring layer is small, the connection between the wirings is easy, the connection portion between the wirings can be formed flat, and the protective film is sufficiently covered. be able to.

According to the configuration of the invention of claim 2, claim 1
Since the semiconductor device of the invention can be easily manufactured, it is possible to provide a semiconductor device having a highly reliable multilayer wiring structure which is excellent in high density and flatness.

[0012]

1 is a cross-sectional view showing a structure of a semiconductor device 1 according to an embodiment of the present invention, in which a recess 5 formed between first wiring layers 4 is provided with a second insulating film 6 interposed therebetween. It has a structure in which the wiring layer 9 is formed. The insulating film 3 formed on the silicon substrate 2 is for electrically insulating the silicon substrate 2 and the first wiring layer 4 made of an aluminum alloy film having a thickness of 1 μm. Recesses 5 formed between the patterns of the first wiring layer 4
The insulating film 6 that covers the surface of the first wiring layer 4 and the first wiring layer 4
Of the Ti / TiN film 7 and the W film 8 formed between the wiring layers 4 of
This is for electrically insulating the second wiring layer 9 composed of layers. The Ti / TiN film 7 is formed by the CVD method W
It is used to improve the adhesion between the film 8 and the insulating film 6. This is because the W film 8 formed by the CVD method is optimal as a filling material, but has poor adhesion with an insulating film such as a silicon oxide film.

Contact hole 10 for first wiring layer 4, second wiring layer 9 composed of two layers of Ti / TiN film 7 and W film 8
A conductive film 14 made up of two layers, a Ti / TiN film 12 and a W film 13, is buried in the first conductive film 14.
The wiring layer 4 and the second wiring layer 9 are connected. Ti /
The TiN film 12 is used to improve the adhesion between the W film 13 formed by the CVD method and the insulating film 6 and the insulating film 10.

As described above, the semiconductor device 1 of the embodiment has the first
The second wiring layer 9 in the concave portion 5 between the wiring patterns of the wiring layer 4 of
And the second wiring layer 9 and the first wiring layer 4 are connected by the conductive film 14, the space between the wirings is effectively used, and the wiring density and the flatness are increased. Is being promoted. Further, since the height difference between the first wiring layer 4 and the second wiring layer 9 becomes small, the wirings can be easily connected, and the connection portion between the wirings can be formed flat.
Since the coating of No. 5 can be sufficiently applied, the reliability for preventing deterioration is also improved.

2A to 2I are cross-sectional views showing a manufacturing process of the semiconductor device 1 shown in FIG. 1. However, for simplification of description, a transistor forming process is omitted and two wiring layers are formed. It shows a process of forming. As shown in FIG. 2 (a),
In order to electrically insulate on the silicon substrate 2, a thickness of 0.
An insulating film 3 having a thickness of 8 μm is formed, and a first wiring layer 4 made of an aluminum alloy film having a thickness of 1 μm is further formed by a sputtering method. After that, the first wiring layer 4 is formed by leaving the aluminum alloy film only in the region necessary for wiring.

Next, as shown in FIG.
An insulating film 6 having a thickness of 4 μm is formed by a plasma CVD method using SiH ₄ and N ₂ O as a reaction gas, and the surface of the first wiring layer 4 and the recess 5 formed between the patterns of the first wiring layer 4 is formed. To coat. Next, as shown in FIG. 2C, a continuous film of Ti film and TiN film with a thickness of 150 nm is formed by the sputtering method.
WF ₆ of Ti / TiN film 7 after forming, the reaction gas,
1 μm thick W is formed by the CVD method using SiH ₄ and H _2.
The film 5 is formed, and the recess 5 formed by the first wiring layer 4 is formed.
Embed. The filling temperature is 400 ° C.

Next, as shown in FIG. 2D, the W film 8 was etched back by a dry etching method using SF ₆ , O ₂ and Ar as etching gases, and Cl ₂ and Ar were used. The Ti / TiN film 7 is etched back by the dry etching method to form the second wiring layer 9. Next, FIG.
As shown in (e), the insulating film 10 having a thickness of 0.4 μm is formed by a plasma CVD method using SiH ₄ and N ₂ O as reaction gases.

Next, as shown in FIG.
A contact hole 11 for connecting the wire layer 4 and the second wiring layer 9 is formed.
CH for photolithography and etching gas
F₃, N ₂, O₂By dry etching method using
To achieve. Next, as shown in FIG. 2 (g),
The TiN / Ti film 12 is formed by the sputtering method.
It However, stable contact resistance with the first wiring layer 4
Sputter etch using argon ions
Before forming TiN / Ti12 by
Bottom of the hole 11, that is, the surface of the first wiring layer 4 and W
The natural oxide film formed on the surface of the film 8 is removed. So
After that, at the film forming temperature of 400 ° C., WF was added to the reaction gas.₆, Si
H_Four, H₂1 μm thick W film 1 by the CVD method using
3 is deposited and the contact hole 11 is buried.

Next, as shown in FIG. 2 (h), the W film 13 is etched back by a dry etching method using SF ₆ , O ₂ , and Ar as etching gases, and Cl ₂ is used as an etching gas. The TiN / Ti film 12 is etched back by a dry etching method using Ar, and the conductive film 14 including the W film 13 and the TiN / Ti film 12 is left only in the contact hole 11, and the first conductive film 14 is used. The wiring 4 and the second wiring layer 9 are connected.

Finally, as shown in FIG. 1 (i), a silicon nitride film 15 having a thickness of 1 μm is formed by a plasma CVD method using SiH ₄ and NH ₃ as a reaction gas to protect the surface. The process of forming the two-layer wiring is completed. In the above-mentioned embodiment, the case of the two-layer wiring has been described, but by repeating the above steps, it is possible to manufacture a semiconductor device having a multilayer wiring structure of three or more layers. Figure 3
FIG. 3 is a cross-sectional view illustrating the configuration of a semiconductor device 20 when four-layer wiring is used. In the above-described embodiment, the recesses of the third wiring layer 16 are covered with a third insulating layer 17, and the third insulating film 17 To the fourth
Embedded in the wiring layer 18 and the third and fourth insulating layers 17, 1
The conductive layer 20 is embedded in the layer 9.

[0021]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, the second wiring layer is embedded in the gap between the patterns of the first wiring layer to form a multilayer wiring structure. , It is now possible to achieve high wiring density by effectively utilizing the space between wirings. Further, since the height difference between the first wiring layer and the second wiring layer can be reduced, the connection between the wirings can be facilitated and the connection portion between the wirings can be formed flat, so that the protective film is sufficiently covered. Therefore, the reliability of preventing deterioration can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.

2A to 2I are cross-sectional views showing a procedure of a manufacturing process of the semiconductor device shown in FIG.

FIG. 3 is a cross-sectional view showing a configuration example in the case where a semiconductor device having a multilayer wiring structure is formed by repeatedly using the manufacturing method of the present invention.

FIG. 4 is a cross-sectional view showing a procedure of a conventional manufacturing process.

[Explanation of symbols]

 1 Semiconductor Device 2 Silicon Substrate 3, 6, 10, 15 Insulating Film 4 First Wiring Layer 5 Recess 9 Second Wiring Layer 11 Contact Hole 14 Conductive Film

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[Procedure amendment]

[Submission date] November 25, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Fig. 2]

[Figure 1]

[Figure 3]

[Figure 4]

Claims (2)

[Claims] 1. A first wiring layer formed on a semiconductor element, a first insulating film covering a concave portion formed between the first wiring layer patterns, and a first insulating film embedded in the first insulating film. A second wiring layer, a second insulating film covering the first wiring layer and the second wiring layer, and the first and second wiring layers embedded in the first and second insulating films A semiconductor device having a multi-layered wiring structure including a conductive film for connecting to each other. 2. A step of forming a first wiring layer pattern on a semiconductor element, and a step of coating a surface of a recess between the first wiring layer and the first wiring layer pattern with a first insulating film. A step of burying a second wiring layer in the recess covered with the first insulating film, a step of coating the buried second wiring layer with a second insulating film, and first and second wiring layers Of a semiconductor device having a multi-layer wiring structure including a step of forming a contact hole for connecting both wiring layers in a first and a second insulating film covering the film and a step of burying a conductive film in the contact hole. Production method.