JPH05129433A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce layout area in a chip, by making a clock driver region which has existed as a unit a vacant region, at the time of pattern design of a clock driver. CONSTITUTION:A unit 106 in a clock driver region which has existed as a unit can be made a completely vacant region, by dividing an element and arranging it at the peripheral part like positions 101 where elements are not present. Hence layout area in a chip can be smaller than the conventional one.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to the pattern design of a clock driver circuit after manufacturing a semiconductor wafer.

[0002]

2. Description of the Related Art An example of a pattern designing pattern of a clock driver in a conventional semiconductor integrated circuit is shown in FIGS.

A conventional clock driver pattern design procedure is, as shown in FIG. 3, constructed inside a chip as one unit.

In FIG. 3, in the present semiconductor integrated circuit, layout units A, B, C and a layout unit 301 of a clock driver are arranged, a guard ring 303 is provided around them, and a large number of pads 302 are arranged. ing. Part of the pattern design of the internal elements of the clock driver is as shown in FIG.

In FIG. 4, there is a guard ring 401, and a part of the element pattern design procedure of the layout unit 301 of the clock driver is partially surrounded by the guard ring 401.

In order to drive the waveform of the clock driven by the clock driver to every corner of the chip, the load is increased and the drive capability of the final stage inverter is increased.
As shown in FIG. 5, the channel width of the transistor must be increased.

FIG. 5 shows a portion 501 for dividing the final stage inverter of the clock driver.

Therefore, it has been a cause of increasing the internal layout area.

[0009]

Since the conventional clock driver described above is arranged inside the chip as one unit as shown in FIG. 3, there is a problem in that the layout area is taken by itself. In addition, the channel width of the transistor is increased in order to increase the driving capability,
There is a problem in that noise is likely to occur in the power supply and ground inside the chip, which may cause malfunction and latch-up.

An object of the present invention is to solve the above problems and to provide a semiconductor integrated circuit in which the layout area can be reduced without increasing the channel width of the transistor.

[0011]

The structure of a semiconductor integrated circuit of the present invention is characterized in that the element is divided and the element is arranged in an empty region outside the guard ring near the peripheral input / output buffer. To do.

[0012]

1 is a circuit diagram showing a semiconductor integrated circuit according to an embodiment of the present invention.

In FIG. 1, in the present embodiment, the unit 106 surrounded by the dotted line in FIG. 1 is the area of the clock driver which is conventionally arranged as one unit. In the area where the elements are not arranged, such as a portion having a wide pad interval, which is an empty area of the input / output buffer 102 in the peripheral portion, or the periphery of the power supply Vcc and the pad 103 of the GND, like the element arrangement position 101 of FIG. The element having a large channel width of the transistor forming the element is divided and arranged.

FIG. 2 is an enlarged view of the internal portion of the dotted line portion 107 in FIG. As shown in FIG. 2, an element 203 obtained by dividing a clock driver is arranged in a vacant region, a wiring 201 connecting the element 203 and the element 203 is passed through the inside of the guard ring 202, passed through the inside of the chip, and circulates inside the chip. Wire along the clock.

The state of the transistor is shown in part 501 of FIG.
The element 203 is arranged in the form of being surrounded by and separated from each other. By arranging the elements of the clock driver separately in the peripheral portion in this manner, it is not necessary to arrange a transistor having a large channel width in the region of the unit 106 inside the chip.

In FIG. 2, the input / output buffers 204 are provided on both sides of the element 203, and the pads 20 are provided below the input / output buffers 204.
The presence of 5 is as shown in FIG.

[0017]

As described above, according to the present invention, the layout area inside the chip can be reduced and the guard area can be reduced by dividing the clock driver and arranging it in the empty area of the peripheral input / output buffer. By being arranged outside the ring, there is an effect of reducing the noise generated inside the chip and the influence of latch-up and the like.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a plan view showing an enlarged part of FIG.

FIG. 3 is a plan view of a conventional clock driver.

FIG. 4 is a plan view showing an enlarged part of FIG.

FIG. 5 is a circuit diagram showing a transistor arrangement of a final stage inverter of a clock driver.

[Explanation of symbols]

A, B, C Layout unit 101 Arrangement position of divided Kudok driver elements 102, 204 Input / output buffers 103, 205, 302 Pads 104, 202, 303, 401 Guard ring 105 Clock wiring 106 Conventional clock driver layout Unit 201 Divided clock driver connection wiring 203 Divided clock driver element 301 Clock driver layout 501 Dividing the last stage inverter of the clock driver

Claims (1)

[Claims] 1. A semiconductor integrated circuit, characterized in that an element constituting a clock driver is divided and the element is arranged in an empty region outside the guard ring near the peripheral input / output buffer.