JPH05129373A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH05129373A JPH05129373A JP3313774A JP31377491A JPH05129373A JP H05129373 A JPH05129373 A JP H05129373A JP 3313774 A JP3313774 A JP 3313774A JP 31377491 A JP31377491 A JP 31377491A JP H05129373 A JPH05129373 A JP H05129373A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- resin
- pins
- semiconductor device
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は信頼性の高い実装構造の
半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a highly reliable mounting structure and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来、実装構造の簡略化を図った半導体
装置として、図７に示すフリップチップ構造が提案され
ている。これは、半導体チップ１の電極パッド３上に半
田等でバンプ９を形成し、この半導体チップ１のバンプ
９の形成面を下向きにしてプリント基板２のボンディン
グパッド４に直接バンプ９を溶融接続したものである。
又、半導体チップの保護のために例えばエポキシ樹脂等
の樹脂８で封止している。しかしながら、この構造で
は、半導体チップ１とプリント基板２の間に熱膨張係数
の相違があると、半導体チップにストレスが発生し、半
導体チップに割れが発生して信頼性が低下されるおそれ
がある。2. Description of the Related Art Conventionally, a flip chip structure shown in FIG. 7 has been proposed as a semiconductor device having a simplified mounting structure. This is because bumps 9 are formed on the electrode pads 3 of the semiconductor chip 1 by soldering or the like, and the bumps 9 of the semiconductor chip 1 are directly connected to the bonding pads 4 of the printed circuit board 2 with the surface of the bumps 9 facing downward. It is a thing.
Further, for protection of the semiconductor chip, it is sealed with a resin 8 such as an epoxy resin. However, in this structure, if there is a difference in thermal expansion coefficient between the semiconductor chip 1 and the printed circuit board 2, stress may be generated in the semiconductor chip, and the semiconductor chip may be cracked to reduce reliability. ..
【０００３】このため、近年では図８のように、ピンを
用いた接続構造が提案されている。これは半導体チップ
１の電極パッド３上に微小長さの導体ピン７を立設し、
このピン７の他端をプリント基板２のボンディングパッ
ド４に接続するものである。８は封止用の樹脂である。
この構造では、半導体チップ１とプリント基板２の間の
熱膨張係数の相違により発生するストレスをピン７の変
形によって吸収し、半導体チップ１の割れを防止するこ
とができる。Therefore, in recent years, a connection structure using pins has been proposed as shown in FIG. This is because a minute length of the conductor pin 7 is erected on the electrode pad 3 of the semiconductor chip 1,
The other end of the pin 7 is connected to the bonding pad 4 of the printed board 2. Reference numeral 8 is a resin for sealing.
In this structure, the stress generated due to the difference in thermal expansion coefficient between the semiconductor chip 1 and the printed circuit board 2 can be absorbed by the deformation of the pin 7, and the semiconductor chip 1 can be prevented from cracking.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、このピ
ン方式による半導体装置では、実装後に半導体チップ１
を封止するための樹脂８をプリント基板２と半導体チッ
プ１の間に完全に充填させるのが非常に難しく、さらに
これを確認することが難しいという問題がある。このよ
うに樹脂８の充填が不完全であると、生じた空隙を通し
て外部から水分が侵入され、半導体チップ１の耐水性が
劣化されることになる。又、半導体チップをプリント基
板に実装する時の不注意によってピン７に曲がりが発生
したり、樹脂８を封入する時の充填圧力等によってピン
曲がりが発生することがあり、このピン曲がりによって
ピンの他端をプリント基板に対して同一平面に揃えるこ
とが難しく、接続不良が生じるおそれがあるという問題
もある。本発明の目的は、耐水性に優れ、ピン曲がりや
ピンの接続不良を防止して信頼性の高い実装構造の半導
体装置及びその製造方法を提供することにある。However, in this semiconductor device of the pin system, the semiconductor chip 1 is mounted after mounting.
There is a problem that it is very difficult to completely fill the space between the printed board 2 and the semiconductor chip 1 with the resin 8 for encapsulating, and it is difficult to confirm this. If the resin 8 is not completely filled in this way, moisture will enter from the outside through the generated voids and the water resistance of the semiconductor chip 1 will deteriorate. In addition, the pin 7 may be bent due to carelessness when mounting the semiconductor chip on a printed circuit board, or the pin may be bent due to the filling pressure when the resin 8 is sealed. There is also a problem in that it is difficult to align the other end on the same plane with the printed circuit board, which may result in poor connection. It is an object of the present invention to provide a semiconductor device having a mounting structure which is excellent in water resistance, prevents pin bending and pin connection failure, and has high reliability, and a manufacturing method thereof.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置は、
プリント基板に設けたボンディングパッドと、半導体チ
ップの電極パッドとを対向配置させ、かつ複数本の導体
ピンを絶縁体に貫通支持させたボンディング構体を介し
てボンディングパッドと電極パッドとを電気接続する。
又、本発明の半導体装置の製造方法は、複数本の導体ピ
ンを半導体チップの電極パッド及びプリント基板のボン
ディングパッドに対応する位置に略垂直に立てる工程
と、これらのピンをその両端が露呈されるように絶縁体
で支持させる工程と、前記ピンの各端にプリント基板の
ボンディングパッドと半導体チップの電極パッドを夫々
接続する工程を含んでいる。The semiconductor device of the present invention comprises:
A bonding pad provided on a printed circuit board and an electrode pad of a semiconductor chip are arranged so as to face each other, and the bonding pad and the electrode pad are electrically connected via a bonding structure in which a plurality of conductor pins are penetratingly supported by an insulator.
Further, the method of manufacturing a semiconductor device of the present invention comprises a step of vertically setting a plurality of conductor pins at positions corresponding to electrode pads of a semiconductor chip and bonding pads of a printed circuit board, and exposing these pins at both ends. Thus, the step of supporting with an insulator, and the step of connecting the bonding pad of the printed board and the electrode pad of the semiconductor chip to each end of the pin are included.
【０００６】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の第１実施例の断面図である。同図に
おいて、１は半導体チップ、２はプリント基板である。
半導体チップ１には所要の電極パッド３が形成される。
又、プリント基板２にも半導体チップの電極パッド３に
対応する位置にボンディングパッド４が形成される。そ
して、半導体チップ１とプリント基板２の間には、樹脂
６に複数本の導体ピン７を貫通支持させたボンディング
構体５を介挿させ、このボンディング構体５によって前
記電極パッド３とボンディングパッド４とを相互に接続
している。更に、半導体チップ１とボンディング構体５
を樹脂８で封止している。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a first embodiment of the present invention. In the figure, 1 is a semiconductor chip and 2 is a printed circuit board.
Required electrode pads 3 are formed on the semiconductor chip 1.
Further, a bonding pad 4 is also formed on the printed board 2 at a position corresponding to the electrode pad 3 of the semiconductor chip. Then, between the semiconductor chip 1 and the printed circuit board 2, a bonding structure 5 in which a plurality of conductor pins 7 are pierced and supported by a resin 6 is inserted, and by this bonding structure 5, the electrode pad 3 and the bonding pad 4 are connected. Are connected to each other. Furthermore, the semiconductor chip 1 and the bonding structure 5
Are sealed with resin 8.
【０００７】図１の半導体装置の製造方法を図２に示
す。先ず、図２（ａ）に示すように、底面にピン立て用
の穴を有し、かつテフロン材等の樹脂との離型性の良い
材質、或いはこのような材質を内面にコーティングした
治具容器１０に、半田等を被覆したピン７の下端を挿入
し、振動を加えながらかつ周動を加えてピン７を立てた
状態とし、半田溶融して固定する。穴がない場合は半田
等の接着材をピンに被覆し、直接治具容器１０に半田溶
融してピンを立てる。FIG. 2 shows a method of manufacturing the semiconductor device of FIG. First, as shown in FIG. 2A, a material having a pin stand hole on the bottom surface and having a good mold releasability from a resin such as a Teflon material, or a jig having an inner surface coated with such a material. The lower end of the pin 7 coated with solder or the like is inserted into the container 10, and while the vibration is being applied, the pin 7 is erected while being circulated, and the solder is melted and fixed. If there are no holes, the pins are covered with an adhesive such as solder, and the pins are raised by directly melting the solder in the jig container 10.
【０００８】次いで、図２（ｂ）のように、前記各ピン
７の上端をガイドする穴を有するカバー１１を治具容器
１０上に被せる。このカバー１１は前記治具容器１０と
同様に少なくとも表面に樹脂との離型性の良いコーティ
ング材をコーティングしている。これにより、各ピン７
は垂直状態に保持される。その上で、治具容器１０とカ
バー１１との空間内に固定用樹脂６を充填させる。この
樹脂６には、硬化後もゴム状であるシリコンや熱膨張係
数を設計できるポリイミド樹脂等からなる樹脂が用いら
れる。Next, as shown in FIG. 2B, the jig container 10 is covered with a cover 11 having a hole for guiding the upper end of each pin 7. Similar to the jig container 10, at least the surface of the cover 11 is coated with a coating material having good releasability from resin. This allows each pin 7
Is held in a vertical position. Then, the fixing resin 6 is filled in the space between the jig container 10 and the cover 11. As the resin 6, a resin made of silicon, which is rubber-like even after curing, or a polyimide resin, which can be designed for a thermal expansion coefficient, is used.
【０００９】その後、加熱して充填した樹脂６を硬化さ
せる。この樹脂６の硬化によって、図２（ｃ）のよう
に、樹脂を治具容器１０から取り出しても、各ピン７は
樹脂６によって垂直状態に保持された状態に保たれる。
これによりボンディング構体５が形成される。尚、この
硬化に際しては、前記カバー１１にアルミニウム等の熱
吸収材を用い、各ピン７に接触しない状態であれば、カ
バー１１をそのまま残しておいてもよい。又、ボンディ
ング構体５を治具容器１０取り出した後に、必要に応じ
てピン７の長さを所定の長さに切断して長さを調整する
こともできる。更に、ピンの上端及び下端に夫々バンプ
９を形成してもよいAfter that, the filled resin 6 is cured by heating. Due to the curing of the resin 6, even if the resin is taken out from the jig container 10 as shown in FIG. 2C, the pins 7 are maintained in the vertical state by the resin 6.
As a result, the bonding structure 5 is formed. At the time of this curing, a heat absorbing material such as aluminum may be used for the cover 11, and the cover 11 may be left as it is as long as it does not come into contact with the pins 7. Further, after taking out the bonding structure 5 from the jig container 10, the length of the pin 7 can be cut into a predetermined length as necessary to adjust the length. Furthermore, bumps 9 may be formed on the upper and lower ends of the pin, respectively.
【００１０】しかる上で、図２（ｄ）のように、このボ
ンディング構体５の各ピン７の上端をバンプ９の溶融に
より半導体チップ１の電極パッド３に接続する。この状
態で、必要に応じて各ピン７の下端を試験装置等に接続
して半導体チップ１の電気選別を行ってもよい。次い
で、半導体チップ１を接続したボンディング構体５をプ
リント基板２上に置き、バンプ９の溶融にて各ピン７の
下端をプリント基板２に接続する。その上で全体を樹脂
８で封止することで、図１の半導体装置が完成する。Then, as shown in FIG. 2D, the upper ends of the pins 7 of the bonding structure 5 are connected to the electrode pads 3 of the semiconductor chip 1 by melting the bumps 9. In this state, the lower end of each pin 7 may be connected to a testing device or the like as needed to perform electrical selection of the semiconductor chip 1. Next, the bonding structure 5 to which the semiconductor chip 1 is connected is placed on the printed board 2, and the lower ends of the pins 7 are connected to the printed board 2 by melting the bumps 9. Then, the whole is sealed with a resin 8 to complete the semiconductor device of FIG.
【００１１】この半導体装置によれば、ピン７は樹脂６
により支持されているので、接続工程の不注意によって
ピン６が曲げられることは少なくなる。又、最終工程で
樹脂８で封止するときに樹脂の充填圧力によってもピン
が曲がることはない。更に、半導体チップ１とプリント
基板２との間にはボンディング構体５の樹脂６が存在し
ているため、半導体チップとプリント基板との間に樹脂
８を充填させなくとも、封止性を高め、耐水性を向上さ
せることができる。According to this semiconductor device, the pin 7 is made of the resin 6
Since it is supported by, the pin 6 is less likely to be bent by the carelessness of the connection process. Further, the pins are not bent by the filling pressure of the resin when sealing with the resin 8 in the final step. Further, since the resin 6 of the bonding structure 5 exists between the semiconductor chip 1 and the printed board 2, the sealing property is improved without filling the resin 8 between the semiconductor chip and the printed board. Water resistance can be improved.
【００１２】尚、ボンディング構体のピンの端部にバン
プを形成する代わりに、半導体チップ１の電極パッド３
上にバンプを形成してもよい。この場合、バンプの製造
方法は従来の方法を用いて実施することができる。例え
ば、半導体チップ１の電極パッド３面にＴｉ，Ｃｒ，Ｐ
ｂ−Ｓｎ等の金属膜をメッキ法により形成してバンプ形
成を行う。又、このバンプ形成はメッキ法の他に特開昭
49−52973 号で開示されているように、Ａｕ，Ｐｂ−Ｓ
ｎ等からなるワイヤーを接続した上で根本から切断する
方法や溶融半田中に浸漬してパッド電極上のみに半田バ
ンプを形成する方法等、従来のバンプ形成法を利用する
ことができる。Instead of forming bumps on the ends of the pins of the bonding structure, the electrode pads 3 of the semiconductor chip 1 are used.
You may form a bump on it. In this case, the bump manufacturing method can be performed using a conventional method. For example, on the surface of the electrode pad 3 of the semiconductor chip 1, Ti, Cr, P
A bump is formed by forming a metal film such as b-Sn by a plating method. In addition to the plating method, this bump is formed by
As disclosed in 49-52973, Au, Pb-S
A conventional bump forming method such as a method of connecting a wire made of n or the like and then cutting it from the root or a method of immersing in a molten solder to form a solder bump only on the pad electrode can be used.
【００１３】尚、図３に示すように、ボンディング構体
５の樹脂６の周辺部を上側に突設してダム６ａを設けて
おき、このダム６ａを利用して樹脂６と半導体チップ１
との間に樹脂８を充填することで、半導体チップの封止
効果を高めるようにしてもよい。As shown in FIG. 3, a peripheral portion of the resin 6 of the bonding structure 5 is provided on the upper side to project a dam 6a, and the dam 6a is utilized to utilize the resin 6 and the semiconductor chip 1.
The sealing effect of the semiconductor chip may be enhanced by filling the resin 8 between the space and the space.
【００１４】図４は前記製造方法の他の方法を工程順に
示す断面図である。先ず、図４（ａ）のように、複数本
の導体ピン７をプリント基板２のボンディングパッド４
上に直接接続する。この場合、ピン７に半田等を被覆し
熱溶融により接続する。そして、このプリント基板２上
に前記ピン７を包囲するように樹脂ダム１３を形成す
る。次いで、図４（ｂ）のように、ピン７を垂直状態に
保持するカバー１４を被せ、前記樹脂ダム１３とカバー
１４との間の空間に樹脂６を充填する。そして、図４
（ｃ）のように、樹脂６が硬化するまで加熱し、カバー
１４を取り除く。カバー１４に熱吸収材を用いた場合は
取り除かなくてよい。又、場合によっては樹脂ダム１３
も取り除かなくともよい。その後、ピン７の上端にバン
プ９を形成し、これに対して半導体チップ１の電極パッ
ド３を接続することで図１の半導体装置が完成する。FIG. 4 is a cross-sectional view showing another method of the manufacturing method in the order of steps. First, as shown in FIG. 4A, the plurality of conductor pins 7 are connected to the bonding pads 4 of the printed circuit board 2.
Connect directly on. In this case, the pins 7 are covered with solder or the like and are connected by heat fusion. Then, a resin dam 13 is formed on the printed circuit board 2 so as to surround the pin 7. Next, as shown in FIG. 4B, a cover 14 holding the pins 7 in a vertical state is covered, and the space between the resin dam 13 and the cover 14 is filled with the resin 6. And FIG.
As shown in (c), the resin 6 is heated until it hardens, and the cover 14 is removed. If a heat absorbing material is used for the cover 14, it need not be removed. In some cases, resin dam 13
Need not be removed. Then, bumps 9 are formed on the upper ends of the pins 7 and the electrode pads 3 of the semiconductor chip 1 are connected to the bumps 9 to complete the semiconductor device of FIG.
【００１５】図５は本発明の半導体装置の第２実施例の
断面図である。同図において、１は半導体チップ、２は
プリント基板、５Ａはボンディング構体である。このボ
ンディング構体は絶縁基板６Ａに複数本のピン７を貫通
支持し、その上端及び下端を夫々半導体チップ１の電極
パッド３とプリント基板２のボンディングパッド４に接
続している。この絶縁基板６Ａは、各ピン７に接続され
る配線層７Ａを多層に形成した多層配線基板として構成
している。FIG. 5 is a sectional view of a second embodiment of the semiconductor device of the present invention. In the figure, 1 is a semiconductor chip, 2 is a printed circuit board, and 5A is a bonding structure. The bonding structure has a plurality of pins 7 penetratingly supported on the insulating substrate 6A, and the upper and lower ends thereof are connected to the electrode pads 3 of the semiconductor chip 1 and the bonding pads 4 of the printed circuit board 2, respectively. This insulating substrate 6A is configured as a multilayer wiring substrate in which wiring layers 7A connected to each pin 7 are formed in multiple layers.
【００１６】図６は図５の半導体装置の製造方法を工程
順に示す断面図である。先ず、図６（ａ）のように、多
層配線７Ａを形成した多層配線基板６Ａにポンチ等によ
りスルーホール７ａを空ける。そして、図６（ｂ）のよ
うに、各スルーホール７ａに導体ピン７を挿入し、各ピ
ン７には夫々配線層７Ａが個別に接続されるようにす
る。この時、多層配線基板６Ａとの密着性を増すために
予めピン７に半田等を被覆しておき挿入後熱溶融しても
よい。6A to 6C are sectional views showing a method of manufacturing the semiconductor device of FIG. First, as shown in FIG. 6A, a through hole 7a is formed by punching or the like in the multilayer wiring board 6A on which the multilayer wiring 7A is formed. Then, as shown in FIG. 6B, the conductor pin 7 is inserted into each through hole 7 a so that the wiring layer 7 A is individually connected to each pin 7. At this time, in order to increase the adhesiveness with the multilayer wiring board 6A, the pins 7 may be coated with solder or the like in advance and heat-melted after insertion.
【００１７】しかる上で、ピン７の上端及び下端にバン
プ９を形成した上で、上端を半導体チップ１の電極パッ
ド３に接続し、下端をプリント基板２のボンディングパ
ッド４に接続し、その後多層配線基板６Ａの周囲部分を
切断除去することで図５の半導体装置が完成される。こ
の製造方法では、半導体チップ１をプリント基板２に接
続し、多層配線基板６Ａを切断する前に、各配線層７Ａ
に接続される電気選別用パッド７Ｂを利用して通電を行
なうことで、半導体チップ１の電気選別を行うことがで
きる。Then, bumps 9 are formed on the upper and lower ends of the pin 7, the upper end is connected to the electrode pad 3 of the semiconductor chip 1, the lower end is connected to the bonding pad 4 of the printed board 2, and then the multilayer structure is formed. The semiconductor device of FIG. 5 is completed by cutting and removing the peripheral portion of the wiring board 6A. In this manufacturing method, the semiconductor chip 1 is connected to the printed board 2 and each wiring layer 7A is formed before cutting the multilayer wiring board 6A.
Electricity can be selected for the semiconductor chip 1 by supplying electricity using the electric selection pad 7B connected to.
【００１８】[0018]
【発明の効果】以上説明したように本発明の半導体装置
及びその製造方法によれば、半導体チップとプリント基
板を絶縁体で支持されたピンによって接続しているの
で、両者の熱膨張の違いにより起こる半導体チップの割
れを防ぐことができるとともに、絶縁体によってピン曲
がり防ぎ、かつピンの接続不良を防止して信頼性の高い
実装構造を得ることができる。As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, since the semiconductor chip and the printed circuit board are connected by the pins supported by the insulator, there is a difference in thermal expansion between the two. It is possible to prevent the semiconductor chip from cracking, prevent the pin from being bent by the insulator, and prevent the pin from being defectively connected to obtain a highly reliable mounting structure.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の半導体装置の第１実施例の断面図であ
る。FIG. 1 is a cross-sectional view of a first embodiment of a semiconductor device of the present invention.
【図２】図１の半導体装置の製造方法を工程順に示す断
面図である。FIG. 2 is a cross-sectional view showing a method of manufacturing the semiconductor device of FIG. 1 in process order.
【図３】図１の半導体装置の変形例の断面図である。3 is a cross-sectional view of a modified example of the semiconductor device of FIG.
【図４】図１の半導体装置の他の製造方法を工程順に示
す断面図である。4A to 4C are cross-sectional views showing another method of manufacturing the semiconductor device of FIG.
【図５】本発明の半導体装置の第２実施例の断面図であ
る。FIG. 5 is a sectional view of a second embodiment of the semiconductor device of the present invention.
【図６】図５の半導体装置の製造方法を工程順に示す断
面図である。6A to 6C are cross-sectional views showing a method of manufacturing the semiconductor device of FIG.
【図７】従来の半導体装置の一例の断面図である。FIG. 7 is a cross-sectional view of an example of a conventional semiconductor device.
【図８】従来の半導体装置の他の例の断面図である。FIG. 8 is a cross-sectional view of another example of a conventional semiconductor device.
１ 半導体チップ ２ プリント基板 ３ 電極パッド ４ ボンディングパッド ６ 樹脂 ７ ピン ８ 樹脂 1 Semiconductor Chip 2 Printed Circuit Board 3 Electrode Pad 4 Bonding Pad 6 Resin 7 Pin 8 Resin
Claims (2)
ドと、半導体チップの電極パッドとを対向配置させ、か
つ複数本の導体ピンを絶縁体に貫通支持させたボンディ
ング構体を介して前記ボンディングパッドと電極パッド
とを電気接続したことを特徴とする半導体装置。1. A bonding pad provided on a printed circuit board and an electrode pad of a semiconductor chip are arranged to face each other, and the bonding pad and the electrode pad are arranged via a bonding structure in which a plurality of conductor pins are supported by an insulator. A semiconductor device characterized by being electrically connected to and.
パッド及びプリント基板のボンディングパッドに対応し
た位置に略垂直に立てる工程と、これらのピンをその両
端が露呈されるように絶縁体で支持させる工程と、前記
ピンの各端にプリント基板のボンディングパッドと半導
体チップの電極パッドを夫々接続する工程を含むことを
特徴とする半導体装置の製造方法。2. A step of vertically standing a plurality of conductor pins at positions corresponding to electrode pads of a semiconductor chip and bonding pads of a printed circuit board, and supporting these pins with an insulator so that both ends thereof are exposed. And a step of connecting a bonding pad of a printed circuit board and an electrode pad of a semiconductor chip to each end of the pin, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3313774A JPH05129373A (en) | 1991-10-31 | 1991-10-31 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3313774A JPH05129373A (en) | 1991-10-31 | 1991-10-31 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05129373A true JPH05129373A (en) | 1993-05-25 |
Family
ID=18045363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3313774A Pending JPH05129373A (en) | 1991-10-31 | 1991-10-31 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05129373A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1085565A2 (en) * | 1999-09-14 | 2001-03-21 | Casio Computer Co., Ltd. | Semiconductor device having sealing film formed on the surface having columnar electrodes thereon and method of manufacturing the same |
| US7436071B2 (en) | 1997-03-10 | 2008-10-14 | Seiko Epson Corporation | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board |
-
1991
- 1991-10-31 JP JP3313774A patent/JPH05129373A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7436071B2 (en) | 1997-03-10 | 2008-10-14 | Seiko Epson Corporation | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board |
| US7598619B2 (en) | 1997-03-10 | 2009-10-06 | Seiko Epson Corporation | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board |
| US7932612B2 (en) | 1997-03-10 | 2011-04-26 | Seiko Epson Corporation | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board |
| US8134237B2 (en) | 1997-03-10 | 2012-03-13 | Seiko Epson Corporation | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board |
| EP1085565A2 (en) * | 1999-09-14 | 2001-03-21 | Casio Computer Co., Ltd. | Semiconductor device having sealing film formed on the surface having columnar electrodes thereon and method of manufacturing the same |
| EP1085565A3 (en) * | 1999-09-14 | 2001-07-04 | Casio Computer Co., Ltd. | Semiconductor device having sealing film formed on the surface having columnar electrodes thereon and method of manufacturing the same |
| US6472249B1 (en) | 1999-09-14 | 2002-10-29 | Casio Computer Co., Ltd. | Semiconductor device having sealing film formed on the surface having columnar electrode formed thereon and method of manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5717252A (en) | Solder-ball connected semiconductor device with a recessed chip mounting area | |
| JP3604248B2 (en) | Method for manufacturing semiconductor device | |
| TW501208B (en) | Semiconductor device and manufacturing method of the same | |
| US5841192A (en) | Injection molded ball grid array casing | |
| US5672912A (en) | Resin-sealed type semiconductor device and method for manufacturing the same | |
| US6198165B1 (en) | Semiconductor device | |
| US20040048418A1 (en) | Low cost and compliant microelectronic packages for high I/O and fine pitch | |
| KR100323194B1 (en) | Semiconductor device and manufacturing method thereof | |
| US5736789A (en) | Ball grid array casing for integrated circuits | |
| JP2001015650A (en) | Ball grid array package and its manufacture | |
| JP2000200870A (en) | Semiconductor device and manufacture thereof | |
| JP2000150716A (en) | Package structure and semiconductor device, manufacture of package and semiconductor device | |
| JPH05129373A (en) | Semiconductor device and manufacture thereof | |
| JP3309832B2 (en) | Connection structure and connection method for electronic components | |
| US8168525B2 (en) | Electronic part mounting board and method of mounting the same | |
| JP3686047B2 (en) | Manufacturing method of semiconductor device | |
| JP3763962B2 (en) | Mounting method of chip parts on printed circuit board | |
| KR20060108742A (en) | Semiconductor chip package | |
| JP2001168224A (en) | Semiconductor device, electronic circuit device, and its manufacturing method | |
| JP3676590B2 (en) | Semiconductor device | |
| JPH09283555A (en) | Mounting structure of semiconductor chip, manufacture of semiconductor package and semiconductor package | |
| JPH10335386A (en) | Semiconductor mounting method | |
| JPH10126044A (en) | Structure and method for flip chip mounting and flip chip | |
| JP2001332584A (en) | Semiconductor device and method of manufacturing the same, and substrate and semiconductor chip | |
| US20030001262A1 (en) | Semiconductor device having solder bumps and method for manufacturing same |