JPH05129315A - Semiconductor device operated at low temperature - Google Patents

Semiconductor device operated at low temperature

Info

Publication number
JPH05129315A
JPH05129315A JP29124991A JP29124991A JPH05129315A JP H05129315 A JPH05129315 A JP H05129315A JP 29124991 A JP29124991 A JP 29124991A JP 29124991 A JP29124991 A JP 29124991A JP H05129315 A JPH05129315 A JP H05129315A
Authority
JP
Japan
Prior art keywords
emitter
base
region
collector
concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29124991A
Other languages
Japanese (ja)
Inventor
Masabumi Miyamoto
正文 宮本
Kazuo Yano
和男 矢野
Koichi Seki
浩一 関
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP29124991A priority Critical patent/JPH05129315A/en
Publication of JPH05129315A publication Critical patent/JPH05129315A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To obtain a bipolar transistor wherein it is provided with a base concentration distribution which shortens the base delay time at a low temperature of 200 deg. K or lower and it is suitable for a high-speed operation by a method wherein the impurity concentration on the side of a collector of a base region is set to a concentration which is higher than the impurity concentration on the side of an emitter of the base region. CONSTITUTION:A bipolar transistor is constituted in the following manner: it is operated at a low temperature of 200 deg. K or lower; carrier; to be used as an emitter current or a collector current flow from an emitter region 8 formed on the surface of a semiconductor substrate 1 toward a collector region 2 formed at the inside of the semiconductor substrate 1. In the bipolar transistor, the impurity concentration on the side of the collector 2 of a base region 7 is set to a concentration which is higher than the impurity concentration on the side of the emitter 8 of the base region 7. For example, when a base region 7 is formed by a low-temperature epitaxial growth operation, the amount of boron as a dopant is controlled, it is set at 3X10<19>/cm<3> at the beginning, and the amount of impurities is reduced to 3X10<18>/ cm<3> while 100nm is grown.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はバイポーラ型の半導体装
置に係り、特に200K以下の低温で動作するととも
に、半導体基板の表面に形成されたエミッタ領域から該
半導体基板の内部に形成されたコレクタ領域に向かって
エミッタ電流もしくはコレクタ電流となるキャリヤが流
れる如く構成された所謂順方向動作のバイポーラトラン
ジスタもしくは半導体基板表面にエミッタ領域とコレク
タ領域が形成された所謂ラテラルトランジスタに関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar type semiconductor device, and in particular, it operates at a low temperature of 200 K or less, and has an emitter region formed on the surface of a semiconductor substrate and a collector region formed inside the semiconductor substrate. The present invention relates to a so-called forward operation bipolar transistor configured so that a carrier that becomes an emitter current or a collector current flows toward a so-called lateral transistor in which an emitter region and a collector region are formed on a semiconductor substrate surface.

【0002】[0002]

【従来の技術】バイポーラトランジスタの高速動作のた
めにベース濃度分布を工夫した従来例として、例えば、
菅野卓雄監修「超高速バイポーラデバイス」培風館、p
36に述べられている傾斜型ベース濃度分布が知られて
いる。これは図5にその導電不純物の濃度分布を示すよ
うにベース領域7の濃度がエミッタ側で高く、コレクタ
側で低くなっていいる。このベース領域7の濃度分布に
よれば、濃度による擬フェルミレベルの違いからポテン
シャルエネルギーがコレクタ側で低くなり、ベース領域
を走行するキャリアを加速する内蔵電界が生ずる。
2. Description of the Related Art As a conventional example in which a base concentration distribution is devised for high speed operation of a bipolar transistor, for example,
Super-high-speed bipolar device supervised by Takuo Sugano, Baifukan, p
The graded base concentration distribution described in 36 is known. This is because the concentration of the base region 7 is high on the emitter side and low on the collector side, as shown in the concentration distribution of the conductive impurities in FIG. According to the concentration distribution of the base region 7, the potential energy becomes low on the collector side due to the difference in pseudo Fermi level depending on the concentration, and an internal electric field that accelerates the carriers traveling in the base region is generated.

【0003】通常キャリアは拡散によりベースを走行す
るが、この内蔵電界によりドリフトで走行する効果が生
ずるのでベース走行時間が通常の1/2から1/3程度
に短縮される。また、この濃度分布はベース形成に一般
的に用いられる不純物熱拡散もしくはイオン打ち込みに
より、容易に形成することができる。
Normally, carriers travel in the base by diffusion, but the built-in electric field produces an effect of traveling by drift, so that the base travel time is shortened from 1/2 to 1/3 of the normal time. Further, this concentration distribution can be easily formed by thermal diffusion of impurities or ion implantation generally used for forming a base.

【0004】[0004]

【発明が解決しようとする課題】従来の傾斜型ベース濃
度分布は室温では確かに効果があるが、200K以下の
低温動作を考慮したものではない。すなわち、擬フェル
ミレベルは温度に比例するため、低温になるに従い濃度
による擬フェルミレベルの差は小さくなってしまう。こ
のため低温になるに従いベース領域内の内蔵電界も低下
して、ベース遅延時間の短縮効果は減少する。
Although the conventional graded base concentration distribution is certainly effective at room temperature, it does not consider low temperature operation below 200K. That is, since the pseudo Fermi level is proportional to the temperature, the difference in the pseudo Fermi level due to the concentration becomes smaller as the temperature becomes lower. Therefore, as the temperature becomes lower, the built-in electric field in the base region also decreases, and the effect of shortening the base delay time decreases.

【0005】また、従来例では室温動作を考えていたた
め不純物によるバンドギャップ縮小効果に対し十分な配
慮がされていなかった。バンドギャップ縮小効果は濃度
が高いほど強くなり、温度にはほとんど依存しない。そ
のため低温ではバンドギャップ縮小の差による内蔵電界
の方がフェルミレベルの差による内蔵電界と比較して相
対的に大きくなる。バンドギャップ縮小効果は濃度の高
い方が大きいため、従来の濃度分布ではエミッタ側のバ
ンドギャップが小さくなり、キャリアをエミッタ側に引
き戻す方向に内蔵電界が生ずる。これにより、低温では
傾斜型濃度分布のベース遅延時間が均一濃度分布よりも
長くなるという問題が起きる。
Further, in the conventional example, since the operation at room temperature was considered, sufficient consideration was not given to the bandgap reduction effect due to impurities. The bandgap reduction effect becomes stronger as the concentration increases, and hardly depends on the temperature. Therefore, at low temperatures, the built-in electric field due to the difference in bandgap reduction becomes relatively larger than the built-in electric field due to the difference in Fermi level. Since the higher the concentration is, the larger the bandgap reduction effect is, the bandgap on the emitter side becomes smaller in the conventional concentration distribution, and an internal electric field is generated in the direction in which carriers are pulled back to the emitter side. This causes a problem that the base delay time of the gradient concentration distribution becomes longer than the uniform concentration distribution at low temperature.

【0006】また、従来の傾斜型濃度分布のバイポーラ
トランジスタでは、半導体基板の表面に形成されたエミ
ッタ領域をコレクタとして動作させ、半導体基板の内部
に形成されたコレクタ領域をエミッタとして動作させ、
半導体基板の内部から半導体基板の表面にエミッタ電流
もしくはコレクタ電流となるキャリヤが流れる如く構成
された所謂逆方向動作のモードでは上記の問題は生じな
いが、逆に逆方向動作に特有なエミッタ遅延時間の増加
や高いエミッタ抵抗,外部ベースへのキャリア注入の影
響により、高速動作には適さないという問題がある。
Further, in the conventional bipolar transistor having a gradient concentration distribution, the emitter region formed on the surface of the semiconductor substrate is operated as the collector, and the collector region formed inside the semiconductor substrate is operated as the emitter.
The above-mentioned problem does not occur in the so-called reverse operation mode in which the carrier serving as the emitter current or the collector current flows from the inside of the semiconductor substrate to the surface of the semiconductor substrate, but the emitter delay time peculiar to the reverse operation does not occur. Increase, high emitter resistance, and influence of carrier injection into the external base, there is a problem that it is not suitable for high speed operation.

【0007】本発明の目的は、200K以下の低温にお
いてベース遅延時間を短縮するベース濃度分布を持ち、
高速動作に適したバイポーラトランジスタを提供するこ
とである。
An object of the present invention is to have a base concentration distribution that shortens the base delay time at a low temperature of 200 K or less,
It is to provide a bipolar transistor suitable for high speed operation.

【0008】[0008]

【課題を解決するための手段】本発明の代表的な実施形
態による所謂順方向動作のバイポーラトランジスタ基本
的濃度分布を図1に示すように、従来の傾斜型ベース濃
度分布とは逆にベース領域7のコレクタ側の不純物濃度
をエミッタ側よりも高くされている。
As shown in FIG. 1, a so-called forward operation bipolar transistor basic concentration distribution according to a typical embodiment of the present invention is shown in FIG. The impurity concentration on the collector side of 7 is set higher than that on the emitter side.

【0009】[0009]

【作用】以下本発明の作用を、77Kでのバンドポテン
シャル図(図3)を用いて説明する。本発明のベース濃
度分布はベース領域7のコレクタ側の濃度がエミッタ側
よりも高くなっているため、擬フェルミレベルの差によ
る内蔵電界は従来の傾斜濃度分布型とは逆にエミッタ側
にキャリアを引き戻す方向働いている。しかし、擬フェ
ルミレベルは温度に比例するため、この内蔵電界は77
Kでは室温の約1/4になる。一方、バンドギャップ縮
小効果によれば、ベース領域7のコレクタ側のバンドギ
ャップEg2はエミッタ側のバンドギャップEg1より
も小さくなり、キャリアをコレクタ側に加速する内蔵電
界が生ずる。バンドギャップ縮小効果は温度にほとんど
依存しないため、低温でもその内蔵電界は低下しない。
このため、77Kではバンドギャップ縮小効果による内
蔵電界がフェルミレベルによる内蔵電界を上回るように
なり、全体としてはベース走行中のキャリアをコレクタ
側に加速する方向に内蔵電界が作用する。この内蔵電界
によりベース遅延時間を短縮することができる。また、
順方向動作あるいは横方向動作であれば、エミッタ遅延
やエミッタ抵抗が小さいため、ベース遅延時間の短縮を
トランジスタ全体の遅延時間の向上に大きく反映させる
ことができる。
The operation of the present invention will be described below with reference to the band potential diagram (FIG. 3) at 77K. In the base concentration distribution of the present invention, the concentration on the collector side of the base region 7 is higher than that on the emitter side. Therefore, the built-in electric field due to the difference in pseudo-Fermi level causes carriers to flow to the emitter side, contrary to the conventional gradient concentration distribution type. It is working to pull back. However, since the pseudo Fermi level is proportional to temperature, this built-in electric field is 77
At K, it is about 1/4 of room temperature. On the other hand, according to the bandgap reduction effect, the collector-side bandgap Eg2 of the base region 7 becomes smaller than the emitter-side bandgap Eg1, and an internal electric field that accelerates carriers to the collector side is generated. Since the bandgap reduction effect hardly depends on temperature, the built-in electric field does not decrease even at low temperature.
Therefore, at 77K, the built-in electric field due to the bandgap reduction effect exceeds the built-in electric field due to the Fermi level, and as a whole, the built-in electric field acts in the direction of accelerating the carriers running in the base to the collector side. This built-in electric field can reduce the base delay time. Also,
In the forward operation or the lateral operation, the emitter delay and the emitter resistance are small, so that the reduction of the base delay time can be largely reflected in the improvement of the delay time of the entire transistor.

【0010】[0010]

【実施例】以下、本発明の実施例を図面を用いて説明す
る。実施例では順方向動作npn型バイポーラを例に説
明するが、横方向動作を行う所謂ラテラルトランジスタ
でも、pnp型でも動作原理は同じである。
Embodiments of the present invention will be described below with reference to the drawings. In the embodiment, the forward operation npn-type bipolar will be described as an example, but the operation principle is the same for a so-called lateral transistor that performs lateral operation and a pnp-type bipolar transistor.

【0011】図2は本発明の第1の実施例を示す断面図
である。本実施例の製造方法はSi基板1の表面をイオ
ン打込みにより高濃度にした後エピタキシャル成長でコ
レクタ領域2を形成し、酸化により素子分離絶縁膜3を
形成する。素子分離絶縁膜3に開口部を形成し、この開
口部の半導体表面の上にベース領域7を低温のエピタキ
シャル成長で形成してある。このエピタキシャル成長時
にドーパントのボロンの量を制御して始めは3×1019
/cm3 とし、100nmを成長させる間に不純物の量を
減らして3×1018/cm3 としている。その後、素子分
離絶縁膜3の上にボロンを高濃度に含んだポリシリコン
4を堆積してベース電極9との接続用の外部ベース電極
を形成する。その上にベース・エミッタ分離用シリコン
酸化膜5を介してポリシリコン8を堆積して燐もしくは
砒素等のイオン打ち込みをしてアニールすることにより
エミッタ領域を形成する。
FIG. 2 is a sectional view showing a first embodiment of the present invention. In the manufacturing method of this embodiment, the surface of the Si substrate 1 is made to have a high concentration by ion implantation, the collector region 2 is formed by epitaxial growth, and the element isolation insulating film 3 is formed by oxidation. An opening is formed in the element isolation insulating film 3, and a base region 7 is formed on the semiconductor surface of the opening by low temperature epitaxial growth. At the time of this epitaxial growth, the amount of boron as a dopant is controlled and the initial value is 3 × 10 19
/ Cm 3, and the amount of impurities is reduced to 3 × 10 18 / cm 3 while growing 100 nm. Then, polysilicon 4 containing boron at a high concentration is deposited on the element isolation insulating film 3 to form an external base electrode for connection with the base electrode 9. A polysilicon 8 is deposited on the base / emitter separating silicon oxide film 5 and ion-implanted with phosphorus or arsenic and annealed to form an emitter region.

【0012】図2のa−a′線上の濃度分布は図1に示
す本発明の基本的な濃度分布になっており、200K以
下の低温ではキャリアをコレクタ側に加速する内蔵電界
が生ずる。また、ベース領域の濃度は低温におけるキャ
リアフリーズアウト効果を防ぐため、モット転移濃度の
1×1018/cm3 以上に設定してある。
The concentration distribution on the line aa 'in FIG. 2 is the basic concentration distribution of the present invention shown in FIG. 1. At a low temperature of 200 K or less, a built-in electric field that accelerates carriers to the collector side is generated. The concentration of the base region is set to 1 × 10 18 / cm 3 or more of the Mott transition concentration in order to prevent the carrier freeze-out effect at low temperatures.

【0013】本実施例の効果として、本発明の逆傾斜濃
度分布型ベースと従来の傾斜濃度分布型ベースにおける
ベース遅延時間の温度依存性を図4に示す。これからわ
かるように、200K以上の温度では従来の傾斜濃度型
ベースの方が遅延時間が短いが、200K以下の温度で
次第に本発明の逆傾斜濃度型ベースの方が遅延時間が短
くなり、低温になるほどその差は大きくなる。本実施例
では77Kにおいてベース遅延時間を従来の約1/4と
することができる。
As an effect of this embodiment, FIG. 4 shows the temperature dependence of the base delay time in the reverse gradient concentration distribution type base of the present invention and the conventional gradient concentration distribution type base. As can be seen from the above, the delay time of the conventional gradient concentration type base is shorter at a temperature of 200 K or higher, but the delay time of the reverse gradient concentration type base of the present invention is gradually shorter at a temperature of 200 K or lower, and the temperature becomes lower. The difference becomes bigger. In this embodiment, at 77K, the base delay time can be reduced to about 1/4 of the conventional value.

【0014】本発明を擬似ヘテロバイポーラトランジス
タ(以下PHBT)に適応した第2の実施例の濃度分布
をを図6に示す。また、断面構造を図7に示す。PHB
Tは低温で高性能を得るためのトランジスタで、ベース
領域7の濃度をエミッタ領域6よりも高くしてバンドギ
ャップ縮小を大きくすることにより、実効的にナローギ
ャップベースのヘテロバイポーラトランジスタと同様な
動作をさせようとするものである。図7のベース形成ま
での製造方法は第1の実施例と同じであるが、絶縁膜5
を堆積した後、エミッタ用の穴をあけ、再度低温エピタ
キシャル成長により、低濃度のエミッタ領域6を形成す
る。この時ベース領域7以外ではポリシリコンとなって
堆積される。その後、高不純物濃度のエミッタポリシリ
コン電極8と金属電極9とを堆積して完成する。本実施
例では低温でベースの遅延時間が短縮されるとともに擬
似ヘテロバイポーラトランジスタの効果で電流増幅率が
増加してエミッタの遅延時間も減少するので高速なバイ
ポーラトランジスタを提供することができる。
FIG. 6 shows the concentration distribution of the second embodiment in which the present invention is applied to a pseudo hetero bipolar transistor (hereinafter referred to as PHBT). The cross-sectional structure is shown in FIG. PHB
T is a transistor for obtaining high performance at a low temperature. By increasing the concentration of the base region 7 to be higher than that of the emitter region 6 to increase the band gap reduction, an operation similar to that of a narrow-gap base hetero-bipolar transistor is achieved. It is something that tries to let you do. The manufacturing method up to the base formation of FIG. 7 is the same as that of the first embodiment, but the insulating film 5 is used.
After depositing, a hole for an emitter is opened, and a low concentration emitter region 6 is formed again by low temperature epitaxial growth. At this time, polysilicon is deposited in regions other than the base region 7 as polysilicon. Then, a high impurity concentration emitter polysilicon electrode 8 and a metal electrode 9 are deposited and completed. In this embodiment, the delay time of the base is shortened at a low temperature, the current amplification factor is increased by the effect of the pseudo-hetero bipolar transistor, and the delay time of the emitter is also reduced, so that a high speed bipolar transistor can be provided.

【0015】本発明は上記の実施例に限定されるもので
はなく、その技術思想の範囲内で種々の変形が可能であ
る。例えば、半導体基板表面にエミッタ領域とコレクタ
領域が形成され、横方向動作を行う所謂ラテラルトラン
ジスタにおいて、ベース領域のコレクタ側の不純物濃度
が前記ベース領域のエミッタ側の不純物濃度よりも高濃
度とすることにより、同様に200K以下の低温におい
て優れた特性を得ることができる。
The present invention is not limited to the above embodiments, but various modifications can be made within the scope of its technical idea. For example, in a so-called lateral transistor in which an emitter region and a collector region are formed on the surface of a semiconductor substrate and operates laterally, the impurity concentration on the collector side of the base region should be higher than the impurity concentration on the emitter side of the base region. Thus, similarly, excellent characteristics can be obtained at a low temperature of 200 K or less.

【0016】[0016]

【発明の効果】以上に説明したように、本発明の逆傾斜
型ベース濃度分布に依ればバンドギャップ縮小による内
蔵電界により、200K以下の低温においてベースの遅
延時間を大幅に低減し、高速なバイポーラトランジスタ
を提供することができる。
As explained above, according to the reverse slope type base concentration distribution of the present invention, the built-in electric field due to the bandgap reduction greatly reduces the delay time of the base at a low temperature of 200 K or less, and the high speed. A bipolar transistor can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の基本的実施例の濃度分布を示す図であ
る。
FIG. 1 is a diagram showing a concentration distribution of a basic embodiment of the present invention.

【図2】本発明の第1の実施例の断面構造を示す図であ
る。
FIG. 2 is a diagram showing a cross-sectional structure of a first embodiment of the present invention.

【図3】本発明の基本的濃度分布時のバンドのポテンシ
ャルを示す図である。
FIG. 3 is a diagram showing a band potential in the case of a basic concentration distribution of the present invention.

【図4】本発明の効果を示すベース遅延時間の温度依存
性を示す。
FIG. 4 shows the temperature dependence of the base delay time showing the effect of the present invention.

【図5】従来の濃度分布を示す図である。FIG. 5 is a diagram showing a conventional density distribution.

【図6】本発明を擬似ヘテロバイポーラトランジスタに
用いた第2の実施例を示す濃度分布図である。
FIG. 6 is a concentration distribution diagram showing a second embodiment in which the present invention is used in a pseudo hetero bipolar transistor.

【図7】本発明を擬似ヘテロバイポーラトランジスタに
用いた第2の実施例の断面構造を示す図である。
FIG. 7 is a diagram showing a cross-sectional structure of a second embodiment in which the present invention is applied to a pseudo hetero bipolar transistor.

【符号の説明】[Explanation of symbols]

1…シリコン基板、2…コレクタ層、3…素子分離用シ
コン酸化膜、4…ポリシリコン外部ベース電極、5…ベ
ースエミッタ分離用シリコン酸化膜、6…低濃度のエミ
ッタ領域、7…ベース領域、8…ポリシリコンエミッタ
領域、9…アルミニウム電極、10…ポリシリコンの低
濃度エミッタ領域。
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Collector layer, 3 ... Element isolation silicon oxide film, 4 ... Polysilicon external base electrode, 5 ... Base emitter isolation silicon oxide film, 6 ... Low concentration emitter region, 7 ... Base region, 8 ... Polysilicon emitter region, 9 ... Aluminum electrode, 10 ... Polysilicon low concentration emitter region.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】200K以下の低温で動作するとともに、
半導体基板の表面に形成されたエミッタ領域から該半導
体基板の内部に形成されたコレクタ領域に向かってエミ
ッタ電流もしくはコレクタ電流となるキャリヤが流れる
如く構成されたバイポーラトランジスタであって、ベー
ス領域のコレクタ側の不純物濃度が前記ベース領域のエ
ミッタ側の不純物濃度よりも高濃度にされたことを特徴
とするバイポーラトランジスタ。
1. Operating at a low temperature of 200 K or less,
A bipolar transistor configured such that an emitter current or a carrier serving as a collector current flows from an emitter region formed on a surface of a semiconductor substrate toward a collector region formed inside the semiconductor substrate, the collector side of a base region. The impurity concentration of is higher than the impurity concentration of the base region on the emitter side.
【請求項2】前記ベース領域のエミッタ側の不純物濃度
を1×1018/cm3 よりも高くすることを特徴とする請
求項1項のバイポーラトランジスタ。
2. The bipolar transistor according to claim 1, wherein the impurity concentration on the emitter side of the base region is higher than 1 × 10 18 / cm 3 .
【請求項3】前記ベース領域に接するエミッタ領域をベ
ース領域のエミッタ側よりも低濃度にすることを特徴と
する請求項1項のバイポーラトランジスタ。
3. The bipolar transistor according to claim 1, wherein the emitter region in contact with the base region has a lower concentration than the emitter side of the base region.
【請求項4】前記ベース領域をエピタキシャル成長で形
成することを特徴とする請求項1項のバイポーラトラン
ジスタ。
4. The bipolar transistor according to claim 1, wherein the base region is formed by epitaxial growth.
【請求項5】200K以下の低温で動作するとともに、
半導体基板表面にエミッタ領域とコレクタ領域が形成さ
れたラテラルトランジスタであって、ベース領域のコレ
クタ側の不純物濃度が前記ベース領域のエミッタ側の不
純物濃度よりも高濃度にされたことを特徴とするバイポ
ーラトランジスタ。
5. While operating at a low temperature of 200 K or less,
A lateral transistor having an emitter region and a collector region formed on a surface of a semiconductor substrate, wherein a collector side impurity concentration of a base region is higher than an emitter side impurity concentration of the base region. Transistor.
JP29124991A 1991-11-07 1991-11-07 Semiconductor device operated at low temperature Pending JPH05129315A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29124991A JPH05129315A (en) 1991-11-07 1991-11-07 Semiconductor device operated at low temperature

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29124991A JPH05129315A (en) 1991-11-07 1991-11-07 Semiconductor device operated at low temperature

Publications (1)

Publication Number Publication Date
JPH05129315A true JPH05129315A (en) 1993-05-25

Family

ID=17766419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29124991A Pending JPH05129315A (en) 1991-11-07 1991-11-07 Semiconductor device operated at low temperature

Country Status (1)

Country Link
JP (1) JPH05129315A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07193075A (en) * 1993-12-27 1995-07-28 Nec Corp Semiconductor device and its manufacture
CN112687736A (en) * 2020-12-05 2021-04-20 西安翔腾微电子科技有限公司 Base region variable doping transistor for ESD protection

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07193075A (en) * 1993-12-27 1995-07-28 Nec Corp Semiconductor device and its manufacture
US5569611A (en) * 1993-12-27 1996-10-29 Nec Corporation Method of manufacturing a bipolar transistor operating at low temperature
CN112687736A (en) * 2020-12-05 2021-04-20 西安翔腾微电子科技有限公司 Base region variable doping transistor for ESD protection
CN112687736B (en) * 2020-12-05 2024-01-19 西安翔腾微电子科技有限公司 Base region variable doping transistor for ESD protection

Similar Documents

Publication Publication Date Title
JP2582519B2 (en) Bipolar transistor and method of manufacturing the same
US5331186A (en) Heterojunction bipolar transistor with base electrode having Schottky barrier contact to the emitter
US4825265A (en) Transistor
US6423990B1 (en) Vertical heterojunction bipolar transistor
JPH05347313A (en) Manufacture of extremely thin active region of high-speed semiconductor device
US20070045664A1 (en) Semiconductor device and manufacturing method of the same
US5381027A (en) Semiconductor device having a heterojunction and a two dimensional gas as an active layer
US5258631A (en) Semiconductor device having a two-dimensional electron gas as an active layer
JPH05129315A (en) Semiconductor device operated at low temperature
JPH0684934A (en) Heterojunction bipolar transistor and its manufacture
JPH07193075A (en) Semiconductor device and its manufacture
US7214973B2 (en) Semiconductor device and method of manufacturing the same
US5096840A (en) Method of making a polysilicon emitter bipolar transistor
JPH0371774B2 (en)
JP3183468B2 (en) Heterojunction bipolar transistor and method of manufacturing the same
JPH0744185B2 (en) Semiconductor device and manufacturing method thereof
JPH05243253A (en) Semiconductor device
JPH0131314B2 (en)
JP2803147B2 (en) Bipolar transistor
JPH0344937A (en) Bipolar transistor and manufacture thereof
JP2646856B2 (en) Manufacturing method of bipolar transistor
JP2670118B2 (en) Semiconductor device and photoelectric conversion device using the same
JPH03198344A (en) Semiconductor device and photoelectric transducer using same
JPS63155664A (en) Semiconductor device and its manufacture
JP3001599B2 (en) Semiconductor device