CN112687736B

CN112687736B - Base region variable doping transistor for ESD protection

Info

Publication number: CN112687736B
Application number: CN202011393920.6A
Authority: CN
Inventors: 蒲石; 田泽; 郎静; 邵刚; 谢运祥
Original assignee: Xian Xiangteng Microelectronics Technology Co Ltd
Current assignee: Xian Xiangteng Microelectronics Technology Co Ltd
Priority date: 2020-12-05
Filing date: 2020-12-05
Publication date: 2024-01-19
Anticipated expiration: 2040-12-05
Also published as: CN112687736A

Abstract

The invention relates to a base region variable doping transistor for ESD protection. The invention comprises a P-type substrate, a first NWELL region, a first PWELL region, a first N+ contact region, a second N+ contact region and a first P+ contact region, wherein the first NWELL region is positioned above the inside of the P-type substrate, the first PWELL region is positioned above the right inside of the first NWELL region, the first N+ contact region is positioned above the left inside of the first NWELL region, the second N+ contact region is positioned above the left inside of the first PWELL region, the first P+ contact region is positioned above the right inside of the first PWELL region, and the first PWELL region is formed by a linear variable doping mode. The invention can reduce the transport coefficient of the base region through the self-built field of the base region, thereby improving the maintenance voltage of the device and avoiding the occurrence of latch-up effect.

Description

Base region variable doping transistor for ESD protection

Technical Field

The invention relates to the field of electronic science and technology, is mainly used for electrostatic discharge (Electro Static Discharge, abbreviated as ESD) protection technology, and particularly relates to a base region variable doping transistor for ESD protection.

Background

ESD, i.e., electrostatic discharge, is a phenomenon commonly found in nature. ESD exists at every corner of people's daily life. But such common electrical phenomena are fatal threats to sophisticated integrated circuits.

As integrated circuit fabrication processes have increased, their minimum linewidths have decreased to sub-micron and even nanometer levels, and as chip performance has increased, their resistance to ESD attack has also decreased substantially, thus causing more serious electrostatic damage. The contradiction between process development and the anti-ESD capability of the chip becomes a problem that must be considered by the integrated circuit designer.

Conventional devices for ESD protection include: diode, MOSFET, resistor, BJT, SCR, etc. Compared with other trigger structures, the NPN structure has bidirectional conduction characteristics and good protection performance, and is often parasitic in various trigger structures, so that the NPN structure has important significance for research and application of ESD protection devices.

The sustain voltage is an important design parameter of ESD protection devices, and must be greater than the normal operating voltage of the circuit being protected to avoid the protection device from entering the latch-up state and to have anti-latch-up capability. The conventional NPN structure for ESD protection has a fatal disadvantage in that a turn-back (snapback) phenomenon occurs after the NPN tube is turned on, and a sustain voltage after the turn-back is very low. If VDD of the protected circuit is high, the NPN will not self-turn off upon triggering, and latch-up occurs.

Disclosure of Invention

The invention aims to solve the technical problems in the background art and provides an NPN transistor with high maintenance voltage for ESD protection.

The technical scheme of the invention is as follows: the invention relates to a base region variable doping transistor structure for ESD protection, which is characterized in that: the transistor structure comprises a P-type substrate, a first NWELL region, a first PWELL region, a first N+ contact region, a second N+ contact region and a first P+ contact region, wherein the first NWELL region is positioned above the inside of the P-type substrate, the first PWELL region is positioned above the right inside of the first NWELL region, the first N+ contact region is positioned above the left inside of the first NWELL region, the second N+ contact region is positioned above the left inside of the first PWELL region, the first P+ contact region is positioned above the right inside of the first PWELL region, and the first PWELL region is formed in a linear variable doping manner.

The first PWELL region serving as the transistor base region is non-uniformly doped, the doping concentration near the second N+ contact region is low, and the doping concentration near the first N+ contact region is high.

A base region metamorphic transistor structure for ESD protection, characterized in that: the transistor structure comprises a P-type substrate, a second NWELL region, a second P+ contact region, a third N+ contact region and a third P+ contact region, wherein the second NWELL region is positioned at the upper right side of the inside of the P-type substrate, the second P+ contact region is positioned at the upper left side of the inside of the second NWELL region, the third N+ contact region is positioned at the upper right side of the inside of the second NWELL region, the third P+ contact region is positioned at the upper left side of the inside of the P-type substrate, and the second NWELL region is formed by a linear variable doping mode

The second NWELL region serving as the transistor base region is unevenly doped, and has a low doping concentration near the third p+ contact region and a high doping concentration near the second p+ contact region.

According to the base region variable doping transistor for ESD protection, the transport coefficient of the base region is reduced through base region variable doping, so that the maintenance voltage of the device is improved, and the latch-up effect is avoided.

Drawings

FIG. 1 is a block diagram of a first embodiment of the present invention;

FIG. 2 is a process diagram of a base region metamorphism doping of the present invention;

fig. 3 is a structural diagram of a second embodiment of the present invention.

The reference numerals are explained as follows:

01. a P-type substrate; 10. a first NWELL region; 13. a second NWELL region; 22. a first PWELL region; 20. a second PWELL region; 11. a first n+ contact region; 12. a second n+ contact region; 14. a third n+ contact region; 21. a first P+ contact region; 23. a second P+ contact region; 24. and a third P+ contact region.

Detailed Description

The technical scheme of the invention is further described in detail below with reference to the attached drawings and specific embodiments.

Example 1

Referring to fig. 1, the structure of the first embodiment of the present invention includes: the semiconductor device comprises a P-type substrate 01, a first NWELL region 10, a first PWELL region 22, a first N+ contact region 11, a second N+ contact region 12 and a first P+ contact region 21, wherein the first NWELL region 10 is positioned above the inside of the P-type substrate 01, the first PWELL region 22 is positioned above the inside of the first NWELL region 10 to the right, the first N+ contact region 11 is positioned above the inside of the first NWELL region 10 to the left, the second N+ contact region 12 is positioned above the inside of the first PWELL region 22 to the left, the first P+ contact region 21 is positioned above the inside of the first PWELL region 22 to the right, and the first PWELL region 10 is formed by a linear variable doping mode.

Referring to fig. 2, the first embodiment works as follows: the variable doping base region of the first PWELL region 10 is formed by linear variable doping, and has uneven doping, low doping concentration near the emitter region (the second n+ contact region 12), high doping concentration near the collector region (the first n+ contact region 11), and full ionization of impurities at room temperature, so that the multi-sub holes have approximately the same concentration distribution as the acceptor impurities. The non-uniformity in hole concentration causes holes to diffuse from high to low concentrations while ionized impurities are immobilized and thus negatively charged near the collector region and positively charged near the emitter region. The separation of space charges forms a built-in electric field. The built-in electric field inhibits the drift of minority carriers (electrons) injected into the base region to the collector region, and inhibits the transport of the minority carriers of the base region, so that the transport coefficient of the base region is reduced, and the maintenance voltage of the device is improved.

Example 2

Referring to fig. 3, the structure of the second embodiment of the present invention includes: the semiconductor device comprises a P-type substrate 01, a second NWELL region 13, a second P+ contact region 23, a third N+ contact region 14 and a third P+ contact region 24, wherein the second NWELL region 13 is positioned at the upper right inside the P-type substrate 01, the third P+ contact region 24 is positioned at the upper left inside the P-type substrate 01, the second P+ contact region 23 is positioned at the upper left inside the second NWELL region 13, the third N+ contact region 14 is positioned at the upper right inside the second NWELL region 13, and the second NWELL region 13 is formed by linear doping.

The variable doping base region of the second NWELL region 13 is formed by linear variable doping, and has a non-uniform doping, a low doping concentration near the emitter region (the third p+ contact region 24), and a high doping concentration near the collector region (the second p+ contact region 23).

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A base-doped transistor structure for ESD protection, characterized by: the transistor structure comprises a P-type substrate, a first NWELL region, a first PWELL region, a first N+ contact region, a second N+ contact region and a first P+ contact region, wherein the first NWELL region is positioned above the inside of the P-type substrate, the first PWELL region is positioned above the inside of the first NWELL region, the first N+ contact region is positioned above the left inside of the first NWELL region, the second N+ contact region is positioned above the left inside of the first PWELL region, the first P+ contact region is positioned above the right inside of the first PWELL region, the first PWELL region is formed in a linear variable doping manner, namely a variable doping base region formed by the first PWELL region is formed in a linear variable doping manner, and the doping concentration near an emitting region formed by the second N+ contact region is low, and the doping concentration near a collector region formed by the first N+ contact region is high.

2. A base-doped transistor structure for ESD protection, characterized by: the transistor structure comprises a P-type substrate, a second NWELL region, a second P+ contact region, a third N+ contact region and a third P+ contact region, wherein the second NWELL region is positioned at the right upper part in the P-type substrate, the third P+ contact region is positioned at the left upper part in the P-type substrate, the second P+ contact region is positioned at the left upper part in the second NWELL region, the third N+ contact region is positioned at the right upper part in the second NWELL region, the second NWELL region is formed in a linear variable doping manner, namely a variable doping base region formed by the second NWELL region is formed in a linear variable doping manner, and the doping concentration close to an emitter region formed by the third P+ contact region is low and the doping concentration close to a collector region formed by the second P+ contact region is high.