JPH05129200A - Manufacture of semiconductor film - Google Patents
Manufacture of semiconductor filmInfo
- Publication number
- JPH05129200A JPH05129200A JP3289886A JP28988691A JPH05129200A JP H05129200 A JPH05129200 A JP H05129200A JP 3289886 A JP3289886 A JP 3289886A JP 28988691 A JP28988691 A JP 28988691A JP H05129200 A JPH05129200 A JP H05129200A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- substrate
- wafer
- thin film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、SOI(Silicon On I
nsulator)構造における半導体薄膜,特に、単結晶半導
体薄膜の製造方法に関するものである。BACKGROUND OF THE INVENTION The present invention relates to SOI (Silicon On I)
The present invention relates to a method for manufacturing a semiconductor thin film in an nsulator structure, particularly a single crystal semiconductor thin film.
【0002】[0002]
【従来の技術】従来より、SOI構造を実現する方法が
各種提案されている。代表的な製造方法として、絶縁基
板上に非晶質半導体を堆積後、低温(600℃前後)で
長時間熱処理をして、結晶化する方法がある(固相成長
法)。2. Description of the Related Art Conventionally, various methods for realizing an SOI structure have been proposed. As a typical manufacturing method, there is a method in which an amorphous semiconductor is deposited on an insulating substrate and then heat-treated for a long time at a low temperature (around 600 ° C.) to crystallize it (solid phase growth method).
【0003】この場合、結晶成長時の核を持たない場合
には非晶質膜中にランダムに核が発生し、多結晶の膜と
なってしまうという問題がある。一方、絶縁基板を単結
晶基板と絶縁膜とで構成し、絶縁膜に設けた開口部を介
して下地の単結晶面をシードに用いて結晶成長させる方
法がある。この場合には下地基板の結晶性を継承した単
結晶膜を形成することができる。しかしながら、単結晶
シードからの成長距離には限界があるため周期的に下地
開口部を設けなければならず、有効なSOI領域が限定
されてしまう。また、下地シードを用いる必要性から基
板材料が限定されてしまうという問題点も有している。In this case, when there is no nucleus during crystal growth, there is a problem that nuclei are randomly generated in the amorphous film, resulting in a polycrystalline film. On the other hand, there is a method in which an insulating substrate is composed of a single crystal substrate and an insulating film, and crystal growth is performed using an underlying single crystal surface as a seed through an opening provided in the insulating film. In this case, a single crystal film that inherits the crystallinity of the underlying substrate can be formed. However, since the growth distance from the single crystal seed is limited, the base opening must be periodically provided, and the effective SOI region is limited. Further, there is a problem that the substrate material is limited due to the necessity of using the underlayer seed.
【0004】また、絶縁基板上に所定の方位を有する結
晶のみを残し、これをシードとして結晶成長させる方法
(特開昭63−292617号公報参照)がある。この
方法によれば、絶縁基板の基板材料に制約をうけること
もなく、また形成するSOI領域の自由度も大きくする
ことが可能である。しかしながら、シードの位置制御は
不可能であり、また個々のシードにおいて軸方向は揃っ
ても、面内において結晶軸が回転することについては制
御できないという問題がある。There is also a method (see Japanese Patent Laid-Open No. 63-292617) in which only a crystal having a predetermined orientation is left on an insulating substrate and this crystal is used as a seed. According to this method, the substrate material of the insulating substrate is not restricted, and the degree of freedom of the SOI region to be formed can be increased. However, there is a problem that it is impossible to control the position of the seed, and it is impossible to control the rotation of the crystal axis in the plane even if the individual seeds have the same axial direction.
【0005】[0005]
【発明が解決しようとする課題】本発明は上記種々の問
題を鑑みてなされたものであり、絶縁基板の基板材料に
制約をうけることなく該絶縁基板上に単結晶半導体膜を
形成することができ、しかも、SOI素子のレイアウト
の自由度を向上して集積度を向上させ、単結晶膜の結晶
方位も制御することができる半導体薄膜の製造方法を提
供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above various problems, and it is possible to form a single crystal semiconductor film on an insulating substrate without being restricted by the substrate material of the insulating substrate. It is an object of the present invention to provide a method for manufacturing a semiconductor thin film, which is capable of improving the degree of freedom of layout of an SOI device, improving the degree of integration, and controlling the crystal orientation of a single crystal film.
【0006】[0006]
【発明の概要】あらかじめ表面に非晶質半導体膜を形成
した絶縁基板と、これとは別に表面が複数の突起形状と
なるように加工された単結晶半導体基板とを用意する。
そして非晶質半導体膜表面と突起形状を有する面とが対
向するように両基板を配置して接触させた後、これを熱
処理する。SUMMARY OF THE INVENTION An insulating substrate having an amorphous semiconductor film formed on its surface in advance and a single crystal semiconductor substrate processed so that the surface has a plurality of protrusions are prepared separately from the insulating substrate.
Then, the two substrates are arranged and brought into contact with each other so that the surface of the amorphous semiconductor film and the surface having the protrusion shape face each other, and then the substrates are heat treated.
【0007】このとき突起部と接触した非晶質半導体領
域では突起部をシードとしてこの結晶性を継承しながら
順次結晶成長していく。この複数ある突起部相互の位置
関係を制御しておけば、ランダムな核発生が起こる前に
固相成長した結晶同士が結合することになる。ここで、
突起部は単結晶であるためにその結晶方位は揃ってお
り、固相成長した結晶同士の結合面において粒界を形成
することはない。At this time, in the amorphous semiconductor region which is in contact with the protrusion, the protrusion is used as a seed to successively grow crystals while inheriting the crystallinity. By controlling the positional relationship between the plurality of protrusions, the solid-phase grown crystals are bound to each other before random nucleation occurs. here,
Since the protrusions are single crystals, their crystal orientations are uniform, and no grain boundaries are formed at the bonding surfaces of solid-phase grown crystals.
【0008】次に、これら接触状態にある両基板を互い
の接触点が酸化膜により分離するまで熱酸化する。そし
て、この酸化膜を介して貼り合せられた基板をエッチャ
ント中に浸漬することより該酸化膜をエッチング除去
し、単結晶化薄膜の形成された絶縁基板とシードとして
用いた単結晶半導体基板とを分離する。Next, the two substrates in contact with each other are thermally oxidized until their contact points are separated by an oxide film. Then, the substrate bonded via the oxide film is immersed in an etchant to remove the oxide film by etching, and the insulating substrate having the single crystallized thin film formed thereon and the single crystal semiconductor substrate used as the seed are obtained. To separate.
【0009】このように、位置制御され且つ結晶軸の完
全に揃ったシードを非晶質半導体膜の表面側から供給す
るようにしているため、このシードから固相成長を施す
ことにより絶縁基板の全面に所定の方位を有する単結晶
膜を形成することができる。また、下地からシードを供
給しないため、絶縁基板の材質も特に選ばない。As described above, since the seed whose position is controlled and whose crystal axes are perfectly aligned is supplied from the surface side of the amorphous semiconductor film, solid phase growth is performed from this seed to form an insulating substrate. A single crystal film having a predetermined orientation can be formed on the entire surface. Moreover, since the seed is not supplied from the base, the material of the insulating substrate is not particularly selected.
【0010】従って本発明の製造方法によれば、絶縁基
板の基板材料に制約をうけることなく該絶縁基板上に単
結晶半導体膜を形成することができ、しかも、SOI素
子のレイアウトの自由度を向上して集積度を向上させ、
単結晶膜の結晶方位も制御することができるという優れ
た効果が奏される。Therefore, according to the manufacturing method of the present invention, the single crystal semiconductor film can be formed on the insulating substrate without being restricted by the substrate material of the insulating substrate, and the degree of freedom of the layout of the SOI element can be increased. To improve the degree of integration,
The excellent effect that the crystal orientation of the single crystal film can also be controlled is exhibited.
【0011】[0011]
【実施例】以下,本発明を具体化した実施例を図面に従
って説明する。図1,図2は本発明第1実施例を適用し
たシリコン(Si)単結晶SOI薄膜の製造工程を説明
するのに供する図である。以下、図面を参照しつつ本実
施例の製造工程を説明する。Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are views provided for explaining a manufacturing process of a silicon (Si) single crystal SOI thin film to which the first embodiment of the present invention is applied. The manufacturing process of this embodiment will be described below with reference to the drawings.
【0012】まず、図1(a)に示すように、主表面が
(100)面,オリエンテーションフラットが<110
>軸方向であるような単結晶Siウエハ4表面にSiO
2 膜などのマスク材料6を形成し、該マスク材料6を公
知のフォトリソグラフィによりパターニングし、<11
0>方向に対して平行および垂直な辺を有する正方形状
のマスクパターンを形成する。そして、KOH水溶液等
によってSiウエハ4表面をエッチングする。First, as shown in FIG. 1A, the main surface is the (100) plane and the orientation flat is <110.
> SiO on the surface of the single crystal Si wafer 4 in the axial direction
A mask material 6 such as two films is formed, and the mask material 6 is patterned by known photolithography, <11
A square mask pattern having sides parallel and perpendicular to the 0> direction is formed. Then, the surface of the Si wafer 4 is etched with a KOH aqueous solution or the like.
【0013】この結果、図1(b)に示すように、結晶
面のエッチング速度の違いによって(111)面のみで
構成されるピラミッド状の突起4aをウエハ表面に形成
することができる。As a result, as shown in FIG. 1B, a pyramid-shaped protrusion 4a composed of only the (111) plane can be formed on the wafer surface due to the difference in the etching rate of the crystal planes.
【0014】また、別途用意したSiウエハ1の主表面
側全面に、SiO2等の絶縁膜2および非晶質Si薄膜
3’を順次堆積する。そして、このSiウエハ1とSi
ウエハ4とを各々HF等で表面の酸化膜を除去した後、
図2(a)に示すように、その非晶質Si薄膜3’を形
成した主表面側と突起4aを形成した主表面側とにおい
て対向させて突起4aにて接触させ、その後、熱処理を
行い、非晶質Si薄膜3’を結晶化させる。このとき突
起4aと接触した非晶質Si薄膜3’は、突起4aをシ
ードとしてこの結晶性を継承しながら順次結晶成長し、
単結晶Si薄膜3を形成する。Further, separately on the entire main surface of a prepared Si wafer 1, sequentially depositing an insulating film 2 and the amorphous Si thin film 3 of SiO 2 or the like '. And this Si wafer 1 and Si
After removing the oxide film on the surfaces of the wafer 4 and HF respectively,
As shown in FIG. 2A, the main surface side on which the amorphous Si thin film 3 ′ is formed and the main surface side on which the projection 4 a is formed are opposed to each other and brought into contact with each other by the projection 4 a, and then heat treatment is performed. , The amorphous Si thin film 3 ′ is crystallized. At this time, the amorphous Si thin film 3 ′ that is in contact with the protrusions 4a successively grows with the protrusions 4a as seeds while inheriting this crystallinity.
A single crystal Si thin film 3 is formed.
【0015】ここで、ピラミッド状の突起4aの相互の
位置関係を制御しておけば、ランダムな核発生が起こる
前に固相成長した結晶同士が結合することになる。この
突起4aの間隔は熱処理(600℃前後)における結晶
の成長距離によって設定できるものであるが、完全な単
結晶とするには5μm以下とするのが望ましい。また、
突起4aは単結晶であるためにその結晶方位は揃ってお
り、固相成長した結晶同士の結合面において粒界を形成
することはない。なお、熱処理時には非晶質Si薄膜
3’と突起4aとの接触を確実にするため、荷重をかけ
るようにするとよい。Here, if the mutual positional relationship of the pyramid-shaped projections 4a is controlled, the solid-phase grown crystals are bonded to each other before random nucleation occurs. The interval between the protrusions 4a can be set by the crystal growth distance during heat treatment (around 600 ° C.), but is preferably 5 μm or less in order to form a complete single crystal. Also,
Since the projections 4a are single crystals, their crystal orientations are aligned, and grain boundaries are not formed at the bonding surfaces of the solid-phase grown crystals. A load may be applied during the heat treatment in order to ensure contact between the amorphous Si thin film 3'and the protrusions 4a.
【0016】次に、図2(b)に示すように、この2枚
のウエハ1,4を貼り合わせたまま酸化する。これによ
り突起4aの先端を介して接触する2枚のウエハ1,4
は、接触部に酸化膜5が介在することになる。Next, as shown in FIG. 2B, the two wafers 1 and 4 are oxidized while being bonded to each other. As a result, the two wafers 1, 4 contacting each other through the tips of the protrusions 4a
Means that the oxide film 5 is present at the contact portion.
【0017】次に、この貼り合せウエハをHF水溶液に
浸漬することで、上述の図2(b)の工程で形成された
酸化膜5はエッチング除去され、図2(c)に示すよう
に、2枚のウエハ1,4が分離される。Next, by dipping this bonded wafer in an HF aqueous solution, the oxide film 5 formed in the above step of FIG. 2B is removed by etching, and as shown in FIG. 2C. The two wafers 1 and 4 are separated.
【0018】以上のように、本実施例の製造方法によれ
ば、非晶質Si薄膜3’の表面側から、結晶軸の揃った
単結晶Siウエハ4の突起4aによるシードを供給し、
このシードから固相成長するようにしているため、単結
晶Siウエハ4できまる所定の方位を有する単結晶Si
薄膜3を得ることができる。As described above, according to the manufacturing method of this embodiment, the seeds by the projections 4a of the single crystal Si wafer 4 having the uniform crystal axes are supplied from the surface side of the amorphous Si thin film 3 '.
Since the solid phase growth is performed from this seed, the single crystal Si having a predetermined orientation that can be formed by the single crystal Si wafer 4
The thin film 3 can be obtained.
【0019】また、従来のように下地からシードを供給
するものではないため、絶縁基板の材質も特に選ばず、
例えばガラス基板でもよい。またシード形成時に従来構
成していた開口部に起因して発生する凹凸も低減でき、
平坦化も期待できる。Further, since the seed is not supplied from the underlayer as in the conventional case, the material of the insulating substrate is not particularly selected,
For example, a glass substrate may be used. In addition, it is possible to reduce the unevenness caused by the opening that was conventionally configured during seed formation,
Flattening can also be expected.
【0020】なお、上記実施例では突起をピラミッド状
としてその先端を点状としたが、これを線状としても非
晶質Si薄膜3’との接触面積が小さければ分離酸化の
際に形成する酸化膜厚は薄くでき、接合部と非接合部で
のSi薄膜の差を小さくできる。In the above-mentioned embodiment, the projection is formed in a pyramid shape and the tip is formed in a dot shape, but even if it is formed in a linear shape, it is formed during the separation oxidation if the contact area with the amorphous Si thin film 3'is small. The oxide film thickness can be made thin, and the difference between the Si thin film at the bonded portion and the non-bonded portion can be reduced.
【0021】次に、図3,図4を用いて本発明の第2実
施例を説明する。まず、シードを供給する単結晶Siウ
エハ4の主表面にレジストを塗布し、電子ビーム露光に
より微細ドットパターンを形成する。その後、異方性ド
ライエッチングによりSiをエッチングして、図3に示
すように、突起4bを形成する。その後、図4(a)〜
(c)に示すように、上述の図2(a)〜(c)に示す
工程と同様にして、2枚のウエハ1,4を貼り合わせ、
熱処理して分離酸化を行い、HF水溶液によるウエハ分
離を行うことで、単結晶SOI薄膜3を形成した絶縁基
板を得ることができる。Next, a second embodiment of the present invention will be described with reference to FIGS. First, a resist is applied to the main surface of the single crystal Si wafer 4 which supplies a seed, and a fine dot pattern is formed by electron beam exposure. After that, Si is etched by anisotropic dry etching to form the protrusion 4b as shown in FIG. After that, FIG.
As shown in FIG. 2C, the two wafers 1 and 4 are bonded together in the same manner as the steps shown in FIGS.
An insulating substrate having the single crystal SOI thin film 3 formed thereon can be obtained by performing heat treatment, separation and oxidation, and wafer separation using an HF aqueous solution.
【0022】なお、上記第1実施例のようにアルカリ溶
液による異方性エッチングを用いて突起を形成する場合
には、マスクパターンサイズにバラツキがあるとピラミ
ッド状突起の高さがバラツクことがある。その場合、非
晶質Si薄膜との接触を行った時に部分的に接触しない
箇所ができることがある。しかしながら、本実施例では
ウエハの主表面を維持したまま突起4bを形成できるた
め、複数ある突起の高さを均一に揃えることができる。
ここで、本実施例では接触領域が面となるためこの面積
を極力低減する必要があるが、電子ビーム描画を用いる
ようにすれば線幅として数100A程度のパターンを加
工でき、後工程の分離酸化において酸化膜5により両基
板を良好に分離することができ、問題は起こらない。な
お、電子ビームのかわりにFIB装置をもちいて直接S
iウエハ4を加工するようにしてもよい。また、突起4
bの高さは酸化工程で酸素の供給の妨げにならないよ
う、数1000Å程度以上とすることが望ましい。When the protrusions are formed by using anisotropic etching with an alkaline solution as in the first embodiment, the height of the pyramidal protrusions may vary if the mask pattern size varies. .. In that case, when the amorphous Si thin film is contacted, there may be a part that does not partially contact. However, in this embodiment, since the protrusions 4b can be formed while maintaining the main surface of the wafer, the heights of the plurality of protrusions can be made uniform.
Here, in this embodiment, since the contact region is a surface, it is necessary to reduce this area as much as possible. However, if electron beam drawing is used, a pattern with a line width of several hundreds of A can be processed, and a separation in a post process is performed. In the oxidation, the oxide film 5 allows the two substrates to be well separated, and no problem occurs. It should be noted that the FIB device is used instead of the electron beam to directly perform S
The i-wafer 4 may be processed. Also, the protrusion 4
The height of b is preferably about several thousand Å or more so as not to hinder the supply of oxygen in the oxidation step.
【0023】図5および図6は本発明の第3実施例によ
る,シード用単結晶Siウエハ4の加工方法を説明する
図である。本実施例は単結晶Siの突起を陽極化成処理
によって形成するものである。図5に示すように、単結
晶Si基板4を用意し、単結晶Si基板4の裏面側にア
ルミ電極板7を配置し、単結晶Si基板4の表面が露出
するようにアルミ電極板7を保護用ワックス8で覆う。
そして、この単結晶Si基板4を濃度約25%のHF水
溶液12に浸し、白金電極9を対向配置する。そして、
単結晶Si基板4を陽極とし、白金電極9を陰極として
定電流源10から電流を流して、単結晶Si基板4の表
面を陽極化成処理する。FIGS. 5 and 6 are views for explaining a method for processing the seed single crystal Si wafer 4 according to the third embodiment of the present invention. In this embodiment, the protrusions of single crystal Si are formed by anodizing treatment. As shown in FIG. 5, a single crystal Si substrate 4 is prepared, an aluminum electrode plate 7 is arranged on the back surface side of the single crystal Si substrate 4, and the aluminum electrode plate 7 is exposed so that the surface of the single crystal Si substrate 4 is exposed. Cover with protective wax 8.
Then, the single crystal Si substrate 4 is dipped in an HF aqueous solution 12 having a concentration of about 25%, and the platinum electrodes 9 are arranged facing each other. And
Using the single crystal Si substrate 4 as an anode and the platinum electrode 9 as a cathode, a current is passed from a constant current source 10 to anodize the surface of the single crystal Si substrate 4.
【0024】これは、HF水溶液12中においてO2-と
OH- が単結晶Si基板4に引きつけられ、単結晶Si
基板4の表面においてO2-とOH- の電子が奪われ活性
な酸素が発生する。そして、この活性な酸素によりSi
O2 が単結晶Si基板4の表面に形成され、このSiO
2 がHF水溶液12にて溶解される。このようなメカニ
ズムのもとに陽極化成処理が進み、図6に示すように単
結晶Si基板4の表面において多孔質Si層4cが形成
される。この多孔質Si層4cは径が数nm程度の量子
細線よりなっている。なお、図5中、11は電流計であ
る。This is because O 2− and OH − are attracted to the single crystal Si substrate 4 in the HF aqueous solution 12,
On the surface of the substrate 4, electrons of O 2− and OH − are deprived and active oxygen is generated. Then, due to this active oxygen, Si
O 2 is formed on the surface of the single crystal Si substrate 4, and the SiO 2
2 is dissolved in the HF aqueous solution 12. Anodization proceeds under such a mechanism, and a porous Si layer 4c is formed on the surface of the single crystal Si substrate 4 as shown in FIG. The porous Si layer 4c is made of quantum wires having a diameter of about several nm. In FIG. 5, 11 is an ammeter.
【0025】本第3実施例によれば高価なEB露光装置
やFIB装置を用いなくても簡単に安価に微細突起を形
成できる。According to the third embodiment, the fine projections can be formed easily and inexpensively without using an expensive EB exposure device or FIB device.
【図1】図(a),(b)は本発明第1実施例に使用す
る単結晶Si基板4の製造方法を説明するために供する
図である。1A and 1B are views provided to explain a method for manufacturing a single crystal Si substrate 4 used in a first embodiment of the present invention.
【図2】図(a)〜(c)は本発明第1実施例の製造工
程順における断面図である。2A to 2C are cross-sectional views in the manufacturing process order of the first embodiment of the present invention.
【図3】本発明第2実施例に使用する単結晶Si基板4
の製造方法を説明するために供する図である。FIG. 3 is a single crystal Si substrate 4 used in the second embodiment of the present invention.
FIG. 7 is a diagram which is provided for explaining the manufacturing method of FIG.
【図4】図(a)〜(c)は本発明第2実施例の製造工
程順における断面図である。4A to 4C are cross-sectional views in the manufacturing process order of the second embodiment of the present invention.
【図5】本発明第3実施例に使用する単結晶Si基板4
の製造方法を説明するために供する図である。FIG. 5 is a single crystal Si substrate 4 used in the third embodiment of the present invention.
FIG. 7 is a diagram which is provided for explaining the manufacturing method of FIG.
【図6】本発明第3実施例に使用する単結晶Si基板4
の製造方法を説明するために供する図である。FIG. 6 is a single crystal Si substrate 4 used in the third embodiment of the present invention.
FIG. 7 is a diagram which is provided for explaining the manufacturing method of FIG.
1 Si基板 2 絶縁膜 3’ 非晶質Si薄膜 3 単結晶Si薄膜 4 単結晶Si基板 4a,4b,4c 突起 5 酸化膜 DESCRIPTION OF SYMBOLS 1 Si substrate 2 Insulating film 3'Amorphous Si thin film 3 Single crystal Si thin film 4 Single crystal Si substrate 4a, 4b, 4c Protrusion 5 Oxide film
Claims (1)
成された単結晶半導体基板とを用意し、前記絶縁基板上
に非晶質半導体膜を形成する工程と、 前記非晶質半導体膜表面に対向して前記単結晶半導体基
板を前記突起の形成された表面側において配置し、両者
を接触させる工程と、 前記非晶質半導体膜および前記単結晶半導体基板を熱処
理して単結晶半導体基板の突起先端部をシードとして前
記非晶質半導体膜を結晶化させる工程と、 該結晶化半導体膜と前記単結晶半導体基板の接する領域
が酸化物により完全分離するまで酸化する工程と、 該酸化物をエッチング除去することにより、前記結晶化
半導体膜の形成された絶縁基板と前記単結晶半導体基板
とを分離する工程とを含むことを特徴とする半導体膜の
製造方法。1. A step of preparing an insulating substrate and a single crystal semiconductor substrate having a plurality of protrusions formed on the surface thereof, and forming an amorphous semiconductor film on the insulating substrate; and the amorphous semiconductor film. A step of disposing the single crystal semiconductor substrate facing the surface on the side of the surface on which the protrusion is formed and bringing them into contact with each other; and heat treating the amorphous semiconductor film and the single crystal semiconductor substrate to form a single crystal semiconductor substrate. Crystallizing the amorphous semiconductor film by using the protrusion tips as seeds, and oxidizing until the region where the crystallized semiconductor film and the single crystal semiconductor substrate are in contact with each other is completely separated by oxide. And a step of separating the insulating substrate on which the crystallized semiconductor film is formed and the single crystal semiconductor substrate by etching away.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3289886A JPH05129200A (en) | 1991-11-06 | 1991-11-06 | Manufacture of semiconductor film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3289886A JPH05129200A (en) | 1991-11-06 | 1991-11-06 | Manufacture of semiconductor film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05129200A true JPH05129200A (en) | 1993-05-25 |
Family
ID=17749047
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3289886A Withdrawn JPH05129200A (en) | 1991-11-06 | 1991-11-06 | Manufacture of semiconductor film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05129200A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004260145A (en) * | 2003-02-03 | 2004-09-16 | Mitsubishi Electric Corp | Method for manufacturing crystalline film |
JP2006216658A (en) * | 2005-02-02 | 2006-08-17 | Seiko Epson Corp | Method of manufacturing thin film semiconductor device |
JP2009224727A (en) * | 2008-03-18 | 2009-10-01 | Semiconductor Technology Academic Research Center | Semiconductor device and its manufacturing method |
JP2012507172A (en) * | 2008-10-31 | 2012-03-22 | コミサリヤ・ア・レネルジ・アトミク・エ・オ・エネルジ・アルテルナテイブ | Method for forming a single crystal film in the field of microelectronics |
JP2012507171A (en) * | 2008-10-31 | 2012-03-22 | コミサリヤ・ア・レネルジ・アトミク・エ・オ・エネルジ・アルテルナテイブ | Method of manufacturing a hybrid substrate with a buried electrically insulating continuous layer |
-
1991
- 1991-11-06 JP JP3289886A patent/JPH05129200A/en not_active Withdrawn
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004260145A (en) * | 2003-02-03 | 2004-09-16 | Mitsubishi Electric Corp | Method for manufacturing crystalline film |
JP2006216658A (en) * | 2005-02-02 | 2006-08-17 | Seiko Epson Corp | Method of manufacturing thin film semiconductor device |
JP4734944B2 (en) * | 2005-02-02 | 2011-07-27 | セイコーエプソン株式会社 | Method for manufacturing thin film semiconductor device |
JP2009224727A (en) * | 2008-03-18 | 2009-10-01 | Semiconductor Technology Academic Research Center | Semiconductor device and its manufacturing method |
US8963124B2 (en) | 2008-03-18 | 2015-02-24 | Semiconductor Technology Academic Research Center | Semiconductor device including a plurality of different functional elements and method of manufacturing the same |
JP2012507172A (en) * | 2008-10-31 | 2012-03-22 | コミサリヤ・ア・レネルジ・アトミク・エ・オ・エネルジ・アルテルナテイブ | Method for forming a single crystal film in the field of microelectronics |
JP2012507171A (en) * | 2008-10-31 | 2012-03-22 | コミサリヤ・ア・レネルジ・アトミク・エ・オ・エネルジ・アルテルナテイブ | Method of manufacturing a hybrid substrate with a buried electrically insulating continuous layer |
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Legal Events
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A300 | Withdrawal of application because of no request for examination |
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