JPH05129149A - Film capacitor - Google Patents

Film capacitor

Info

Publication number
JPH05129149A
JPH05129149A JP28589591A JP28589591A JPH05129149A JP H05129149 A JPH05129149 A JP H05129149A JP 28589591 A JP28589591 A JP 28589591A JP 28589591 A JP28589591 A JP 28589591A JP H05129149 A JPH05129149 A JP H05129149A
Authority
JP
Japan
Prior art keywords
thin film
glaze
layer
thickness
glaze layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP28589591A
Other languages
Japanese (ja)
Other versions
JP3042090B2 (en
Inventor
Junji Kojima
淳司 小島
Mikio Haga
幹夫 羽賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3285895A priority Critical patent/JP3042090B2/en
Publication of JPH05129149A publication Critical patent/JPH05129149A/en
Application granted granted Critical
Publication of JP3042090B2 publication Critical patent/JP3042090B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To see that the film such as the dielectric, the inner electrode, etc., made on a glaze and the resin layer on an inorganic insulating film can not be made with high accuracy with specified patterns shapes by solving the theme such as that the pattern shape of a film dielectric, an inner electrode, etc., can not be made with high accuracy. CONSTITUTION:The thickness of the glaze layer 2 on a ceramic board 1 is 10-25mum and the average roughness Ra of time center line at the surface of the glaze layer is 0.01-0.2mum. Hereby, the specified pattern shape of the film or the protective resin made on the glaze layer can be made with high accuracy.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子機器等における電
子回路に使用される薄膜コンデンサに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film capacitor used in electronic circuits in electronic equipment and the like.

【0002】[0002]

【従来の技術】近年、電子機器の小型・軽量化が進む
中、面実装技術を用いた電子部品の高密度実装化に伴う
電子部品に対するチップ化、小型化の要望が益々強くな
ってきている。その中で、コンデンサにおいても小型化
への種々の取り組みがなされ、その取り組みの一つに誘
電体の薄膜化を図った薄膜コンデンサがある。
2. Description of the Related Art In recent years, as electronic devices have become smaller and lighter, there has been an increasing demand for chipping and miniaturization of electronic components accompanying the high-density mounting of electronic components using surface mounting technology. .. Among them, various efforts have been made to reduce the size of capacitors, and one of the efforts is a thin film capacitor in which the dielectric film is made thin.

【0003】以下、従来の薄膜コンデンサについて説明
する。図1は従来および本発明の薄膜コンデンサの基本
的構成を示す断面図であり、セラミック基板1上に図2
に示すようなパタ−ンでグレ−ズ層2を形成し、薄膜誘
電体3と一層ごとにグレ−ズ層2を越えてセラミック基
板1の両端方向に位置ずれさせた内部電極4a、4bと
を交互に積層し、さらにセラミック基板1の両端の内部
電極4a、4bの部分を除いて無機絶縁膜5を形成し、
その無機絶縁膜5の上に樹脂層6を形成し、これを個片
に分割して外部電極7を形成して薄膜コンデンサとして
いた。
A conventional thin film capacitor will be described below. FIG. 1 is a sectional view showing the basic structure of a conventional thin film capacitor and a thin film capacitor of the present invention.
The glaze layer 2 is formed by a pattern as shown in FIG. 1, and the thin-film dielectric 3 and the internal electrodes 4a and 4b which are displaced layer by layer across the glaze layer 2 toward both ends of the ceramic substrate 1. Are alternately laminated, and the inorganic insulating film 5 is formed except for the internal electrodes 4a and 4b at both ends of the ceramic substrate 1.
A resin layer 6 was formed on the inorganic insulating film 5, and the external electrode 7 was formed by dividing this into individual pieces to form a thin film capacitor.

【0004】このとき、外部電極7の付着強度を確保す
るためセラミック基板1の両端は平均中心線粗さ(以
下、Raという)が0.1μm以上である非グレ−ズ部
8とし、薄膜誘電体3の特性が十分発揮できるグレ−ズ
層2の表面としてRaを0.01μm以下とする必要が
あり、これを達成するためにはグレ−ズ層2の膜厚を図
3に示すように厚く、すなわち約50μmとする必要が
あった。
At this time, in order to secure the adhesion strength of the external electrodes 7, both ends of the ceramic substrate 1 are made into non-glaze parts 8 having an average center line roughness (hereinafter referred to as Ra) of 0.1 μm or more, and the thin film dielectric is used. Ra must be 0.01 μm or less for the surface of the glaze layer 2 that can sufficiently exhibit the characteristics of the body 3, and in order to achieve this, the thickness of the glaze layer 2 is set as shown in FIG. It had to be thick, that is, about 50 μm.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記従
来の構成の薄膜コンデンサでは、グレ−ズ層2の膜厚が
厚いため、薄膜誘電体3、内部電極4a、4b等のパタ
−ン形成の際、所定のパタ−ン形状を高精度に確保する
ことが不可能であるという問題を有していた。
However, in the above-mentioned conventional thin film capacitor, since the glaze layer 2 has a large film thickness, when the pattern of the thin film dielectric 3, the internal electrodes 4a, 4b, etc. is formed. However, there is a problem that it is impossible to secure a predetermined pattern shape with high accuracy.

【0006】これは図3に従来のグレ−ズ層2の断面形
状を示すようにグレ−ズ層2の膜厚が厚いとその形状が
平坦領域が非常に少ない山状となるため、板状のマスク
(図示せず)を用いたパタ−ン形成の際、マスクとグレ
−ズ面の密着が不完全となるためである。
As shown in the cross-sectional shape of the conventional glaze layer 2 in FIG. 3, when the glaze layer 2 has a large film thickness, the shape thereof becomes a mountain shape having very few flat regions, and therefore, a plate shape. This is because when the pattern is formed using the mask (not shown), the adhesion between the mask and the glaze surface becomes incomplete.

【0007】また、無機絶縁膜5上の樹脂層6の形成に
ついても、スクリ−ン印刷あるいはフォトリソグラフ法
等の手法でパタ−ン状に形成する際、上記と同様にスク
リ−ンマスクとグレ−ズ面の密着の不完全性、あるいは
フォトレジストの解像度の劣化により樹脂形状の精度が
劣化し、後の個片に分割する際のスクライブラインの線
幅を確保することが困難であった。
Also, regarding the formation of the resin layer 6 on the inorganic insulating film 5, when a pattern is formed by a method such as screen printing or photolithography, a screen mask and a grain are formed in the same manner as described above. The accuracy of the resin shape is deteriorated due to the incomplete adhesion of the scratch surface or the deterioration of the resolution of the photoresist, and it is difficult to secure the line width of the scribe line when dividing into individual pieces later.

【0008】本発明は上記課題を解決するもので、グレ
−ズ層の表面に形成する誘電体、内部電極等の薄膜およ
び無機絶縁膜上の樹脂層の所定のパタ−ン形状を高精度
に形成できる薄膜コンデンサを提供することを目的とし
ている。
The present invention is intended to solve the above-mentioned problems. The dielectric layer formed on the surface of the glaze layer, thin films such as internal electrodes, and the predetermined pattern shape of the resin layer on the inorganic insulating film can be precisely formed. An object is to provide a thin film capacitor that can be formed.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に本発明の薄膜コンデンサは、グレ−ズ層の膜厚を10
〜25μmとし、その時のRaを0.01〜0.2μm
とするものである。
In order to achieve the above object, the thin film capacitor of the present invention has a glaze layer having a thickness of 10
To 25 μm, and Ra at that time is 0.01 to 0.2 μm
It is what

【0010】[0010]

【作用】したがって本発明によれば、グレ−ズ層の膜厚
を10〜25μmとすることにより、板状のマスクまた
はスクリ−ンマスクとグレ−ズ面との密着性が向上し、
またフォトレジストの解像度の劣化が少なくなるため、
誘電体、内部電極等の薄膜および無機絶縁膜上の樹脂層
の所定のパタ−ン形状を高精度に確保することが可能と
なる。その時のグレ−ズ表面のRaは0.01〜0.2
μmであれば薄膜誘電体の特性は十分満足できる。
Therefore, according to the present invention, the film thickness of the glaze layer is set to 10 to 25 μm to improve the adhesion between the plate-shaped mask or screen mask and the glaze surface.
Also, since the deterioration of the resolution of the photoresist is reduced,
It is possible to ensure a predetermined pattern shape of the resin layer on the thin film such as the dielectric and the internal electrode and the inorganic insulating film with high accuracy. Ra of the glaze surface at that time is 0.01 to 0.2.
If it is μm, the characteristics of the thin film dielectric can be sufficiently satisfied.

【0011】[0011]

【実施例】以下、本発明の一実施例について図面を参照
にして説明する。図1は本発明による薄膜コンデンサの
構成を示すものであり、従来例と同一部分には同一番号
を付して説明を省略し、相違する点について説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the structure of a thin film capacitor according to the present invention. The same parts as those of the conventional example are designated by the same reference numerals, and the description thereof will be omitted. Differences will be described.

【0012】本発明における薄膜コンデンサは、セラミ
ック基板1の上にグレ−ズ層2を設け、そのグレ−ズ層
2と非グレ−ズ部8に跨るように内部電極4aを形成
し、つぎに内部電極4aとグレ−ズ層2に跨るように有
機物質よりなる薄膜誘電体3を形成した後、薄膜誘電体
3の上に内部電極4aとは極性の異なる内部電極4bを
形成し、さらにその内部電極4bの上に薄膜誘電体3を
形成する。このような積層を繰返し、所定の数の積層を
終え、個々の薄膜コンデンサを形成させ、無機絶縁膜5
を封止膜として薄膜コンデンサの全面に形成し、さらに
その無機絶縁膜5の上から非グレ−ズ部8を残して樹脂
層6を形成し、つぎに樹脂層6を形成していない部分の
無機絶縁膜5をエッチング処理によって除去し、非グレ
−ズ部8を露出させる。その後個々の薄膜コンデンサを
炭酸ガスレ−ザ−によるスクライブラインを入れた後分
割して個片とし、内部電極積層部の端部が形成されてい
る非グレ−ズ部8を含むセラミック基板1の両端部に外
部電極7を形成して図1に示す薄膜コンデンサが完成す
る。
In the thin film capacitor of the present invention, the glaze layer 2 is provided on the ceramic substrate 1, and the internal electrode 4a is formed so as to extend over the glaze layer 2 and the non-glaze portion 8. Then, After forming the thin film dielectric 3 made of an organic material so as to straddle the internal electrode 4a and the glaze layer 2, an internal electrode 4b having a polarity different from that of the internal electrode 4a is formed on the thin film dielectric 3 and further, The thin film dielectric 3 is formed on the internal electrode 4b. By repeating such lamination, a predetermined number of laminations are completed to form individual thin film capacitors, and the inorganic insulating film 5 is formed.
Is used as a sealing film over the entire surface of the thin film capacitor, and the resin layer 6 is formed on the inorganic insulating film 5 with the non-glaze portion 8 left, and then the resin layer 6 is not formed. The inorganic insulating film 5 is removed by etching to expose the non-glaze part 8. Thereafter, each thin film capacitor is divided into individual pieces by inserting a scribe line by a carbon dioxide gas laser into individual pieces, and both ends of the ceramic substrate 1 including the non-glaze portion 8 in which the end portion of the internal electrode laminated portion is formed. The external electrode 7 is formed on the portion to complete the thin film capacitor shown in FIG.

【0013】以下、2種類の実施例と3種類の比較例を
図面を参照しながらさらに詳しく説明する。
Two types of embodiments and three types of comparative examples will be described in more detail below with reference to the drawings.

【0014】(実施例1)セラミック基板1上に図1に
示す構成により薄膜コンデンサを形成した。グレ−ズ層
2の膜厚は25μm、グレ−ズ表面のRaは0.05μ
mとし、内部電極4a,4bはアルミニウムを500Å
の厚さでEB蒸着(エレクトロンビ−ム蒸発源による蒸
着)し、有機物質よりなる薄膜誘電体3としてポリユリ
アを2000Åの厚さで蒸着重合法によりそれぞれメタ
ルマスクを用いてパタ−ン形成した。無機絶縁膜5はプ
ラズマCVD法によるシリコン酸化窒化膜(SiON
膜)を2μmの厚さで形成し、樹脂層6は東京応化工業
(株)製ポジ型レジストOFPR−2を用いてフォトリ
ソグラフ法で形成した。
Example 1 A thin film capacitor was formed on a ceramic substrate 1 with the structure shown in FIG. The thickness of the glaze layer 2 is 25 μm, and Ra on the glaze surface is 0.05 μm.
m, and the internal electrodes 4a and 4b are made of aluminum with 500Å
EB vapor deposition (electron beam evaporation source vapor deposition) with a thickness of 2000 .ANG., And polyurea as a thin film dielectric 3 made of an organic material was patterned at a thickness of 2000 .ANG. By a vapor deposition polymerization method using a metal mask. The inorganic insulating film 5 is a silicon oxynitride film (SiON) formed by a plasma CVD method.
The resin layer 6 was formed by a photolithography method using a positive resist OFPR-2 manufactured by Tokyo Ohka Kogyo Co., Ltd.

【0015】つぎにフッ酸(HF)とフッ化アンモニウ
ム(NH4 F)を1:5の比率で混合したエッチング液
に浸漬し樹脂層6を形成していない部分のSiON膜を
除去し、その後炭酸ガスレ−ザ−によるスクライブライ
ンを入れ基板分割を行い外部電極7を形成して実施例1
の薄膜コンデンサを完成した。
Then, the SiON film in the portion where the resin layer 6 is not formed is removed by immersing it in an etching solution in which hydrofluoric acid (HF) and ammonium fluoride (NH 4 F) are mixed in a ratio of 1: 5. EXAMPLE 1 A scribe line by a carbon dioxide gas laser was inserted to divide the substrate to form external electrodes 7.
The thin film capacitor of was completed.

【0016】(実施例2)セラミック基板1上に図1に
示す構成により薄膜コンデンサを形成した。グレ−ズ層
2の膜厚は10μm、グレ−ズ表面のRaは0.2μm
とし、内部電極4a,4bはアルミニウムを500Åの
厚さでEB蒸着し、薄膜誘電体3としてポリユリアを2
000Åの厚さで蒸着重合法によりそれぞれメタルマス
クを用いてパタ−ン形成した。無機絶縁膜5はプラズマ
CVD法によるSiON膜を2μmの厚さで形成し、樹
脂層6は(株)セイコ−アドバンス製スクリ−ン印刷用
樹脂1300番120ホワイトをスクリ−ン印刷法で形
成した。
Example 2 A thin film capacitor was formed on a ceramic substrate 1 with the structure shown in FIG. The thickness of the glaze layer 2 is 10 μm, and Ra on the glaze surface is 0.2 μm.
The inner electrodes 4a and 4b are formed by EB vapor-depositing aluminum with a thickness of 500Å, and polyurea is used as the thin-film dielectric 3.
Patterns were formed with a thickness of 000Å by vapor deposition polymerization using metal masks. As the inorganic insulating film 5, a SiON film having a thickness of 2 μm is formed by a plasma CVD method, and as the resin layer 6, a screen printing resin 1300 # 120 white manufactured by Seiko Advance Co., Ltd. is formed by a screen printing method. ..

【0017】つぎにフッ酸(HF)とフッ化アンモニウ
ム(NH4 F)を1:5の比率で混合したエッチング液
に浸漬し樹脂層6を形成していない部分のSiON膜を
除去し、その後炭酸ガスレ−ザ−によるスクライブライ
ンを入れ基板分割を行い外部電極7を形成して実施例2
の薄膜コンデンサを完成した。
Then, the SiON film at the portion where the resin layer 6 is not formed is removed by immersing it in an etching solution in which hydrofluoric acid (HF) and ammonium fluoride (NH 4 F) are mixed at a ratio of 1: 5. EXAMPLE 2 A scribe line using a carbon dioxide gas laser was inserted to divide the substrate to form external electrodes 7.
The thin film capacitor of was completed.

【0018】(比較例1)セラミック基板1上に図3に
示す従来の形状のグレ−ズ層2を有する薄膜コンデンサ
を形成した。グレ−ズ層2の膜厚は50μm、グレ−ズ
表面のRaは0.005μmとし、内部電極4a,4b
はアルミニウムを500Åの厚さでEB蒸着し、薄膜誘
電体3としてはポリユリアを2000Åの厚さで蒸着重
合法によりそれぞれメタルマスクを用いてパタ−ン形成
した。無機絶縁膜5はプラズマCVD法によるSiON
膜を2μmの厚さで形成し、樹脂層6は東京応化工業
(株)製ポジ型レジストOFPR−2を用いてフォトリ
ソグラフ法で形成した。
Comparative Example 1 A thin film capacitor having a conventional glaze layer 2 shown in FIG. 3 was formed on a ceramic substrate 1. The thickness of the glaze layer 2 is 50 μm, Ra on the glaze surface is 0.005 μm, and the internal electrodes 4a and 4b are
Was EB vapor-deposited with a thickness of 500 Å, and as the thin film dielectric 3, polyurea with a thickness of 2000 Å was formed by vapor deposition polymerization using a metal mask. The inorganic insulating film 5 is SiON formed by plasma CVD method.
The film was formed to a thickness of 2 μm, and the resin layer 6 was formed by a photolithography method using a positive resist OFPR-2 manufactured by Tokyo Ohka Kogyo Co., Ltd.

【0019】つぎにフッ酸(HF)とフッ化アンモニウ
ム(NH4 F)を1:5の比率で混合したエッチング液
に浸漬し樹脂層6を形成していない部分のSiON膜を
除去し、その後炭酸ガスレ−ザ−によるスクライブライ
ンを入れ基板分割を行い外部電極7を形成して比較例1
の薄膜コンデンサを完成した。
Next, the SiON film in the portion where the resin layer 6 is not formed is removed by immersing it in an etching solution in which hydrofluoric acid (HF) and ammonium fluoride (NH 4 F) are mixed in a ratio of 1: 5. Comparative Example 1 in which a scribe line by a carbon dioxide gas laser was inserted to divide the substrate to form external electrodes 7.
The thin film capacitor of was completed.

【0020】(比較例2)セラミック基板1上に図3に
示す従来の形状のグレ−ズ層2を有する薄膜コンデンサ
を形成した。グレ−ズ層2の膜厚は50μm、グレ−ズ
表面のRaは0.01μmとし、内部電極4a,4bは
アルミニウムを500Åの厚さでEB蒸着し、薄膜誘電
体3としてポリユリアを2000Åの厚さで蒸着重合法
によりそれぞれメタルマスクを用いてパタ−ン形成し
た。無機絶縁膜5はプラズマCVD法によるSiON膜
を2μmの厚さで形成し、樹脂層6は(株)セイコ−ア
ドバンス製スクリ−ン印刷用樹脂1300番120ホワ
イトをスクリ−ン印刷法で形成した。
Comparative Example 2 A thin film capacitor having a conventional glaze layer 2 shown in FIG. 3 was formed on a ceramic substrate 1. The thickness of the glaze layer 2 is 50 μm, Ra of the glaze surface is 0.01 μm, aluminum is EB vapor-deposited on the internal electrodes 4a and 4b to a thickness of 500 Å, and the thin film dielectric 3 is made of polyurea to a thickness of 2000 Å. Then, patterns were formed by vapor deposition polymerization using metal masks. As the inorganic insulating film 5, a SiON film having a thickness of 2 μm is formed by a plasma CVD method, and as the resin layer 6, a screen printing resin 1300 # 120 white manufactured by Seiko Advance Co., Ltd. is formed by a screen printing method. ..

【0021】つぎにフッ酸(HF)とフッ化アンモニウ
ム(NH4 F)を1:5の比率で混合したエッチング液
に浸漬し樹脂層6を形成していない部分のSiON膜を
除去し、その後炭酸ガスレ−ザ−によるスクライブライ
ンを入れ基板分割を行い外部電極7を形成して比較例2
の薄膜コンデンサを完成した。
Then, the SiON film in the portion where the resin layer 6 is not formed is removed by immersing in an etching solution in which hydrofluoric acid (HF) and ammonium fluoride (NH 4 F) are mixed at a ratio of 1: 5. Comparative Example 2 in which a scribing line using a carbon dioxide gas laser was inserted to divide the substrate into external electrodes 7.
The thin film capacitor of was completed.

【0022】(比較例3)セラミック基板1上に図1に
示す構成により薄膜コンデンサを形成した。グレ−ズ層
2の膜厚は5μm、グレ−ズ表面のRaは0.4μmと
し、内部電極4a、4bはアルミニウムを500Åの厚
さでEB蒸着し、薄膜誘電体3としてポリユリアを20
00Åの厚さで蒸着重合法によりそれぞれメタルマスク
を用いてパタ−ン形成した。無機絶縁膜5はプラズマC
VD法によるSiON膜を2μmの厚さで形成し、樹脂
層6は(株)セイコ−アドバンス製スクリ−ン印刷用樹
脂1300番120ホワイトをスクリ−ン印刷法で形成
した。
(Comparative Example 3) A thin film capacitor was formed on a ceramic substrate 1 with the structure shown in FIG. The thickness of the glaze layer 2 is 5 μm, Ra on the glaze surface is 0.4 μm, and aluminum is deposited on the internal electrodes 4a and 4b by a thickness of 500 Å by EB to form polyurea as a thin film dielectric 3.
Patterns having a thickness of 00Å were formed by vapor deposition polymerization using metal masks. The inorganic insulating film 5 is plasma C
A SiON film by the VD method was formed to a thickness of 2 μm, and the resin layer 6 was formed by Seiko Advance Co., Ltd. screen printing resin 1300 # 120 white by the screen printing method.

【0023】つぎにフッ酸(HF)とフッ化アンモニウ
ム(NH4 F)を1:5の比率で混合したエッチング液
に浸漬し樹脂層6を形成していない部分のSiON膜を
除去し、その後炭酸ガスレ−ザ−によるスクライブライ
ンを入れ基板分割を行い外部電極7を形成して比較例3
の薄膜コンデンサを完成した。
Next, the SiON film in the portion where the resin layer 6 is not formed is removed by immersing it in an etching solution in which hydrofluoric acid (HF) and ammonium fluoride (NH 4 F) are mixed at a ratio of 1: 5. Comparative Example 3 in which a scribing line using a carbon dioxide gas laser was inserted to divide the substrate to form external electrodes 7.
The thin film capacitor of was completed.

【0024】上記実施例1、2による薄膜コンデンサの
特性と比較例1、2、3による薄膜コンデンサの特性を
(表1)に比較して示す。
The characteristics of the thin film capacitors according to Examples 1 and 2 and the characteristics of the thin film capacitors according to Comparative Examples 1, 2 and 3 are shown in comparison with (Table 1).

【0025】[0025]

【表1】従来の約50μmの膜厚のグレ−ズ層2を用い
た比較例1、2は完成素子の約40%が信頼性不良を生
じ、また充放電試験によってtanδ値に異常を生じ
た。 信頼性不良の原因の1つは、メタルマスクとグレ
−ズ層2の面との密着が悪いためポリユリアよりなる薄
膜誘電体3がメタルマスクから漏れて成膜され、SiO
N膜よりなる無機絶縁膜5とのクリアランスが確保でき
なくなるためのSiON膜の封止の不完全性にある。も
う1つの原因はフォトレジストの解像度、あるいはスク
リ−ン印刷による樹脂形成精度の劣化によるレ−ザ−ス
クライブ部分への樹脂層6のはみ出により、レ−ザ−が
樹脂層6の上からSiON膜を叩き、SiON膜にクラ
ックが発生することにある。
Table 1 In Comparative Examples 1 and 2 using the conventional glaze layer 2 having a film thickness of about 50 μm, about 40% of the completed devices have poor reliability, and the tan δ value becomes abnormal due to the charge / discharge test. It was One of the causes of the poor reliability is that the thin film dielectric 3 made of polyurea leaks from the metal mask because the adhesion between the metal mask and the surface of the glaze layer 2 is poor.
This is an incomplete sealing of the SiON film because the clearance with the inorganic insulating film 5 made of the N film cannot be secured. Another cause is that the resin layer 6 protrudes from the resin layer 6 due to the resolution of the photoresist or the deterioration of the resin forming accuracy due to the screen printing. There is a possibility that a crack is generated in the SiON film by hitting.

【0026】充放電試験によるtanδ値異常の原因
は、上記の樹脂層6の外部電極7側へのはみ出しによる
内部電極4a、4bと外部電極7との電気的接合の劣化
によるものである。
The cause of the abnormal tan δ value in the charge / discharge test is that the electrical connection between the internal electrodes 4a and 4b and the external electrode 7 is deteriorated by the protrusion of the resin layer 6 to the external electrode 7 side.

【0027】また、比較例3のように5μmの膜厚のグ
レ−ズ層2を用いるとRaが0.4μmとなる。このた
め全てのパタ−ン精度は良好となるが、ポリユリアの耐
電圧が劣化し、SiON膜の封止性が劣化するため、耐
電圧歩留が低下し、さらに信頼性も低下する。
When the glaze layer 2 having a film thickness of 5 μm is used as in Comparative Example 3, Ra becomes 0.4 μm. Therefore, all the pattern precisions are good, but the withstand voltage of the polyurea is deteriorated and the sealing property of the SiON film is deteriorated, so that the withstand voltage yield is lowered and the reliability is also lowered.

【0028】それに対し、実施例1、2は、グレ−ズ層
2の膜厚を10〜25μmとすることで完成素子はポリ
ユリアとSiON膜とのクリアランスを確保でき、また
フォトレジストの解像度の良化、あるいはスクリ−ン印
刷法による樹脂形成の高精度化が図れるため、樹脂層6
のはみ出しが無く、レ−ザ−部分が確保できるようにな
り、100%の信頼性を確保することができた。また内
部電極4a、4bと外部電極7との電気的接合も良好で
あり充放電試験によるtanδ値の変化はなかった。
また、Raは0.2μm迄は特性上問題はなかった。
On the other hand, in Examples 1 and 2, by setting the thickness of the glaze layer 2 to 10 to 25 μm, the completed element can secure the clearance between the polyurea and the SiON film, and the resolution of the photoresist is good. Or the accuracy of the resin formation by the screen printing method can be improved.
There was no protrusion, and the laser portion could be secured, and 100% reliability could be secured. Also, the electrical connection between the internal electrodes 4a and 4b and the external electrode 7 was good, and there was no change in the tan δ value due to the charge / discharge test.
Further, Ra had no problem in characteristics up to 0.2 μm.

【0029】なお、本実施例では薄膜誘電体3としてポ
リユリアを用いたが、他の有機薄膜あるいは無機薄膜を
用いても同様の効果が得られる。また無機絶縁膜5とし
てプラズマCVD法によるSiONを用いたが、他の成
膜方法による封止性のよい材料でもよい。また樹脂層6
の樹脂は適応可能な他の樹脂材料でもよく、その形成方
法も本実施例ではフォトリソグラフ法、スクリ−ン印刷
法を用いたが、他の方法を用いてもよいことはいうまで
もない。さらに本発明では薄膜コンデンサについて述べ
たが、他の有機、無機、金属薄膜を用いた他の回路部品
についても同様のことが言える。
In this embodiment, polyurea is used as the thin film dielectric 3, but the same effect can be obtained by using other organic thin film or inorganic thin film. Further, although SiON by the plasma CVD method is used as the inorganic insulating film 5, a material having a good sealing property by another film forming method may be used. In addition, the resin layer 6
The resin may be any other applicable resin material, and the photolithographic method or the screen printing method is used in the present embodiment as the forming method, but it goes without saying that other methods may be used. Further, although the present invention describes the thin film capacitor, the same can be said for other circuit parts using other organic, inorganic, and metal thin films.

【0030】[0030]

【発明の効果】上記実施例から明らかなように、本発明
の薄膜コンデンサはグレ−ズ層の膜厚を10〜25μ
m、Raを0.01〜0.2μmとすることにより、グ
レ−ズ面と板状およびスクリ−ンマスクとの密着性が向
上し、またフォトレジストの解像度劣化が少なくなり、
所定のパタ−ン形状を高精度に確保することができ、優
れたコンデンサ特性を得ることができる。
As is apparent from the above embodiments, the thin film capacitor of the present invention has a glaze layer thickness of 10 to 25 .mu.m.
By setting m and Ra to 0.01 to 0.2 μm, the adhesion between the glaze surface and the plate-like or screen mask is improved, and the deterioration of the resolution of the photoresist is reduced,
A predetermined pattern shape can be secured with high accuracy, and excellent capacitor characteristics can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例および従来の薄膜コンデンサ
の基本構成を示す断面図
FIG. 1 is a sectional view showing a basic configuration of an embodiment of the present invention and a conventional thin film capacitor.

【図2】従来の薄膜コンデンサにおけるグレ−ズ層の印
刷パタ−ンを示す斜視図。
FIG. 2 is a perspective view showing a printing pattern of a glaze layer in a conventional thin film capacitor.

【図3】同薄膜コンデンサにおけるセラミック基板上の
グレ−ズ層の形状を示す部分断面図
FIG. 3 is a partial sectional view showing the shape of a glaze layer on a ceramic substrate in the same thin film capacitor.

【符号の説明】[Explanation of symbols]

1 セラミック基板 2 グレ−ズ層 3 薄膜誘電体 4a、4b 内部電極 5 無機絶縁膜 6 樹脂層 7 外部電極 1 Ceramic Substrate 2 Glaze Layer 3 Thin Film Dielectric 4a, 4b Internal Electrode 5 Inorganic Insulation Film 6 Resin Layer 7 External Electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】少なくとも一主面の両端部を除く領域にグ
レ−ズ層を形成したセラミック基板と、前記グレ−ズ層
上に薄膜誘電体を間に介在させて積層され各一端が前記
グレ−ズ層を越えて前記セラミック基板の両端部に一層
毎交互に延長して配設された一対の内部電極と、前記積
層された一対の内部電極および薄膜誘電体上に前記セラ
ミック基板の両端部を除いて形成された無機絶縁膜と、
その無機絶縁膜上に形成された樹脂層と、前記無機絶縁
膜および前記樹脂層に被覆されていない前記内部電極の
延長部分の前記セラミック基板の両端部に形成された外
部電極を有する薄膜コンデンサであって、前記グレ−ズ
層の膜厚が10μm〜25μmであり、かつ前記グレ−
ズ層の表面の平均中心線粗さ(Ra)が0.01μm〜
0.2μmであることを特徴とする薄膜コンデンサ。
1. A ceramic substrate on which a glaze layer is formed in a region excluding both ends of at least one main surface, and a thin film dielectric is interposed on the glaze layer to be laminated, and one end of each of the glaze layers is formed into the glaze layer. -A pair of internal electrodes alternately extended over the ceramic substrate at both ends of the ceramic substrate, and both ends of the ceramic substrate on the laminated pair of internal electrodes and a thin film dielectric. An inorganic insulating film formed by removing
A thin film capacitor having a resin layer formed on the inorganic insulating film, and external electrodes formed on both ends of the ceramic substrate in an extended portion of the internal electrode not covered by the inorganic insulating film and the resin layer. And the thickness of the glaze layer is 10 μm to 25 μm, and
The average center line roughness (Ra) of the surface of the slag layer is 0.01 μm to
A thin film capacitor having a thickness of 0.2 μm.
JP3285895A 1991-10-31 1991-10-31 Thin film capacitors Expired - Fee Related JP3042090B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3285895A JP3042090B2 (en) 1991-10-31 1991-10-31 Thin film capacitors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3285895A JP3042090B2 (en) 1991-10-31 1991-10-31 Thin film capacitors

Publications (2)

Publication Number Publication Date
JPH05129149A true JPH05129149A (en) 1993-05-25
JP3042090B2 JP3042090B2 (en) 2000-05-15

Family

ID=17697414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3285895A Expired - Fee Related JP3042090B2 (en) 1991-10-31 1991-10-31 Thin film capacitors

Country Status (1)

Country Link
JP (1) JP3042090B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008251974A (en) * 2007-03-30 2008-10-16 Tdk Corp Thin-film component and manufacturing method thereof
US7489036B2 (en) 2006-02-17 2009-02-10 Tdk Corporation Thin-film device
EP2078974A2 (en) 2008-01-08 2009-07-15 Olympus Corporation Microscope
US7675136B2 (en) 2006-03-31 2010-03-09 Tdk Corporation Thin-film device including a terminal electrode connected to respective end faces of conductor layers
KR101522666B1 (en) * 2013-12-16 2015-05-26 한국과학기술연구원 Multi layer ceramic capacitor and method for fabricating the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7489036B2 (en) 2006-02-17 2009-02-10 Tdk Corporation Thin-film device
US7675136B2 (en) 2006-03-31 2010-03-09 Tdk Corporation Thin-film device including a terminal electrode connected to respective end faces of conductor layers
US8242575B2 (en) 2006-03-31 2012-08-14 Tdk Corporation Thin-film device including a terminal electrode connected to respective end faces of conductor layers
JP2008251974A (en) * 2007-03-30 2008-10-16 Tdk Corp Thin-film component and manufacturing method thereof
US7683269B2 (en) 2007-03-30 2010-03-23 Tdk Corporation Thin film device and method for manufacturing the same
EP2078974A2 (en) 2008-01-08 2009-07-15 Olympus Corporation Microscope
KR101522666B1 (en) * 2013-12-16 2015-05-26 한국과학기술연구원 Multi layer ceramic capacitor and method for fabricating the same

Also Published As

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