JPH05127990A - Cache data transfer system - Google Patents

Abstract

PURPOSE:To allow to execute look-ahead only in the case of need, and to eliminate useless using time of a bus. CONSTITUTION:A microprogram 11 has transfer mode switching information 11a. A processor 12 informs a cache memory 13 of transfer mode information by executing the microprogram 11. Thus, in the case that mishit is caused, as for data transfer from a main memory 14 to the cache memory 13, for instance, either a block boundary transfer mode A to transfer the data to the block boundary of one block containing the requested data or a requested data transfer mode B to transfer only the block of the requested data is designated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a cache memory, and more particularly to a cache data transfer system from its main memory to the cache memory.

[0002]

2. Description of the Related Art Generally, an information processing apparatus or the like is provided with a high-speed cache memory having a small storage capacity in order to improve processing speed. Such a cache memory stores a part of the data in the main memory, responds as it is if the data is in the cache memory when requested by the processor, and if the data is not in the cache memory. Transfers its data from main memory and responds to the processor. FIG. 2 shows a block diagram for explaining such a cache data transfer method. The device shown is a microprogram (μP)
1, a processor 2, a cache memory 3, and a main memory 4. The microprogram 1 is for the processor 2 to execute an instruction, and includes an operation part and an operand part. Cache memory 3
Is a memory that stores a part of the data in the main memory 4, and stores the data in the main memory 4 in block units. FIG. 3 shows the configurations of the cache memory 3 and the main memory 4. The cache memory 3 includes a tag unit 3a and a data unit 3b, and each block of the data unit 3b is composed of four sub blocks. The width of one sub-block is the same as the data width of the memory bus 5,
The data width of the main memory 4 is the same as that of the memory bus 5. The four sub-blocks of the data part 3b corresponding to the address tags of the tag part 3a are data of consecutive addresses on the main memory 4, and the address tag indicates the head address thereof.

Next, the operation will be described. The processor 2 is controlled by the microprogram 1 shown in FIG. A read request 6 is issued from the processor 2 to the cache memory 3 according to an instruction from the microprogram. As a result, the cache memory 3 checks whether or not the requested data exists in the cache memory 3, and if the requested data exists, responds to the data with the processor 2 (indicated by reference numeral 7 in FIG. 2). ..

If the requested data does not exist in the cache memory 3 (miss hit), the cache memory 3
Issues a read request 8 to the main memory 4. Since the data in the cache memory 3 is managed in units of four sub blocks, the main memory 4 responds to the cache memory 3 with sub block data from request data (data of a certain sub block) to a block boundary. (Indicated by reference numeral 9 in FIG. 2). For example, if the requested data is for the sub-block 2, the main memory 4
Data is continuously transferred up to sub-block 4, which is a block boundary. Further, the memory bus cycle in this case requires three bus cycles because three sub blocks are transferred. Thereafter, when the data transfer to the cache memory 3 is completed, the response 7 is returned from the cache memory 3 to the processor 2, and the access to the cache memory 3 is completed.

[0005]

However, in the above-mentioned conventional cache transfer method, when the cache memory 3 misses, the data in the block to which the sub-block data requested by the processor 2 belongs is changed to the data of the requested sub-block. Since the continuous data from to the last data on the block boundary is transferred to the cache memory 3, the sub block data not requested by the processor 2 is transferred. For example, in FIG. 3, the requested data of the processor 2 is only the sub-block 2, but the data transfer from the main memory 4 also involves the unnecessary sub-blocks 3 and 4. Therefore, there are problems that the memory bus 5 is used for a long time and that the response time from the cache memory 3 to the processor 2 is long. In addition, here
If the data management of the cache memory 3 is performed in units of one sub-block, such a problem at the time of a mishit does not occur, but such management requires a huge memory capacity. Therefore, it is very difficult to use a small capacity cache memory. The present invention has been made to solve the above-mentioned conventional problems, and provides a cache data transfer method capable of eliminating unnecessary memory bus cycles and improving processing speed without lowering the hit rate. The purpose is to

[0006]

A cache data transfer system according to the present invention comprises a main memory and a cache memory for storing a part of data on the main memory in block units, and a processor executes a micro program instruction. Thus, in the cache data transfer method for transferring data between the main memory and the cache memory, transfer mode switching information for switching the transfer mode of the data transfer is provided in the microprogram instruction to the processor, When performing transfer between the cache memories, whether to transfer a plurality of blocks including a block of data requested by the processor or only a block of data requested by the processor based on the transfer mode switching information. Is characterized by selecting Than it is.

[0007]

In the cache data transfer system of the present invention, the microprogram has transfer mode switching information. The processor notifies the transfer mode information to the cache memory by executing the microprogram. As a result, when a mishit occurs, the data transfer from the main memory to the cache memory is, for example, a block boundary transfer mode in which data is transferred to a block boundary of one block including the requested data, or a block of the requested data is transferred. Only one of the request data transfer modes for transferring only data is specified. Therefore, the data can be prefetched only when necessary, and unnecessary use time of the bus can be eliminated.

[0008]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing a system configuration for implementing the cache data transfer system of the present invention.
The system shown in the figure includes a microprogram (μP) 11 and
It includes a processor 12, a cache memory 13, and a main memory 14. The microprogram 11 is composed of an operation part and an operand part, and has 1-bit transfer mode switching information 11a. Processor 1
2 is controlled by this microprogram 11,
The cache memory 13 performs sequential instruction processing.
And the main memory 14 is the conventional cache memory 3
It has the same configuration as the main memory 14.

Next, the operation will be described. By executing the microprogram 11 by the processor 12,
Data access to the cache memory 13 is instructed. The data access order of the microprogram 11 includes a block boundary transfer mode and a request data transfer mode. These transfer modes are identified by the transfer mode switching information 11a in the microprogram 11. When the read request 16 is notified from the processor 12 to the cache memory 13, the cache memory 13 checks whether the data is in the cache memory 13, and if there is, the corresponding data is retrieved by the processor 12
To the response data 17 as the response data. Incidentally, such an operation is similar to the conventional one.

When the requested data from the processor 12 does not exist in the cache memory 13 (miss hit), the cache memory 13 notifies the main memory 14 of the read request 18 or 19. These read requests 18 and 19 also include data transfer mode information based on the transfer mode switching information 11a of the microprogram 11. The read request 18 is the block boundary transfer mode A, and the read request 19 is the requested data transfer mode B.
The request transfer mode is shown. The main memory 14 receiving the read request 18 or 19 returns two types of responses 20 or 21 according to the data transfer mode. Here, the response 20 is a response in the block boundary transfer mode A, and the response 21 is a response in the requested data transfer mode B.

Next, the transfer mode will be described in detail. Block Boundary Transfer Mode FIG. 4 is an explanatory diagram of the block boundary transfer mode. The read request from the cache memory 13 to the main memory 14 (read request 18 in FIG. 1) is in sub-block units, and here, as an example, the read request is for the sub-block 2. Main memory 14
Responds to this read request with continuous data up to the block boundary including the sub-block 2 via the memory bus 15 to the cache memory 13 (Response 2 in FIG. 1).
0). Here, the order of the data is that the sub-block 2 which is the requested data is the first, the sub-block 3 is the second cycle, and the sub-block 4 is the third cycle, so that the data is continuously transferred. At this time, the response memory bus cycle is 3 cycles, which is similar to the conventional data transfer. The cache memory 13 writes the received data from the main memory 14 to the data section 13b, and then responds to the processor 12. In FIG. 4, 13a indicates a tag portion of the cache memory 13.

Request Data Transfer Mode FIG. 5 is an explanatory diagram of the request data transfer mode. The read request from the cache memory 13 to the main memory 14 (read request 19 in FIG. 1) is in sub-block units, and here again, the read request is for the sub-block 2. In response to this read request, the main memory 14 responds only the data of the sub block 2 to the cache memory 13 via the memory bus 15 (response 21 in FIG. 1). At this time, the response memory bus cycle is one cycle. After that, the cache memory 13 writes the received data to the data portion 13b, and then responds to the processor 12, as in the case of the block boundary transfer mode.

As described above, in the above-described embodiment, the transfer mode can be selected for each instruction from the two kinds of transfer modes.
If the instruction requires only the data of one sub-block managed by 3, the requested data can be transferred from the main memory 14 to the cache memory 13, thus eliminating unnecessary bus use time. You can Further, by selecting the block boundary transfer mode, it is possible to prefetch data from the main memory 14 only when necessary.

In the above embodiment, the transfer modes are two types, that is, the request data only or the block boundary. However, the present invention is not limited to this, and the transfer mode is further divided into three or more types. It may be configured to set the mode. To this end, if the transfer mode switching information 11a of the microprogram 11 is 2 bits or more, it is possible to specify three or more transfer modes. In the above embodiment, the data transfer from the main memory 14 to the cache memory 13 was explained as the data transfer between the cache memory 13 and the main memory 14, but conversely to this, from the cache memory 13 to the main memory 14. The data transfer can be performed in the same manner as in the above embodiment.

[0015]

As described above, according to the cache data transfer method of the present invention, when the data transfer between the main memory and the cache memory is performed, only the request data from the processor is transferred or a plurality of blocks are transferred. Since the micro program switches whether to transfer the data for each instruction in units of instructions, it is possible to pre-read the data only when necessary and eliminate the bus usage time due to unnecessary data transfer. The speed can be improved.

[Brief description of drawings]

FIG. 1 is a system configuration diagram for implementing a cache data transfer system of the present invention.

FIG. 2 is a system configuration diagram for implementing a conventional cache data transfer method.

FIG. 3 is a configuration diagram of a general cache memory system.

FIG. 4 is an explanatory diagram of transfer control up to block boundaries in the cache data transfer method of the present invention.

FIG. 5 is an explanatory diagram of transfer control of only request data in the cache data transfer method of the present invention.

[Explanation of symbols]

 11 Micro Program 11a Transfer Mode Switching Information 12 Processor 13 Cache Memory 13a Tag Part 13b Data Part 14 Main Memory A Block Boundary Transfer Mode B Request Data Transfer Mode

Claims (1)

[Claims] 1. A main memory and a cache memory for storing a part of data on the main memory in block units, wherein a processor executes a microprogram instruction to allow a space between the main memory and the cache memory. In a cache data transfer method for transferring data, transfer mode switching information for switching a transfer mode of the data transfer is provided in a microprogram instruction to the processor, and when transfer between the main memory and the cache memory is performed, the transfer mode A cache data transfer method characterized by selecting whether to transfer a plurality of blocks including a block of data requested by the processor or to transfer only a block of data requested by the processor based on switching information.