JPH11149409A - Memory controller and computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve efficiency in data copy processing inside a main memory. SOLUTION: When a data copy instruction is received from a processor 1, a memory controller 3 requests the invalidation of cache contents corresponding to the area of the copy destination in the main memory to the processor 1 and when the area of the copy source in a main memory 4 is not reloaded on a cache, data are copied between the areas of the main memory 4 but when that area is reloaded, the write-back of data in the relevant area is requested to the cache. In response to the request, the data sent from the cache are written in both the areas of the copy source and the copy destination in the main memory 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory controller for controlling a memory access in a computer system, and more particularly to a technique for improving a data access processing speed in a computer system.

[0002]

2. Description of the Related Art In a general computer system, a dedicated cache memory (upper-level memory) constituted by a high-speed memory inside a processor, and a large-capacity and low-speed main memory (lower-level memory) constituted by an inexpensive DRAM or the like are used. ) Form a storage hierarchy. And
Frequent access to the main memory due to a cache miss where the target data does not exist in the cache memory is a main factor that degrades the processing performance of the computer system.

More specifically, a memory bus for transmitting main memory data has a relatively long wiring length, and it is difficult to increase the operating frequency in terms of circuit mounting. Therefore, even if the operating frequency of the processor is increased, if the access to the main memory occurs frequently, the slowness of the memory bus speed becomes a major bottleneck, and the overall performance is not sufficiently improved.

To cope with this, conventionally, it has been practiced to increase the cache capacity and reduce the frequency of access to the main memory.

[0005] As another conventional technique, as described in Japanese Patent Application Laid-Open No. 01-251250, in a multiprocessor system, the cache memory of each processor is commonly used by each processor to reduce the frequency of cache misses. Techniques are known for reducing this and maintaining coherence between individual caches.

[0006]

Generally, a cache memory is intended to reduce access to a main memory on the premise of the locality of an access area. Is relatively small, the effect of improving the performance by the cache memory is great.

However, in a computer system that executes an application in which a large amount of data is frequently copied or moved in a main memory, such as a data server for general business or a web server on the Internet in recent years, a cache memory is not used. Cache misses occur frequently and the effect of performance improvement by the cache memory is small.

For example, in a relational database system (RDBS) or the like, data of 1 GB or more is copied or moved on a daily basis, so that in a computer system used for such a purpose, a memory bus is frequently used. Sufficient performance cannot be obtained. Further, in a computer system for copying and moving such a large amount of data in the main storage, a load on a processor for performing the processing is large.

Accordingly, an object of the present invention is to provide a computer system which can copy and move a large amount of data in a main memory more efficiently. In particular, it is another object of the present invention to realize data coherence control that does not further degrade the efficiency of copying and moving data in a large amount of main storage in a multiprocessor system.

[0010]

In order to achieve the above object,
The present invention is a memory controller which controls at least access to a main memory of a processor in a computer system, wherein the processor issues a data copy instruction requesting data copy between areas of the main memory,
Means for receiving the specification of the copy source area and the copy destination area for performing data copy, means for storing the specification of the received copy source area, and the specification of the received copy destination area, and the copy source of the main memory storing the specification Means for copying data from the area to the copy destination area of the main memory storing the designation.

According to the memory controller of the present invention, the processing performed by the processor for copying data in the main storage only issues a data copy instruction, so that the processing load is significantly reduced. In addition, since data copying in the main storage can be realized only by sending and receiving data between the main storage and the memory controller, it is not necessary to use a low-speed bus to which a processor and a peripheral device are connected. Therefore, the data copy efficiency is also improved.

[0012] Further, the data is read from the copy source area of the main memory in which the designation is stored in the memory controller, and the data in the area is updated in the cache memory and the data in the copy source area of the main memory is updated. Means for issuing a write-back request to the processor for requesting write-back of data in the area of the cache memory which does not match the data, and processing the data sent from the processor in response to the issued write-back request. Means for writing to both the copy source area and the copy destination area of the main memory storing the designation, the data copy required for these areas and the copy source area of the main memory required for data copy. Guarantees coherency with the cache memory in the destination area Uninaru.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below.

FIG. 1 shows the configuration of a computer system according to this embodiment.

As shown, the computer system according to the present embodiment has the configuration of a general computer system, and includes a plurality of processors 1, an input / output unit 25, a display 26, a network adapter 27, a hard disk 28, It has a peripheral device such as a CD-ROM 29, a transmission system 22 such as a bus and a switch matrix, a memory controller 3, a main memory 4, and the like. Transmission system 22
Means a plurality of processors, a memory control unit 3,
The input / output units 25 are interconnected. Each of the peripheral devices 26 to 29 is connected to the input / output unit 25,
The main memory 4 is connected to the memory controller 3.

In such a configuration, the memory controller 3 controls access to the main memory 4 in accordance with commands sent from the processor 1 and the peripheral devices 26 to 29.

The transmission system 22 may be a bus or other forms such as a switch matrix. Also, in FIG. 1, the transmission system between the processor 1 and the memory controller 3 and the transmission system between the input / output unit 25 and the memory controller 3 are shown as common, but the input / output unit 26 is directly connected to the memory controller 3. Etc.
Other connection forms may be used.

Next, FIG. 2 shows the internal configuration of the memory controller 3.

Here, an external storage device 6 such as a hard disk and other peripheral devices 7 are provided as the peripheral devices 26 to 29 in FIG. 1, and the input / output unit 25 in FIG. The case where the bus 22 is a bus is shown as an example.

Now, the memory controller unit 3
A bus control unit 8 that controls data transfer between the processor 1 and the external bus controller 5; an instruction input processing unit 9 that loads an access instruction to the main memory 4 from the processor 1 or the external storage device 6 into the memory controller; An address translation unit 10 for translating between a logical address to be accessed specified by an access instruction from the processor 1 or the peripheral device 7 and a physical address in the main memory 4; A data buffer 11 for temporarily storing data to be written to the main memory 4, a memory input / output control unit 12 for controlling input / output of data to / from the main memory 4, and a data copy control unit 13.

The data copy control unit 13 receives a data copy (data copy) command of data in the main memory 4 from the processor 1, the peripheral device 7, or the like, and stores the copy source address specified by the command. Register (Source-Pa
ge) 14, a DT register (Destination-Page) 15 for storing a copy destination address specified by an instruction, and a page size determined based on a swap size unit of temporary storage data between the main storage 4 and the external storage device 6. And a status register (StatusReg) 17 for storing the status of the data copy process.

Next, the storage hierarchy is shown in FIG.

The storage hierarchy of a general computer system is composed of a plurality of levels. One data transfer between layers is performed only between two adjacent layers. Usually, a hierarchy near the processor is called an upper level, and a hierarchy farther away is called a lower level. The higher-level memory has a smaller storage capacity and is faster than the lower-level memory. The fixed-length minimum unit of data transfer between the two levels is called a normal block, and data is transferred in this unit. The fact that the data requested from the processor or the like to the memory exists in any of the blocks stored in the highest level hierarchy is called a hit, and the absence of it is called a miss. In the case of a hit, the data is read directly from the highest level hierarchy. In the case of a miss, however, the next lower storage hierarchy is searched for the requested data. Therefore, in the case of a mistake, the processing speed is reduced due to a reduction in access speed and data transfer between layers.

Hereinafter, the operation of the memory controller 3 according to the present embodiment will be described.

Here, FIG.
The flow of information in the inside is shown.

In the figure, a processor 1 and peripheral devices 7
The instruction input unit 9 fetches the access instruction of the main memory 4 and the logical address of the access target issued on the bus for example. When the access instruction is a store instruction,
The data output by the instruction on the bus is taken into the data buffer 11.

When the access instruction fetched by the instruction input unit 9 is a normal load / store instruction, the logical address to be accessed is converted into a physical address via the address conversion unit 10 and the memory input / output control unit is transferred together with the instruction. 1
Hand over to 2. When the instruction is a store instruction, the memory input / output control unit 12 writes the data targeted by the store instruction fetched into the data buffer 11 into the converted physical address of the main memory 4. In the case of a load instruction, the memory input / output control unit 12 reads data from the converted physical address in the main memory 4 and stores the data in the data buffer 11. The stored data to be loaded is then transferred to the bus control unit 4.
2 to the bus.

On the other hand, if the access command received by the command input unit 9 is a data copy command, the following processing is performed.

First, the data copy command and the logical addresses of the copy source and the copy destination are passed to the data copy control unit 13 from the command input unit 9. The data copy control unit 13 issues a read / write request for realizing the data copy from the transferred copy source to the copy destination, and realizes the data copy in the main storage 4 using the data buffer 11. Specifically, it is assumed that data copy is performed for each page,
If the copy source logical address and copy destination logical address of the data copy instruction are specified by a page,
First, the data copy control unit 13 stores the copy source page address in the SP register 14 and stores the copy destination page address in the DT register 14. Then, the copy source page address is sent to the address conversion unit 10 and converted into a physical address. In addition, the copy destination page address is sent to the address conversion unit 10 and converted to a physical address.
Then, the data copy control unit 13 internally uses the converted physical address of the copy source page and the physical address of the copy destination page to perform data copy between pages in units of blocks. A pair of a physical address of a block and a physical address of a copy destination block is sequentially generated. That is, the physical addresses of two blocks at the same position in the copy source page and the copy destination page are set, the copy source page is set as the physical address of the copy source block, the copy destination is set as the physical address of the copy destination block, Generate sequentially. Then, the data copy control unit 13 determines, for each set of the physical address of the copy source block and the physical address of the copy destination block, sequentially generated from the physical address of the copy source block of the main memory via the memory input / output control unit 12. The process of reading data, writing the data into the data buffer 11, and writing the data read into the data buffer 11 from the physical address of the copy source block of the main memory 4 to the physical address of the copy destination block of the main memory is sequentially performed in block units. However, as described below,
If the block of the page of the copy source has been read into the cache of the processor 1 or the peripheral device 7 and has been rewritten in the cache, this block is read from the copy source block in the main memory 4. Data copy between the copy destination blocks is performed, and a process of writing the block written back from the cache to both the copy source block and the copy destination block is performed.

In the data copy operation of the memory controller unit 3, if the processor 1 or the peripheral device 7 has a cache memory, in order to guarantee consistency between the cache and the main memory 4, Coherent control is required.

Hereinafter, coherent control performed by the memory controller 3 will be described.

FIG. 5 shows the configuration of the data copy control unit 13 which is the center of the coherent control.

As shown, the data copy control unit 13
Has the above-mentioned SP register 14, DT register 15, page size register 16, and status register 17. Further, a copy control unit 52 and a block address control unit 51 are provided.

In order to realize coherent control, the first
In addition, the data copy control unit 13 prohibits the processor 1 and the peripheral device 7 from accessing the main memory 4 during data copy.

That is, as shown in FIG. 6, upon receiving a data copy command from the command input unit 9, the copy control unit 52 of the data copy control unit 13 sets a value indicating a copying status in the status register 17. The data is held until the data copy described above and the write-back of a dirty block described later are completed. When a value indicating a copying status is set in the status register 17, the instruction input unit 9
Is the memory load from the processor 1 or the peripheral device 7, etc.
When a store / data copy instruction is output to the bus 41, a Wait request is output to the bus 41 as a response to the instruction. When the data copy and the write-back of the dirty block described later are completed and the value indicating the copy waiting state is set in the status register 17,
An it release request is sent to the bus 42.

On the other hand, when the Wait request is responded to the issued instruction, the processor 1 re-issues the instruction to which the Wait request has been responded when the Wait release request is issued. After transmitting the Wait release request to the bus 42, the instruction input unit 9 fetches an instruction until the value indicating the copying status is set in the status register 17, and processes the instruction as described above.

Second, when a block of a copy destination page before being rewritten by the data copy process is read into the cache of the processor 1 or the peripheral device 7, the data copy control unit 13 7
In order not to be used by
A process of issuing a request to invalidate the cache block of the copy destination page indicated as date to the bus 41 is performed.

That is, when the page address is set in the DP register 15, the block address generator 51 of the data copy controller 13 generates the physical address of the copy destination block as described above. The copy control unit 52
Prior to the data copy processing, a request to invalidate the block of the generated physical address is sent to the bus 41. Each processor 1 and peripheral device 7 receiving this invalidates the cache block if it has been read into its own cache.

Third, at the time of data copy, the data copy control unit 13 reads the block of the copy source page into the cache of the processor 1 or the peripheral device 7,
Further, when this is rewritten on the cache, a write-back request shown as Clean in FIG. 7 is issued to the bus 41 so that the rewritten data is reflected also on the copy destination page. Then, the write-backed data is written to both the copy source and copy destination pages.

As shown in FIG. 8, this process is performed as a part of the data copy process after the data copy instruction is issued and the transmission of the above-mentioned host invalidation request is completed.

FIG. 9 shows a processing procedure of the data copy processing.

As shown, in this process, the copy control unit 52 sends a write-back (Clean) request of the copy source block in which the physical address has been generated to the bus 41 (step 92). Each processor 1 and peripheral device 7 receiving this
In the case where this cache block is read into its own cache and this is rewritten on the cache (DIrty), the Modified signal and the data of the block on the cache are sent to the memory control unit 3. , Request a writeback.

When receiving the Modified signal, the copy control unit 52 stores the data of the block requested to be rewritten into the physical address of the generated copy source block and the physical address of the copy destination block in the main memory 4 as a memory. Writing is performed via the input / output control unit 12 (step 94).

On the other hand, when the Modified signal is not received, data is copied from the generated physical address of the copy source block to the physical address of the copy destination block in the main memory 4 as described above.

Finally, the status register 17
Is set to a value indicating a copy waiting state, and the process is terminated.

The embodiment of the present invention has been described above.

As described above, according to the present embodiment, when a data copy requester copies a large amount of data between pages of main memory, the load on the requester can be reduced, and the cache can be cached in a multiprocessor system. Can reduce the number of data write-backs by cache coherency control when there is a processor or peripheral device with
Since the bus usage rate can be reduced, there is an effect of improving the processing speed.

More specifically, FIG. 10 shows a conventional computer system and a result of evaluation of a data copy processing capability according to the present embodiment.

Here, page size (P) = 16 KB
yte, cache line size (C) = 64 Byte
e, memory load latency (l) = 30, memory store latency (s) = 10, main memory access latency (m) from the memory controller was 7, and the dirty rate (d) was used. The total latency (LO) when one page of data is copied in the conventional system is as follows: LO = 1. (P / C). (1-d) + s. (P / C) In addition, the total latency (LN) when the data copy according to the present invention is executed can be expressed by the following equation since there is no memory load latency.

LN = (m · (P / C)) · (1+ (1−
d)) + s · (P / C) · d FIG. 10 shows the processing capacity ratio when the dirty ratio is changed from 0 to 100% in the above equation.

The dirty ratio varies depending on the operating system and application software of the computer system, but is generally about 10 to 30%. The processing capacity according to the present embodiment in this range can achieve 2.5 to 3.5 times the performance of the conventional computer system. In addition, when the bus utilization rate is added to the above result, the conventional computer system uses the bus at the time of loading and storing, so that the capacity difference is larger than the above result.

[0052]

As described above, according to the present invention, it is possible to provide a computer system which can copy and move a large amount of data in the main storage more efficiently. In particular, in a multiprocessor system,
Data coherence control can be realized without deteriorating the efficiency of copying and moving data in a large amount of main storage.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a memory controller according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating a general storage hierarchy of a computer system.

FIG. 4 is a block diagram showing a configuration of a memory controller according to the embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a data copy control unit according to the embodiment of the present invention.

FIG. 6 is a diagram showing how a wait request is issued by coherent control according to the embodiment of the present invention.

FIG. 7 is a diagram showing how an invalidation request / write-back request is issued by coherent control in the embodiment of the present invention.

FIG. 8 is a state transition diagram illustrating transition of coherent control processing according to the embodiment of the present invention.

FIG. 9 is a flowchart illustrating a procedure of a data copy process according to the embodiment of the present invention.

FIG. 10 is a graph showing data copy performance of the computer system according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Processor 2 ... Bus 3 ... Memory controller 4 ... Main memory 5 ... External bus controller 6 ... External storage device 7 ... Peripheral device 8 ... Bus control part 9 ... Instruction input unit 10 ... Address conversion unit 11 ... Data buffer 12 ... Memory input / output control unit 13 ... Data copy control unit 14, 15, 16, 17 ... Register

Claims (6)

[Claims] 1. A memory controller for controlling at least access to a main memory of a processor in a computer system, comprising: executing a data copy instruction issued by the processor to request data copy between areas of a main memory; Means for receiving the specification of the copy source area and the copy destination area to be performed; means for storing the specification of the received copy source area and the specification of the received copy destination area; and Means for copying data to a copy destination area of a main memory storing the designation. 2. A computer system, comprising: a memory controller for controlling access to a main memory of at least a plurality of processors having a cache memory, wherein the processor issues a data copy between areas of the main memory issued by the processor. Means for receiving the requested data copy instruction together with the specification of the copy source area and the copy destination area for performing data copy; means for storing the specification of the received copy source area and the specification of the received copy destination area; A cache memory area from which data of a stored copy source area of the main memory is read, wherein the data of the area is updated on the cache memory and does not match the data of the copy source area of the main memory. Issue a write-back request to the processor to request a write-back of the data in the area Means for writing the data sent from the processor in response to the issued write-back request to both the copy source area and the copy destination area of the main storage storing the designation. controller. 3. The memory controller according to claim 2, wherein the data in the cache memory from which the data in the copy source area of the main memory storing the designation is read is updated in the cache memory. When there is no cache memory area that does not match the data in the main memory copy source area, the specification is stored from the main memory copy source area to the main memory copy destination area in which the specification is stored. Means for copying data. 4. A computer system comprising: the memory controller according to claim 1; a main memory whose access is controlled by the memory controller; and a processor that issues the data copy instruction. 5. The memory controller according to claim 2, comprising: a main memory whose access is controlled by the controller; and a plurality of processors having a cache memory and issuing the data copy instruction. Is an area of the cache memory in which the memory controller reads data of the copy source area of the main memory in which the designation is stored in response to the write-back instruction issued by the memory controller, and the data of the area is cached. A computer system comprising: means for sending data in an area of a cache memory that has been updated on a memory and does not match data in a copy source area of a main memory to the memory controller. 6. A computer system including a main memory and a plurality of processors having a cache memory,
A method of writing data from the cache memory back to the main storage, wherein when copying data between areas in the main storage, the data is read from a copy source area of the main storage and is stored in the cache memory. Reads data from the cache memory area where the data has been updated in the cache memory and does not match the data in the copy source area of the main memory, and stores the read data in both the copy source area and the copy destination area of the main memory. A write-back method of cache data, characterized by writing.