JP3507314B2 - Memory controller and computer system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory controller for controlling memory access in a computer system, and more particularly to a technique for improving the processing speed of data access in the computer system.

[0002]

2. Description of the Related Art In a general computer system, a dedicated cache memory (upper level memory) configured by a high-speed memory inside a processor and a large-capacity / low-speed main memory (lower level memory) configured by an inexpensive DRAM or the like. ) And form a storage hierarchy. And
The frequent access to the main memory due to a cache miss in which the target data does not exist in the cache memory is a main factor that deteriorates the processing performance of the computer system.

More specifically, the memory bus for transmitting main memory data has a relatively long wiring length, and it is difficult to increase the operating frequency in terms of circuit mounting. For this reason, even if the processor operating frequency is improved, if the access to the main memory occurs frequently, the slowness of the memory bus speed becomes a major obstacle, and the overall performance is not sufficiently improved.

Therefore, in order to deal with this, conventionally, the capacity of the cache has been increased and the frequency of access to the main memory has been reduced.

As another conventional technique, as described in Japanese Patent Laid-Open No. 01-251250, the cache memory of each processor is shared by each processor in a multiprocessor system so that the frequency of cache miss can be reduced. Techniques are known that lower the coherence between individual caches as well as reduce it.

[0006]

Generally, the cache memory is intended to reduce the access to the main memory on the premise of the locality of the access area. When is relatively small, the effect of performance improvement by the cache memory is great.

However, in a computer system which executes an application in which a large amount of data may be frequently copied or moved in the main memory such as a data server for general business in recent years or a WEB server on the Internet, the cache memory is not used. Cache misses occur frequently and the effect of performance improvement by the cache memory is small.

For example, in a relational database system (RDBS) or the like, copying or moving of data of 1 GB or more routinely occurs. Therefore, in a computer system used for such an application, the frequency of use of the memory bus increases, Sufficient performance cannot be obtained. Further, in such a computer system that copies or moves a large amount of data in the main memory, the burden on the processor that performs the processing is large.

Therefore, an object of the present invention is to provide a computer system capable of more efficiently copying and moving a large amount of data in a main memory. Another object of the present invention is to realize data coherence control that does not further deteriorate the efficiency of copying or moving a large amount of data in main memory, especially in a multiprocessor system.

[0010]

[Means for Solving the Problems] To achieve the above objects,
The present invention is a memory controller that controls access to at least a main memory of a processor in a computer system, and includes a data copy instruction issued by the processor and requesting data copy between areas of the main memory.
A means for accepting a copy source area for performing data copy and a designation of the copy destination area, a means for storing the designation of the accepted copy source area, and a designation of the accepted copy destination area, and a copy source of the main memory storing the designation Provided is a memory controller having means for copying data from an area to a copy destination area of a main memory storing a designation.

According to the memory controller of the present invention, the processing performed by the processor for copying the data in the main memory only issues the data copy instruction, so that the processing load is remarkably reduced. Further, since the data copy in the main memory can be realized only by transmitting and receiving the data between the main memory and the memory controller, it is not necessary to use a low-speed bus connected to the processor and peripheral devices. Therefore, the data copy efficiency is also improved.

Further, the area of the cache memory in which the data of the copy source area of the main memory storing the designation is read into the memory controller, and the data of the area is updated on the cache memory to the copy source area of the main memory. Means for issuing a write-back request to the processor for requesting write-back of data in the area of the cache memory that does not match the data, and data sent from the processor in response to the issued write-back request. By providing a means for writing in both the copy source area and the copy destination area of the main memory storing the designation, the data copy for these areas and the copy source area of the main memory, which are necessary for data copying The coherency guarantee between the cache memory and the copy destination area cache memory can be performed very efficiently. Uninaru.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below.

FIG. 1 shows the configuration of a computer system according to this embodiment.

As shown in the figure, the computer system according to this embodiment has a general computer system configuration, and includes a plurality of processors 1, an input / output unit 25, a display 26, a network adapter 27, a hard disk 28, and the like. It has peripheral devices such as a CD-ROM 29, a transmission system 22 such as a bus and a switch matrix, a memory controller 3 and a main memory 4. Transmission system 22
Is a plurality of processors, a memory control unit 3,
The input / output units 25 are interconnected. Further, each peripheral device 26 to 29 is connected to the input / output unit 25,
The main memory 4 is connected to the memory controller 3.

In such a configuration, the memory controller 3 controls access to the main memory 4 in accordance with the instructions sent from the processor 1 and the peripheral devices 26 to 29.

It should be noted that the transmission system 22 may be a bus or other forms such as a switch matrix. In FIG. 1, the transmission system between the processor 1 and the memory controller 3 and the transmission system between the input / output unit 25 and the memory controller 3 are shown as common, but the input / output unit 26 is directly connected to the memory controller 3. And so on
Other connection forms may be used.

Next, FIG. 2 shows the internal structure of the memory controller 3.

Here, as the peripheral devices 26 to 29 of FIG. 1, an external storage device 6 such as a hard disk and other peripheral devices 7 are provided, and the input / output unit 25 of FIG. 1 is the external bus controller 5 and the transmission system. The case where 22 is a bus is shown as an example.

Now, the memory controller unit 3 is
A bus control unit 8 for controlling data transfer between the processor 1 and the external bus controller 5, and an instruction input processing unit 9 for fetching an access command from the processor 1, external storage device 6 or the like to the main memory 4 into the memory controller. An address translation unit 10 that translates between a logical address of an access target designated by an access instruction from the processor 1 or the peripheral device 7 and a physical address in the main memory 4, and a main memory 4 read from the main memory 4 or A data buffer 11 for temporarily storing data to be written in, a memory input / output control unit 12 for controlling input / output of data to / from the main memory 4, and a data copy control unit 13.

The data copy control unit 13 receives the data copy (data copy) command of the data in the main memory 4 from the processor 1, the peripheral device 7, etc., and stores the copy source address designated by the command. Register (Source-Pa
ge) 14, a DT register (Destination -Page) 15 for storing a copy destination address specified by an instruction, and a page size determined based on a swap size unit of temporary storage data between the main storage 4 and the external storage device 6. Is provided with a page register (PageSize) 16 and a status register (StatusReg) 17 for holding the status of the data copy processing.

Next, the storage hierarchy will be shown in FIG.

The storage hierarchy of a typical computer system is composed of multiple levels. Data transfer between layers is performed only between two adjacent layers. Usually, a layer closer to the processor is called an upper level, and a layer further away is called a lower level. The upper level memory has a smaller storage capacity and is faster than the lower level memory. A fixed-length minimum unit of data transfer between both levels is called a normal block, and transfer is performed in this unit. The fact that the data requested from the processor or the like to the memory exists in any of the blocks stored in the highest level hierarchy is called a hit, and the data that does not exist is called a miss. In the case of a hit, the data is directly read from the highest level hierarchy, but in the case of a miss, the storage hierarchy one step lower is searched to obtain the requested data. Therefore, in the case of a miss, the processing speed decreases due to the decrease in access speed and the data transfer between layers.

The operation of the memory controller 3 according to this embodiment will be described below.

Here, in FIG. 4, the memory controller 3
The flow of information within is shown below.

In the figure, the processor 1 and peripheral devices 7 are shown.
The instruction input unit 9 fetches the access instruction of the main memory 4 issued on the bus from the above and the logical address to be accessed. If the access instruction is a store instruction,
The data targeted by the instruction output on the bus is fetched into the data buffer 11.

When the access instruction fetched by the instruction input unit 9 is a normal load / store instruction, the logical address to be accessed is converted into a physical address through the address conversion unit 10, and the memory input / output control unit together with the instruction is converted. 1
Pass to 2. When the instruction is a store instruction, the memory input / output control unit 12 writes the data targeted by the store instruction fetched in the data buffer 11 to the converted physical address of the main memory 4. In the case of a load instruction, the memory input / output control unit 12 reads data from the converted physical address of the main memory 4 and stores it in the data buffer 11. The stored data to be loaded is then transferred to the bus control unit 4
2 to send to the bus.

On the other hand, when the access command fetched by the command input unit 9 is a data copy command, the following processing is performed.

First, the command input unit 9 transfers the data copy command and the logical addresses of the copy source and the copy destination to the data copy control unit 13. The data copy control unit 13 issues a read / write request for realizing the data copy from the copy source to the copy destination, and realizes the data copy in the main memory 4 by using the data buffer 11. Specifically, it is assumed that data is copied in page units,
If the copy source logical address and the copy destination logical address of the data copy instruction are specified by the page,
The data copy control unit 13 first stores the page address of the copy source in the SP register 14 and the page address of the copy destination in the DT register 14. Then, the page address of the copy source is sent to the address conversion unit 10 and converted into a physical address. Further, the page address of the copy destination is sent to the address conversion unit 10 and converted into a physical address.
Then, the data copy control unit 13 internally performs the data copy between the pages on a block-by-block basis, so that the copy source to which the data copy is to be performed from the converted physical address of the copy source page and the physical address of the copy destination page. A set of a block physical address and a copy destination block physical address is sequentially generated. That is, the physical addresses of the two blocks at the same position in the copy source page and the copy destination page are set as the physical address of the copy source block for the copy source page and the physical address of the copy destination block for the copy destination page. Generate sequentially. Then, the data copy control unit 13 determines, via the memory input / output control unit 12, the physical address of the copy source block of the main memory for each set of the physical address of the copy source block and the physical address of the copy destination block that are sequentially generated. A process of reading data, writing to the data buffer 11, and writing the data read from the physical address of the copy source block of the main memory 4 to the data buffer 11 to the physical address of the copy destination block of the main memory is sequentially performed in block units. However, as described later, when copying data,
When the block of the copy source page is read in the cache of the processor 1 or the peripheral device 7 and is rewritten in the cache, this block is copied from the copy source block in the main memory 4. Data is copied to the copy destination block, and the block written back from the cache is written to both the copy source block and the copy destination block.

In the data copy operation of the memory controller unit 3 as described above, in the case where the processor 1 or the peripheral device 7 has a cache memory, in order to guarantee the consistency between the cache and the main memory 4, Coherent control of is required.

The coherent control performed by the memory controller 3 will be described below.

FIG. 5 shows the configuration of the data copy control unit 13, which is the center of this coherent control.

As shown, the data copy controller 13
Includes the SP register 14, the DT register 15, the page size register 16 and the status register 17 described above. Further, it further comprises a copy controller 52 and a block address controller 51.

In order to realize coherent control, the first
In addition, the data copy control unit 13 prohibits access to the main memory 4 of the processor 1 and the peripheral device 7 during data copy.

That is, as shown in FIG. 6, when the copy control unit 52 of the data copy control unit 13 receives the data copy command from the command input unit 9, it sets a value indicating the copying status in the status register 17. The data copy described above is held until the write back of a dirty block described later is completed. When the value indicating the copying status is set in the status register 17, the instruction input unit 9
Is a memory load from the processor 1, peripheral device 7, etc.
When a store / data copy instruction is output to the bus 41, a Wait request is output to the bus 41 in response to the instruction. In addition, when the instruction input unit 9 completes the data copy and the write-back of the dirty block described later, and the value indicating the copy waiting state is set in the status register 17,
The it cancellation request is sent to the bus 42.

On the other hand, in the processor 1 to which the Wait request is responded to the issued instruction, the peripheral device 7 reissues the instruction to which the Wait request is responded when the Wait cancellation request is issued. After sending the Wait cancellation request to the bus 42, the command input unit 9 fetches commands until the value indicating the copying status is set in the status register 17, and processes the commands as described above.

Second, when the block of the copy destination page before being rewritten by the data copy process is read in the cache of the processor 1 or the peripheral device 7, the data copy control unit 13 determines that this is the processor 1 or the peripheral device. 7
Invali to prevent it from being used by
A process of issuing a cache block invalidation request of the copy destination page indicated as date to the bus 41 is performed.

That is, when the page address is set in the DP register 15, the block address generator 51 of the data copy controller 13 generates the physical address of the copy destination block as described above. The copy control unit 52
Prior to the data copy processing, an invalidation request for the block of the generated physical address is sent to the bus 41. Receiving this, each processor 1 and the peripheral device 7 invalidate this cache block when it is read in its own cache.

Third, the data copy control unit 13 reads the block of the copy source page into the cache of the processor 1 and the peripheral device 7 at the time of data copy,
Further, when this is rewritten in the cache, the rewriting request shown as Clean in FIG. 7 is issued to the bus 41 so that the rewritten data is reflected in the copy destination page, and as described above. , Write back the written data to both the copy source and copy destination pages.

As shown in FIG. 8, this process is performed as a part of the data copy process after the data copy command is issued and the transmission of the above-mentioned invalidation request of the host is completed.

FIG. 9 shows the processing procedure of this data copy processing.

As shown in the figure, in this processing, the copy controller 52 sends a write back (Clean) request for the copy source block in which the physical address is generated to the bus 41 (step 92). Receiving this, each processor 1, peripheral device 7
Sends the Modified signal and the data of the block in the cache to the memory control unit 3 when this cache block is read in its own cache and is rewritten in the cache (DIrty). , Request a writeback.

When the Modified signal is received, the copy control unit 52 stores the data of the block requested to be written back in the physical address of the generated copy source block and the physical address of the copy destination block in the main memory 4 in the memory. Writing is performed via the input / output control unit 12 (step 94).

On the other hand, if the Modified signal is not received, the data is copied from the physical address of the copy source block generated in the main memory 4 to the physical address of the copy destination block as described above.

Finally, the status register 17
Then, a value indicating the copy waiting state is set in, and the process ends.

The embodiment of the present invention has been described above.

As described above, according to the present embodiment, it is possible to reduce the load on the request source when the data copy request source copies a large amount of data between pages of the main memory, and the cache is used in the multiprocessor system. It is possible to reduce the number of times data is written back by cache coherency control when there is a processor or peripheral device with
Since the bus usage rate can be reduced, the processing speed can be improved.

Specifically, FIG. 10 shows the result of evaluation of the processing capacity of data copying by the conventional computer system and this embodiment.

Here, the page size (P) = 16 KB
yte, cache line size (C) = 64 Byte
e, the memory load latency (l) = 30, the memory store latency (s) = 10, the main memory access latency (m) from the memory controller was set to 7, and the dirty rate (d) was set. When the data copy of one page is executed in the conventional system, the total latency (LO) is LO = l · (P / C) · (1-d) + s · (P / C). Further, the total latency (LN) when the data copy according to the present invention is executed can be expressed by the following equation since there is no memory load latency.

LN = (m. (P / C)). (1+ (1-
d)) + s · (P / C) · d FIG. 10 shows the processing capacity ratio when the dirty rate is changed from 0 to 100% in the above equation.

The dirty rate varies depending on the operating system of the computer system and application software, but is generally about 10 to 30%. The processing capacity according to this embodiment in this range can obtain 2.5 to 3.5 times the performance of the conventional computer system. Further, if the bus utilization rate is also added to the above result, the conventional computer system uses the bus at the time of loading and storing, so that the capacity difference becomes larger than the above result.

[0052]

As described above, according to the present invention, it is possible to provide a computer system capable of more efficiently copying and moving a large amount of data in the main memory. Also, especially in multiprocessor systems,
It is possible to realize data coherence control without further deteriorating the efficiency of copying or moving data in a large amount of main memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a memory controller according to the embodiment of the present invention.

FIG. 3 is a diagram showing a general storage hierarchy of a computer system.

FIG. 4 is a block diagram showing a configuration of a memory controller according to the embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a data copy control unit according to the embodiment of the present invention.

FIG. 6 is a diagram showing how a wait request is issued by coherent control according to the embodiment of the present invention.

FIG. 7 is a diagram showing how an invalidation request / writeback request is issued by coherent control according to an embodiment of the present invention.

FIG. 8 is a state transition diagram showing transition of processing of coherent control in the embodiment of the present invention.

FIG. 9 is a flowchart showing a processing procedure of data copy processing according to the embodiment of the present invention.

FIG. 10 is a graph showing data copy performance of the computer system according to the embodiment of the present invention.

[Explanation of symbols] 1 ... Processor 2 ... bus 3 ... Memory controller 4 ... Main memory 5 ... External bus controller 6 ... External storage device 7 ... Peripheral device 8: Bus control unit 9: Command input section 10 ... Address conversion unit 11 ... Data buffer 12 ... Memory input / output control unit 13 ... Data copy control unit 14, 15, 16, 17 ... Register

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-55459 (JP, A) JP-A-52-129241 (JP, A) JP-A-7-253924 (JP, A) JP-A-3- 158943 (JP, A) JP-A-3-37744 (JP, A) JP-A-2-271443 (JP, A) JP-A-2-141846 (JP, A) JP-A-63-155342 (JP, A) JP 62-256147 (JP, A) International Publication 98/12639 (WO, A1) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 12/08-12/12 G06F 12/00 550 -12/06 G06F 13/16-13/18 G06F 9/30-9/355

Claims (4)

(57) [Claims] 1. A computer system, comprising: a memory controller for controlling access to a main memory of at least a plurality of processors having a cache memory, wherein a data copy between areas of the main memory issued by the processor is performed. A means for accepting the requested data copy command together with the specification of the copy source area and the copy destination area for performing the data copy, a means for storing the specification of the accepted copy source area and the specification of the accepted copy destination area, and a specification A cache memory area that has read the stored data in the copy source area of the main memory, and the data in that area has been updated in the cache memory and does not match the data in the copy source area of the main memory. Issue a write-back request to the processor requesting write-back of the data in the area And a means for writing the data sent from the processor in response to the issued write-back request to both the copy source area and the copy destination area of the main memory storing the designation. controller. 2. The memory controller according to claim 1, wherein the data in the copy source area of the main memory storing the designation is read, and the data in the area is updated in the cache memory. When there is no cache memory area that does not match the data in the main memory copy source area, from the main memory copy source area that stores the designation to the main memory copy destination area that stores the designation, A memory controller having means for copying data. A 3. A memory controller according to claim 1 or 2, wherein, a main memory to which access is controlled by the controller, and a plurality of processors issuing said data copy instruction includes a cache memory, wherein each processor Is a region of the cache memory in which the memory controller reads the data of the copy source region of the main memory storing the designation in response to the write-back command issued by the memory controller, and the data of the region is cached. A computer system comprising means for sending to the memory controller the data in the area of the cache memory that has been updated on the memory and does not match the data in the copy source area of the main memory. 4. A computer system including a main memory and a plurality of processors having a cache memory,
A method of writing back data from the cache memory to the main memory, wherein when copying data between areas in the main memory, the area of the cache memory that has read the data of the copy source area of the main memory, The data in the cache memory area where the data is updated in the cache memory and does not match the data in the main memory copy source area is read, and the read data is stored in both the main memory copy source area and copy destination area. A method of writing back cache data, which is characterized by writing.