JPH0512754B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention stores image information such as documents in a storage device, and extracts required image information from among various image information stored in the storage device as needed. The present invention relates to an image display device of an image information storage and retrieval device that searches for and reads out the information, and outputs it in a visible state.

[Technical background of the invention and its problems] Recently, image information such as documents generated in large quantities is read by optical two-dimensional scanning, and the read image information is stored in a storage device such as an optical disk device. In addition, there is an image information storage and retrieval device that searches and reads required image information from among the various image information stored in this storage device as needed, and outputs it in a state that can be visually viewed on a hard copy device. developed and put into practical use.

In such an image information storage and retrieval device, in order to deal with the difference between reading speed and storage speed or the difference between reading speed and storage speed, image information of one unit (one page) that has been read or read One unit of image information is temporarily stored in a page buffer memory. It is also equipped with an image information display device consisting of a display interface, a CRT display, etc., and is capable of displaying image information in the page buffer memory on a monitor.

By the way, as shown in Figure 1, the page buffer memory has a storage area of 2048 bits x 2800 lines, while the refresh memory in the display interface has a storage area of 1024 bits x 700 lines.
There is only a line storage area, so all the image information in the page buffer memory is stored on the CRT at once.
It is impossible to display it on the display.

Therefore, in the past, a size conversion circuit was provided in the display interface to reduce the image information read from the page buffer memory to 1/4 and store it in the refresh memory, as shown in Fig. 2. All the image information in the page buffer memory was displayed on the CRT display at once.

However, in this case, the reduction ratio is constant regardless of the size of the image information, so the size of the image information displayed on the CRT display varies, and the disadvantage is that the display area on the CRT display is not used effectively. It was hot.

[Object of the Invention] This invention was made in view of the above-mentioned circumstances, and its object is to be able to change the size of an image so that it can be displayed in the entire display area of a display unit, An object of the present invention is to provide an excellent image display device that can effectively utilize the display area of a display section.

[Summary of the Invention] The present invention converts image information retrieved and output from an optical storage means and stored in a page memory by a size conversion means and stores it in a refresh memory, and displays the image information in the refresh memory. By setting the conversion rate of the size conversion means by the control means, regardless of the size of the document stored in the optical storage means, the image information can be displayed at a constant size and the entire display area of the display means can be displayed. It should be displayed as fully as possible.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In Figures 3 and 4, 1
is the main control device, and CPU2, which performs various controls,
A management information storage device that stores management information for managing various file sets (a collection of optical disks to be described later) and various files (optical disks), such as a floppy disk device 3 and an optical disk device 9 to be described later. A title memory 4 for temporarily storing title information, a page buffer memory 5 having a storage area (2048 bits x 2800 lines) corresponding to at least one unit of image information (one page of the manuscript), and a page buffer memory 5 for storing characters, symbols, etc. It consists of a pattern generator 6 and the like in which pattern information is stored. Reference numeral 7 denotes a reading device, such as a two-dimensional scanning device, which scans an original (document) 8 two-dimensionally to obtain a video signal corresponding to image information on the original 8. Reference numeral 9 denotes an optical disk device, which is a large-capacity storage device, which sequentially stores image information read by the two-dimensional scanning device and image information created by the main controller 1 in a storage medium, that is, a dedicated storage area of the optical disk. It is something to do. A keyboard 10 is used to input a unique title and various operation commands corresponding to the image information. A hard copy device 11 is an output device, and outputs image information read by the two-dimensional scanning device 7 or image information read from the optical disk device 9 as a hard copy 12. Reference numeral 13 denotes an image display device which is an output device, and includes a size conversion circuit 14, a display interface 15, a cathode ray tube display device (hereinafter referred to as CRT display) 16, etc., and displays image information read by the two-dimensional scanning device 7. Alternatively, image information read from the optical disk device 9 is displayed.

Thus, a floppy disk device 3, a title memory 4, a page buffer memory 5, a pattern generator 6, a two-dimensional scanning device 7, an optical disk device 9, a keyboard 10, a hard copy device 1
1. The size conversion circuit 14 and display interface 15 are each connected to a data bus 20 from the CPU 2. Further, the title memory 4, page buffer memory 5, pattern generator 6, two-dimensional scanning device 7, optical disk device 9, hard copy device 11, size conversion circuit 14, and display interface 15 are each connected to the image bus 21. and information is now being transferred to each other.

Here, FIG. 5 specifically shows the two-dimensional scanning device 7. As shown in FIG. That is, 31 is a paper feed tray, and a document set on this tray 31 is taken into the main body by take-in rollers 32, 32, and is further transferred to a document table (glass plate) 34 by conveyance rollers 33, 33. fed to the top. The original that has passed through the original platen 34 is transferred to the paper ejection tray 3 by transport rollers 35, 35 and ejection rollers 36, 36.
7 is discharged on top. A pair of exposure lamps 38, 38 are provided at positions corresponding to the document table 34, and the light emitted from these lamps 38, 38 is irradiated onto the document being conveyed, and the reflected light is reflected by a mirror 39. and CCD via projection lens 40
It is projected onto the line sensor 41. In this way, a video signal corresponding to the image information on the document can be obtained from the line sensor 41. In addition, a photocoupler consisting of a light emitting diode 42 and a phototransistor 43 for detecting the document being captured is provided near the capture rollers 32, 32, and a photocoupler for detecting the size of the document being captured. light emitting diodes 44a, 44b,
44c, 44d and phototransistor 45
A photocoupler consisting of a, 45b, 44c, and 44d is provided.

6a and 6b show the structure and operation of an operation control circuit based on the output of the phototransistor 43. FIG. That is, phototransistor 4
The output of timer 3 is sent to the first timer 4 via an inverter 45.
6, the second timer 47 and the third timer 48 are supplied. Since the leading edge of the document has been detected, the first timer 46 outputs a drive signal for operating the rollers and lamps 38, 38 for a certain period of time. The second timer 47 outputs a reading start signal for operating the line sensor 41 a predetermined time after the leading edge of the document is detected. Third timer 48
is adapted to output a reading end signal for stopping the operation of the line sensor 41 after a predetermined time after the leading edge of the document is detected.

Further, FIGS. 7a and 7b show the arrangement of the phototransistors 45a, 45b, 45c, and 45d and the configuration of a size detection circuit based on their outputs. That is, each light emitting diode and its corresponding phototransistor 45a, 45b, 45c, 4
5d are arranged at regular intervals, and the output of each phototransistor differs depending on the size of the document input with reference to the side edge on the conveyance path. A ₃ detection signals, B ₄ detection signals, A ₄ detection signals, respectively.
B ₅ detection signals are obtained.

Here, we will briefly explain what kind of operation is performed in the above configuration.

When a document 8 is set on the two-dimensional scanning device 7, image information on the document 8 is read and sequentially stored in the page buffer memory 5. At this time,
The document size detected by the two-dimensional scanning device 7 is
The data is supplied to the CPU 2 and stored in the RAM within the CPU 2. When one unit of image information is stored in the page buffer memory 5, the CPU 2 reads the size conversion rate (reduction rate) corresponding to the detected document size from the ROM, and sends it to the size conversion circuit 14. Set. In this way, the image information in the page buffer memory 5 is reduced to a predetermined size by the size conversion circuit 14, and the display interface 1
5 is stored in the refresh memory. Then, the image information in the refresh memory is
It is displayed on the CRT display 16.

Further, when image information is read from the optical disk device 9, the read image information is sequentially stored in the page buffer memory 5. At this time, document size information previously included in the index information corresponding to the read image information is supplied to the CPU 2 and stored in the RAM within the CPU 2. When one unit of image information is stored in the page buffer memory 5, the size conversion rate (reduction rate) corresponding to the original size information stored in the CPU 2 is calculated.
The data is read from the ROM and set in the size conversion circuit 14. In this way, the image information in the page buffer memory 5 is reduced to a predetermined size by the size conversion circuit 14 and stored in the refresh memory in the display interface 15. The image information in the refresh memory is then displayed on the CRT display 16.

Next, the above-mentioned size conversion circuit 14 and display interface 15 will be explained in detail. First, FIG. 8 shows the size conversion circuit 14. That is, one line of image information in the page buffer memory 5 is supplied to the data input terminal 400. In this case, one line of image information consists of 2048 bits. The image information supplied to the terminal 400 is
It is supplied to RAM 401 and a 6-bit latch circuit 406. RAM 401 is 2K×1 bit, and its address is designated by the output of counter 413. However, 5 RAM401 ~
405 and seven latch circuits 406-412 are provided. These RAMs 401-405 and latch circuits 406-412 are all operated by a clock signal supplied from a main clock generator 414 via a signal path shown by solid lines or a signal path shown by two-dot chain lines. In this case, the signal path indicated by the solid line is used when the circuit functions as a reduction circuit, and the signal path indicated by the two-dot chain line is used when the circuit functions as an expansion circuit.

Under address control of counter 413,
The image information of the first line of 2048 bits is the first
It is stored in RAM401. Then, when the first bit of the second line of image information is provided to RAM 401, the first bit of the first line of image information stored in RAM 401 is read therefrom and latched in latch circuit 406. Meanwhile, the first bit of the second line is stored in the first memory location of RAM 401. The second bit of the second line is then stored in RAM 401 and the second bit of the first line is read therefrom and latched into latch circuit 406. At the same time, the first line of the first line latched by the latch circuit 406
The bits are read into RAM 402 and stored there. In this way, when the last (2048th) bit of the second line is stored in the RAM, the first line of image information of 2048 bits is shifted to the RAM 402. Therefore, each line of 2048-bit image information is sequentially shifted in the RAMs 401-405. Finally, the image information of the first to fifth lines are stored in the RAMs 405 to 401, respectively, and the first bit of the image information of each of the first to fifth lines is latched in the latch circuit 406 and simultaneously supplied to the terminal 400. The first bit of the sixth line image information is supplied to latch circuit 407.

When the second bit of the sixth line is supplied to the terminal 400, the first bit of each of the first to sixth lines latched by the latch circuit 407 is supplied to the next latch circuit 408, The second bit of each of the six lines is latched into latch circuit 407. Similarly, when the seventh bit of the image information of the sixth line is supplied to the terminal 400, each of the first to sixth bits
The first bit of the line is latched by latch 412, the second bit is latched by latch 411, the third bit is latched by latch 410, the fourth bit is latched by latch 409, and the fifth bit is latched by latch 409. is latched in latch circuit 408, and the sixth bit is latched in latch circuit 407. Therefore, the latch circuits 407-41
When each bit latched at 2 is rearranged into the matrix array, the original image is reproduced as a dot image as shown in FIG. In FIG. 9, black dots represent 1 bit and white dots represent 0 bits. Therefore, 6 bits (X
(direction)×6 lines (Y direction) local image information is supplied from latch circuits 405 to 412 to arithmetic ROM 415.

Two adders 416 and 417, two latch circuits 418 and 419, a comparator 420, and a counter 413 constitute a distance calculation circuit 430 in the X direction, and two adders 421 and 422 and two latches The circuits 423 and 424, the comparator 425, and the counter 426 constitute a distance calculation circuit 431 in the Y direction. These distance calculation circuits 430 and 431 are used to calculate the positions of image dots whose size has been converted in the X and Y directions. The size conversion (enlargement, reduction) rate setting data in the X and Y directions supplied from the CPU 2 is sent to the adders 416 and 41.
7,421 and 422. In FIG. 8, reduction rate data is shown as an example. The integer part of the reduction ratio is supplied to adders 416 and 421 and decoder 427, and the fractional part is supplied to adders 417 and 422. Adder 41
The outputs of 6, 417, 421, and 422 are supplied to latch circuits 418, 419, 423, and 424, respectively. The outputs of latch circuits 418 and 423 are supplied to the negative input sides of comparators 420 and 425, respectively, and fed back to the input sides of adders 416 and 421. The other side of comparators 420, 425 has inputs from counters 413, 426. The outputs of latch circuits 419 and 424 are fed back to the input sides of adders 417 and 422, respectively.

The upper three bits of the decimal part output data of the circuit 430 and the upper three bits of the decimal part output data of the circuit 431 are taken out from the respective latch circuits 419 and 424, and are sent to the arithmetic ROM 4 as an address designation signal.
15. This ROM 415 stores the pixel level before reduction. This operation
Output data read from the ROM 415 is supplied to the input side of a comparator 432, and the other end of the comparator 432 is supplied with slice level data obtained from a slice level data oscillator 433. The match signal of comparator 432 is output from D of flip-flop 434.
The output of AND gate 435 is applied to the flip-flop's clock terminal CL. One input terminal of the AND gate 435 is supplied with the coincidence output XCOM of the comparator 420, and the other input terminal is supplied with the input YCOM from the comparator 425.
is supplied.

Here, the operation of such size conversion circuit 14 will be explained in detail with reference to FIG. 10. Assume that the reduction rate specified by CPU2 is 1/4.5. In this case, the integer part of the reduction ratio is 4, while the decimal part is 0.5. Digitally formed numerical data are sent to adders 416, 417 and 42, respectively.
It is set to 1,422.

In FIG. 10, the image dot positions of the original image are designated by the symbol "X", while the image dot positions of the size-converted image are designated by black dots. The image dot at position (i, j) on the original image is defined by {P _i,j }.

{P _i,j }=1...Black bit 0...White bit The image at position (I, J) on the reduced image is defined by {Q _I,J }.

The distance between two adjacent image dots of the original image is defined as one. Then, the distance between the two reduced dots on the original image is equal to the reduction rate R _r .

L=R _r In this case, the constant L is set as 4.5. When an L×L region with center position Q _I,J is designated as S, the average gray level of S is calculated based on the fact whether an image dot {P _i,j } belonging to region S exists or not. be done. If we define the distance between the original position P _i,j and the transformed position Q _I,J as r _i,j , then the weighting factor α i, _{j for calculating the average gray level φ I, J} is given by the distance r _i,j. determined to be inversely proportional. Therefore, if we set the factor α _i,j as 1 at the position of Q _I,J and 0.5 at the position L/2 away, then the factor α _i,j
can be expressed as α _i,j =1−0.5/L/2r _i,j =1−r _i,j /L.

Therefore, the average gray level φ _I,J is φ _I,J =Σα _i,j ·P _i,j /Σα _I,J (P _i,j ←S). Then, the transformed image dots Q _I,J are obtained by using a predetermined slice level θ, with Q _I,J =1...φ _I,J >θ 0...φ _I,J <θ.

Therefore, the integer part 4 of the reduction ratio supplied from the CPU 2 is passed through the adder 416 to the latch circuit 41.
8. When the contents of counter 413 reach 4, a match signal XCOM is sent out from comparator 420 and provided to latch circuits 418, 419 and AND gate 435. On the other hand, the decimal part 0.5 is latched by a latch circuit 419 via an adder 417. Therefore, when the signal XCOM is supplied to latch circuits 418 and 419, an operation of 0.5+0.5=1 is performed in adder 417, and a carry of 1 is supplied to adder 416. Therefore, 4+4+1=
An operation of 9 is performed in adder 416, and new data "9" is set in latch circuit 418. At this time, when the content of the counter 413 becomes 9, the output
XCOM is obtained at the output of comparator 420. Then, 9+4=13 is set in latch circuit 418. Output XCOM is obtained when counter 413 reaches 13. At this time, an operation of 13+4+1 is performed in adder 416, and new data "18" is set in latch circuit 418.

In this way, the contents of the counter 413 become “4, 9,
Output every time 13, 18, 22, 27, ...”
XCOM is output from comparator 420. This output XCOM is provided to one input of AND gate 435.

The same operation as circuit 430 is performed by circuit 431.
It is also carried out at Output YCOM is counter 42
Every time the content of 6 becomes "4, 9, 13, 18, 22, 27, ...", the AND gate 435 is sent from the comparator 425.
is supplied to the other input of Input XCOM and YCOM
are provided to AND gate 435, the output is provided to the clock terminal of flip-flop 434. At this time, when the output level φ _I,J exceeds the output level of the slice level generator 433, the output is supplied from the comparator 432 to the D terminal of the flip-flop 434, and the black dot output Q _{I,J is output as shown in FIG. J} is obtained from flip-flop 434.

In the magnification operation, for example, a magnification rate of 0.5 is
Adders 416, 417, 421, 4 from CPU2
22. In this case, the number of Q _I,J is twice the number of P _i,j and the image information is expanded twice.

Next, FIG. 11 shows the display interface 15.
This is what is shown. 60 is refresh memory, 1024 bits (X direction) x 1400 lines (Y direction)
It has a storage area of . (CRT display 1
6 has a display area of 1024 bits x 700 lines). 61 is a 16-bit register that stores the image information reduced and supplied by the size conversion circuit 14.
The data is supplied to the refresh memory 60 every 16 bits. 62 is a selector that selects the output of the 16-bit register 61 or the pattern generator 6.
This selects pattern information from .
A write address counter 63 temporarily holds the image information write start address supplied from the CPU 2, divides the frequency of the size conversion circuit 14 (clock from the flip-flop 434 shown in FIG. and AND circuit 65
The X-direction and Y-direction addresses of the refresh memory 60 are designated by counting up in response to a clock signal supplied via the clock signal. In addition, this write address counter 6
3, when writing of image information is completed, a pattern information writing address corresponding to a specific area at the lower right end of the refresh memory 60 in the drawing is supplied from the CPU 2. In this case, a "0" signal is supplied from the CPU 2 to the other input terminal of the AND circuit 65, so that no clock signal is supplied to the write address counter 63. 66 is a CRT controller, which is composed of a counter 67, an address register 68, a 700 line detection circuit 69, etc., and is used when reading image information from the refresh memory 60.
Addressing is performed in the X and Y directions of the refresh memory 60. Here, the counter 67 includes a 1/64 counter 67a that counts a clock signal supplied from an oscillation circuit 70 via a 1/16 counter 71, and a 1/64 counter 67a that counts a clock signal supplied from an oscillation circuit 70 via a 1/16 counter
It consists of a counter 67b for performing a carry count of 7a, and the contents of the counter 67a are used as an X-direction specified address, and the contents of the counter 67b are used as a Y-direction specified address. Further, the address register 68 holds a read start address (line address) supplied from the CPU 2. The 700 line detection circuit 69 detects whether the counter 67b has counted "700" and, if it has counted "700", causes the counter 67b to newly set the start address of the address register 68. be. 72
is a selector which selects either the Y-direction specified address of the address counter 63 or the Y-direction specified address of the counter 67b during writing and reading. A selector 73 selects either the X-direction specified address of the address counter 63 or the X-direction specified address of the counter 67a during writing and reading.
A 16-bit register 74 serially outputs 16-bit image information read from the refresh memory 60 using the output of the oscillation circuit 70 as a clock signal. 80 is a cursor setting circuit,
It generates a cursor video signal corresponding to a predetermined cursor (frame) in synchronization with the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the clock signal from the oscillation circuit 70, which are supplied from the CRT controller 66 to the CRT display 16. be. Therefore, the cursor video signal generated from the cursor setting circuit 80 and the video signal output from the 16-bit register 74 are sent to the OR circuit 200.
The signal is supplied to the CRT display 16 via.

Here, FIG. 12 shows the cursor setting circuit 80. In FIG. 12, reference numeral 81 denotes an X-direction cursor memory, which stores position information on both left and right sides of the cursor in accordance with write code information J from the CPU 2. 82 is a Y-direction cursor memory, which stores write code information J from CPU2.
It holds the position information of the upper and lower sides of the cursor, respectively. 83 is an X-direction address counter which counts the clock signal shown in FIG. 14a (supplied from the oscillation circuit 70 shown in FIG. 11). 84 is a Y-direction address counter, which receives the horizontal synchronization signal Hsync shown in FIG. 14b supplied from the CRT controller 66.
is counted. 85 is a decoder,
When the contents of the counter 83 match the position information on both sides, a logic "1" signal shown in FIG. 14c is output. 86 is a decoder, which outputs a logic "1" as shown in FIG. 14d when the contents of the counter 84 match the position information of the upper and lower sides respectively.
It outputs a signal. 87 and 88 are T-flip-flops, respectively shown in FIG. 14f and g.
The signals shown in are output respectively. 89 is an OR circuit which outputs the signal shown in FIG. 14i. 90
₁ , 90 ₂ and 90 ₃ are AND circuits, among which AND circuits 90 ₁ and 90 ₂ output the signals shown in FIG. 14e and h, respectively. W is the bling signal,
CV is a cursor video signal.

On the other hand, in FIG. 13, 92 is a cursor key provided on the keyboard 10. And 9
3, 94, 95, and 96 are movement keys that emit movement pulses while being pressed. The CPU 2 detects this pulse and moves the image or cursor in the direction of the arrow. 97 is a CRT for image information in the cursor or refresh memory 60
This is a movement key for moving the display area of the display 16 to the upper left corner. 98 is the expansion key, 99
is a reduced key.

In such a configuration, how image information is displayed will be explained.

When the original 8 is set on the two-dimensional scanning device 7,
Image information on the document is read and the size of the document is detected. The read image information is stored in the page buffer memory 5 with a size corresponding to each size as shown in FIG.
is memorized. At this time, if the document size is _B4 , the CPU 2 sets the reduction rate of the size conversion circuit 14 to 1/4. If A ₄ , the reduction rate is 1/3.3,
For B ₅ , the reduction ratio is set to 1/2.7, and for A ₅ , the reduction ratio is set to 1/2. In this way, the image information in the page buffer 5 is reduced by the size conversion circuit 14 and stored in the refresh memory 60. When image information is stored in the refresh memory 60,
The CPU 2 reads a character pattern corresponding to the original size of the image information from the pattern generator 6, and adds it to a specific area of the image information in the refresh memory 60. Therefore, as shown in FIG.
The information is displayed on the CRT display 16, and the display area of the CRT display 16 is utilized to the maximum extent possible. Moreover, in this case, the document size is added to the lower right part of the displayed image information, so
The original size of each image information can be easily recognized. Note that if the page buffer memory 5, refresh memory 60, and original document 8 are used in a landscape orientation, the image information will be as shown in FIGS.
As shown in FIG. 2, the image is displayed over the entire display area of the CRT display 16, and the display area can be used more effectively.

By the way, when such image information is displayed in its entirety, the reduction ratio for the image information is reduced to a certain extent, so there is a problem in terms of resolution.

Therefore, by operating the cursor keys 92 of the keyboard 10, the displayed image and cursor are moved to the desired position, and in this state, the desired image is specified with the cursor, and the specified image is enlarged. It is now possible to display
In this case, the CPU 2 performs control according to the flowchart shown in FIG. In CPU2, first of all,
Address register 68 of CRT controller 66
Set "1" to "1", read the 1st line to 700th line of the refresh memory 60, and
Display it on the CRT display 16 (step S1). That is, as shown in FIG. 19a, image information of the upper half area (solid line in the figure) of the refresh memory 60 is displayed. Further, the CPU 2 sets the address of the cursor S in the cursor setting circuit 80 as shown by the dashed line in FIG. In this state, when the movement key 96 of the cursor key 92 is turned on (steps S2, S3, S4,
S5), the CPU 2 increments the contents of the address register 68 of the CRT controller 66 by, for example, +10 (step S6). In this way, each time the movement key 96 is turned on, the display area for image information in the refresh memory 60 sequentially moves downward as shown in FIGS. 19b and 19c. In this case, the display area and cursor S
There is no change in the corresponding position. After that, when the Y direction start address reaches “700” (step
S5), the CPU 2 rewrites the Y-direction address of the cursor S in the cursor setting circuit 80 every time the cursor key 96 is turned on (step S7).
In this way, each time the movement key 96 is turned on, the 19th
The cursor S moves downward as shown in Figures d and e.

When the movement key 93 is turned on from this state (steps S2, S3, S4, S8, S9),
The display area moves upward as shown in d and c, and then the cursor S moves upward as shown in FIG. 20b and a (step S10). Moreover, if the movement key 95 is turned on in the state shown in FIG. 21a, (step S2,
S3), since there is no movement range in the display area, the cursor S moves to the right and becomes the state shown in FIG. 21b (step S11). Furthermore, if the movement key 94 is turned on in the state shown in FIG. 22a (steps S2, S3), only the cursor S moves to the left, resulting in the state shown in FIG. 22b (step S11). If the enlargement key 98 is turned on in such a display state, the image information within the cursor S is enlarged and newly displayed. Moreover, if the reduction key 99 is turned on, the original display is made.

In this way, by specifying movement of a certain area for the image information in the refresh memory 60, the image information within that certain area can be displayed immediately. This eliminates the need for reading data from the image data, resulting in a significant improvement in display speed. Furthermore, by performing the display based on the movement specification, the reduction rate for the image information only needs to match the storage capacity of the refresh memory 60. In other words, the reduction rate can be made larger than when matching the display capacity of the CRT display. This results in higher resolution and easier recognition. Moreover, since the designation of movement of a certain area is given priority over the designation of movement of a zoom-up area, a single operating mechanism can perform operations for each movement designation, which is very convenient in practice.

In the above embodiment, priority is given to specifying movement of a certain area, but priority may be given to specifying movement of the cursor. In addition, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without changing the gist.

[Effects of the Invention] As described above, according to the present invention, the size of the image can be changed so that the image can be displayed in the entire display area of the display unit, and the display area of the display unit can be used effectively. It is possible to provide an excellent image display device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a storage area of a page buffer memory, FIG. 2 is a diagram showing an example of a display state of image information in FIG. 1, and FIG. 3 is a diagram showing an image information storage search according to an embodiment of the present invention. FIG. 4 is a detailed configuration diagram of FIG. 3, FIG. 5 is a detailed configuration diagram of the two-dimensional scanning device, and FIG. 6 a,
b shows the operation control section in FIG. 5, a is a circuit diagram, b is a time chart, FIG. 7 is a size detection section in FIG. 5, and a is a plane view. FIG. 8 is a configuration diagram specifically showing a size conversion circuit in an embodiment of the present invention, and FIGS. 9 and 10 are for explaining the operation of FIG. 8. , FIG. 11 is a block diagram specifically showing the display interface in an embodiment of the invention, FIG. 12 is a block diagram specifically showing the cursor setting circuit in FIG. 11, and FIG. 13 is a block diagram specifically showing the cursor setting circuit in FIG. FIG. 14 is a time chart for explaining the operation of FIG. 12. FIG. 15 is a configuration diagram showing the correspondence between page buffer memory and image information of various sizes stored therein. Figures 16a, b, c, and d and Figures 17a, b, c, and d show the overall display state of image information in an embodiment of the present invention, and Figure 18 shows display control in the same embodiment. Flow chart, Figure 19 a, b,
c, d, e, Fig. 20 a, b, c, d, e, 2nd
FIGS. 1A and 1B and FIGS. 22A and 22B are diagrams showing examples of image information and cursor display in the same embodiment. 2...CPU, 5...Page buffer memory,
6... Pattern generator, 13... Image information display device, 14... Size conversion circuit, 15... Display interface, 16... CRT display, 60... Refresh memory, 80... Cursor setting circuit, 92...Cursor key.

Claims (1)

[Claims] 1. Optical storage means for storing an image and the original size of the image; a page memory for storing an image retrieved from the optical storage means; and a page memory for storing an image retrieved from the optical storage means; a conversion means for converting; a refresh memory for storing an image whose size has been converted by the conversion means; a display means having a display area for displaying the image stored in the refresh memory; The display size of the converted image displayed by the display means is approximately constant regardless of the original size of the image stored in the optical storage means, and covers approximately the entire display area of the display means. The conversion means has a ROM in which size conversion rates corresponding to various original sizes are stored, and the conversion means reads out from the ROM a size conversion rate corresponding to the original size of the image stored in the optical storage means. 1. An image display device comprising: a control means for setting.