JPH021067A - Picture display device - Google Patents

Abstract

PURPOSE:To display a read picture on the whole of the display area of a display part by storing the read picture, after that converting the size of the read picture regardless of the original size of the read picture, storing the size-converted read picture again, and displaying the picture. CONSTITUTION:The picture of an original 8 having various original sizes is read by a two-dimensional scanner 7, and read picture information is stored in the page buffer memory of a main control unit 1. According to designation from a keyboard 10, the CPU of the main control unit 1 outputs the picture information stored in the page buffer memory to a display device 13 and sets the size converting ratio of a size converting circuit 14 so that the whole of the picture to be displayed on a CRT display 16 can be displayed with an approximately fixed size regardless of the original size of the picture read by the scanner 7. The picture size-converted in the converting circuit 14 is stored in a refresh memory in an interface 15 for display, and the picture information in the refresh memory is displayed on the CRT display 16. Thus, the display area can be effectively used.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention stores image information such as documents in a storage device, and extracts required image information from among various image information stored in the storage device as needed. The present invention relates to an image display device of an image information storage and retrieval device that searches for and reads out the information, and outputs it in a visible state.

[Technical background of the invention and its problems] Recently, image information such as documents, etc., which is generated in large quantities, is
The image information is read by dimensional scanning, and the read image information is stored in a storage device such as an optical disk device.
An image information storage and retrieval device has been developed that searches and reads out required image information as needed from among the various types of image information stored in this storage device, and outputs it in a state that can be viewed with a hard copy device. It has been put into practical use.

In such an image tV information storage and retrieval device, in order to deal with the difference between the reading speed and the storage speed or the difference between the reading speed and the storage speed, the image corresponding to one unit of reading (-negative sign) is The information or read image information is temporarily stored in the page/graph memory. In addition, it is equipped with an image information display device consisting of a display interface, CRT display, etc.
The image information in the Easy9 software memory can be displayed on the monitor.

By the way, as shown in FIG. 1, the 4-shiba sofa memory has a storage area of 2048 bits x 2800 lines, whereas the refresh memory in the display interface has a storage area of 1024 bH x 70.
Only the storage area of the 0th line goes up, so < -X)
All image information in the tsufa memory is transferred to the CRT at once.
It is impossible to display it on the display.

Therefore, in the past, a size conversion circuit was provided in the display interface to reduce the image information read from the page buffer memory to 1/4! (By reducing the image size and storing it in the refresh memory, all the image information in the buffer memory is displayed on the CRT display at once, as shown in FIG. 2.)

However, in this case, since the reduction ratio is constant regardless of the size of the image information, the size of the image information displayed on the CRT display varies, and the display area on the CRT display is not used effectively. there were.

[Object of the invention] This invention was made in view of the above circumstances,
The purpose is to provide an excellent image display device that can change the size of an image so that the image can be displayed on the entire display area of the display unit, and that can effectively utilize the display area of the display unit. There is a particular thing.

[Summary of the Invention] This invention converts image information stored in a first storage means by a size conversion means and stores it in a second storage means, and displays the image information in the second storage means. The conversion rate of the size conversion means is set based on the correspondence between the size of the document in which image information is recorded and the display area of the display means, and the size conversion rate is set by the control means regardless of the document size. By setting
The image information is displayed in a constant size and in its entirety in the display area of the display means.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In FIGS. 3 and 4, 1 is a main control device, which includes a CPU 2 that performs various controls, various file sets (a collection of optical discs to be described later), and various files (
A management information storage device, such as a floppy disk device 3, which stores management information for managing optical disks (optical disks); a title memory 4, which temporarily stores title information read from an optical disk device 9 (to be described later); The storage area (2) corresponding to the image information of the original (minus sign)
It consists of a page buffer memory 5 having 048 pits x 2800 lines), a pattern generator 6 in which pattern information such as characters and symbols is stored, and the like. Also,
7 is a reading device, for example, a two-dimensional scanning device, which scans originals (documents);
By performing two-dimensional scanning over the document 8, a video signal corresponding to the image information on the document 8 is obtained. Reference numeral 9 denotes an optical disk device which is a large-capacity storage device, and sequentially stores image information read by the two-dimensional scanning device and image information created by the main controller 1 in a storage medium, that is, a dedicated storage area of an optical disk. It is something. Is 10 the key? - input a unique title and various operation commands corresponding to the image information. Reference numeral 11 denotes an output device 21-Tocoby device, which outputs image information read by the two-dimensional scanning device 7 or image information read from the optical disk device 9 as a hard copy 12. 13 is an image display device which is an output device;
It consists of a size conversion circuit 14, a display interface 15, a cathode ray tube display device (hereinafter referred to as CRT display) 16, etc., and displays image information read by the two-dimensional scanning device 7 or image information read from the optical disk device 9. It is something.

However, floppy disk device 3, title memo I
) 4, -s! - Schaffer memory 5, nozzle generator 6, two-dimensional scanning device 7, optical disk holder 9,
The key gate 10, hard copy device 11, size conversion circuit 14, and display interface 15 are each CPU
2 is connected to the data bus 20 from 2. In addition, the title memory 4, page buffer memory 5, turn quenerator 6, two-dimensional scanning bag #7, optical disk device 9, hard copy device 11, size conversion circuit 14, and display interface 15 are each image paths 21. The parties are connected and information is transferred to each other.

Here, FIG. 5 specifically shows the two-dimensional scanning device f7. That is, 31 is a paper feed tray, and the document set on this tray 31 is taken in by a take-in roller 32.3.
2 into the main body, and further conveyed by conveying rollers 33,
33 onto a document table (glass plate) 34.

The original that has passed through the original platen 34 is transferred to a transport roller 35,
35 and paper ejection rollers 36, 36, the paper ejection tray 3
7 is discharged on top. A pair of exposure runs f38.38 are provided at positions corresponding to the document table 34, and the light emitted from these lamps 38.38 is irradiated onto the document being conveyed, and the reflected light is reflected by the mirror 39. and is projected onto the CCD line sensor 4 via the projection lens 40.

In this way, a video signal corresponding to the image information on the document can be obtained from the line sensor 41. A photocoupler consisting of a light emitting diode 42 and a phototransistor 43 is disposed near the taking-in rollers 32 and 32 to detect the taken-in original, and also to detect the size of the taken-in original. Light emitting diodes 44a (44b, 44c) for

44d) and phototransistor 45a (45b
.

44c, 44d) are provided.

6(a) and 6(b) show the structure and operation of an operation control circuit based on the output of the phototransistor 43. FIG. That is, the output of the phototransistor 43 is sent to the first timer 46 and the second timer 42 via the inverter 45.
, is supplied to the third timer 48.

The first timer 46 outputs a drive signal for operating the rollers and lamps 38 and 38 for a certain period of time after the leading edge of the document is detected. The second timer 47 starts the line sensor 41 after a predetermined time after the leading edge of the document is detected.
Outputs a reading start signal to operate. The third timer 48 is configured to output a reading end signal to stop the operation of the line sensor 41 after a predetermined period of time after the leading edge of the document is detected.

Further, FIG. 7(,)(b) shows the arrangement of the phototransistors 45h (45b, 45c, 45d) and the configuration of a size detection circuit based on their outputs. That is, each light emitting diode and its corresponding phototransistor 45 are arranged in a direction perpendicular to the conveying direction of the document.
m, 45b, 45e.

45d are arranged at regular intervals, and the output of each phototransistor differs depending on the size of the document input with reference to the side edge on the conveyance path, so that the output from the AND circuits 49, 50, 51, and 52 is different. A3 detection signal, B
4 detection signal, A4 detection signal, and B5 detection signal are obtained.

Here, we will briefly explain what kind of operation is performed in the above configuration.

When a document 8 is set on the two-dimensional scanning device 7, the document 8
The above image information is read and sequentially stored in the page buffer memory 5. At this time, the document size detected by the two-dimensional scanning bag B7 is supplied to the CPU 2.
Stored in RAM within R.

When the - unit of image information is stored in the page/gusa memory 5, the CPU 2 reads out the size conversion rate (reduction rate) corresponding to the detected document size from the ROM and converts it into the size conversion circuit. Set to 14. thus,
The image information in the page buffer memory 5 is reduced to a predetermined size by the size conversion circuit 14 and stored in the refresh memory in the display interface 15. and,
The image information in the refresh memory is displayed on the CRT display 16.

Further, when image information is read from the optical disk device 9,
The read image information is sequentially stored in the page/graph memory 5. At this time, document size information included in advance in the index information corresponding to the image information that has been successively displayed is supplied to the CPU 2, and is stored in the RAM in the CPU R at t.
is memorized. When the unit of image information is written in the page buffer memory 5, the CPU 2 converts the size conversion rate (reduction rate) corresponding to the stored document size information.
is read from the ROM and set in the size conversion circuit 14.

In this way, the image information in the graph memory 5 is reduced to a predetermined size by the size conversion circuit 14 and stored in the refresh memory in the display interface 15. Then, the image information in the refresh memory is C
It is displayed on the RT display 16.

Next, the above-mentioned size conversion circuit 14 and display interface 15 will be explained in detail. First, FIG. 8 shows the size conversion circuit 14.

That is, one line of image information in the page buffer memory 5 is supplied to the data input terminal 400.

In this case, one line of image information consists of 2048 bits. Image information supplied to the terminal 400 is stored in the RAM 401
and is supplied to a 6-bit latch circuit 406. RAM
401 is of 2×1 bits, and its address remains designated by the output of the counter 413. However, 5
1 RAM 401-405 and 7 latch circuits 4
06 to 412 are provided. These RAMs 401-4
05 and latch circuits 406-412 are all operated by a clock signal supplied from a main clock generator 414 via a signal path shown by a solid line or a signal path shown by a dash-dotted line. In this case, the signal path indicated by the solid line is used when the circuit functions as a reduction circuit, and the signal path indicated by the two-dot chain line is used when the circuit functions as an expansion circuit.

Under the address control of the counter 413, the image information of the first line of 2048 bits is stored in the first RAM 40.
1K is stored. Then, when the first bit of the second line of image information is provided to RAM 401, the RAM
The first bit of the first line image information stored in 401 is read therefrom and latched in latch circuit 406. On the other hand, the first bit of the second line is RAM 40
1 first memory location. The second bit of the second line is then stored in RAM 401, and the second bit of the first line is sequentially output therefrom and latched into latch circuit 406. At the same time, latch circuit 406
The first pit of the first line latched to is RAM402.
and stored there. In this way, when the last (2048th) bit of the second line is stored in the RAM, the first line of image information of 2048 bits is stored in the RAM.
Shifted to M 402.

Therefore, each line of image information of 2048 bits is R
AM 401-405 are shifted sequentially. Finally, the image information of the first to fifth lines is stored in RAM 4.
05 to 401, the first bit of the image information of each of the first to fifth lines is latched by the latch circuit 406, and the first bit of the image information of the sixth line, which is simultaneously supplied to the terminal 400, is latched by the latch circuit. =107.

When the second bit of the sixth line is supplied to terminal 400,
The first bits of the first to sixth lines latched by the latch circuit 407 are supplied to the next latch circuit 408, and the second bits of the first to sixth lines are latched by the latch circuit 407. Similarly, when the seventh bit of the image information of the sixth line is supplied to the terminal 400, each of the first
~The first bit of the sixth line is latched by the latch circuit 412, its second bit is latched by the latch circuit 411, the third bit is latched by the latch circuit 410, and the fourth bit is latched by the latch circuit 410.
The bit is latched into latch circuit 409, the fifth bit is latched into latch circuit 408, and the sixth bit is latched into latch circuit 407. Therefore, when the respective bits latched by latch circuits 407-412 are rearranged into a matrix array, the original image is reproduced as a dot image as shown in FIG. In Figure 9,
A black dot represents one bit, and a white dot represents an O pit. Therefore, the local image information of 6 pits (X direction) x 6 lines (X direction) is transmitted to the latch circuits 405 to 412.
The data is supplied to the arithmetic ROM 415 from the ROM 415.

Two adders 416, 417 and two latch circuits 41
8,419, comparator 420, and counter 413
A second adder 421 constitutes the direction distance calculation circuit 430.
．． 422, two latch circuits 423 and 424, a comparator 425, and a counter 426 constitute a distance calculation circuit 431 in the X direction. These distance calculation circuits 430, 43
1 is X.

It is used to calculate the size-converted image dot position in the X direction. X supplied from CPU 2,
Size conversion (enlargement, reduction) rate setting data in the X direction is supplied to adders 416, 417, 421 and 422. In FIG. 8, reduction rate data is shown as an example. The integer part of the reduction ratio is provided to adders 416, 421 and decoder 427, and the fractional part is provided to adder 417.422. The outputs of adders 416, 417°421, and 422 are supplied to latch circuits 418 and 419°423, and 424, respectively. Latch circuit 41
The outputs of 8,423 are supplied to the negative input terminals of comparators 420, 425, respectively, and are feed-macked to the inputs of adders 416, 421. The other side of comparators 420, 425 has inputs from counters 413, 426. The outputs of the latch circuits 419 and 424 are output to the adder 417, respectively.
, 422 are fed back.

The three most significant bits of the fractional output data of circuit 430 and the three most significant bits of the fractional output data of circuit 431 are taken from respective latch circuits 419 and 424 and provided as addressing signals to the %Royx1s. This R.O.
The pixel level before reduction is stored in M415. The output data read from the arithmetic ROM 415 is supplied to the input side of a comparator 432, and the other end of the comparator 432 is supplied with slice level data obtained from a slice level data oscillator 433. The match signal of comparator 432 is applied to the D input terminal of flip-flop 434, and the output of AND/DART 435 is applied to the clock terminal CL of the flip-flop. One input terminal of the AND gate 435 is supplied with the coincidence output XC0M of the comparator 420, and the other input terminal is supplied with the input YCOM from the comparator 425.
M is supplied.

Here, the operation of such size conversion circuit 14 will be explained as follows.
This will be explained in detail using the figure. Assume that the reduction ratio specified by CPU 2 is 174.5. In this case, the integer part of the reduction ratio is 4, while the decimal part is 0.5. Each digitally formed numerical data is added to an adder 416.
, 417 and 421°422.

In FIG. 10, the image dot positions of the original image are designated by the symbol "'X," whereas the image dot positions of the size-converted image are designated by black dots.

The image dot at position (i, j) on the original image is (PI, j
) is defined as

The distance between two adjacent image dots of the original image is defined as one. Then, the distance between the two reduced dots on the original image is equal to the reduction rate R7.

L = R.

In this case, the constant value is set as 4.5. Center position!
LXL with Q+, , when a region is designated as S, the average gray level of S is the image driver belonging to region S)
It is calculated based on the fact whether (PI,j) exists or not. Posture ipi,j and transformation position [Q, .

Defining the distance between r(,j), the weighting factor αs,j for calculating the average gray level φ11. is determined to be inversely proportional to the distance rl,j.

Therefore, factor αi,'' is Q12. If we set it as 1 at the position V2 and set it as 0.5 at the position V2 away, then the factor αi,j is
J) Defined by .

It can be displayed as

Therefore, the average gray level φ, , J u,3=. Then, the transformed image (D) Qx,J is obtained by using a predetermined slice level θ.

Thus, the integer part 4 of the reduction ratio supplied from the CPU 2 is supplied to the latch circuit 418 via the adder 416. When the content of the counter 413 becomes 4, the match signal XC
0M is sent out from comparator 420 and latch circuit 418
, 419 and andr-) 435. On the other hand, the decimal part 0.5 is sent to the latch circuit 4 via the adder 417.
It is latched at 19. Therefore, when the signal XC0M is supplied to the latch circuits 418 and 419, 0.5 + 0
．． An operation of 5=1 is performed in adder 417 and a carry of 1 is provided to adder 416. Therefore, 4+4+1
=9 is performed in the adder 416, and new data "
'9'' is set in the latch circuit 418. At this time, when the content of the counter 413 becomes 9, an output XC0M is obtained at the output of the comparator 420. Then, 9+4=13 is set in the latch circuit 418. The output XC0M is obtained when the counter 413 reaches 13. At this time, 13+4
An operation of +1 is performed in the adder 416, and new data "
18” is set by latch circuit 418.

In this way, the contents of the counter 413 are 4.9°13.18
．． 22, 27. .

The same operation as circuit 430 is performed in circuit 431 as well. The output YCOM indicates that the contents of the counter 426 are 4,
9, 13, 18, 22, 27. ...'' is supplied from the comparator 425 to the other input of the AND dart 435. Both inputs XC0M and YCOM
35, the output is provided to the clock terminal of flip-flop 434. At this time, the output level φ1
1. exceeds the output level of slice level generator 433, the output is transferred from comparator 432 to flip-flop 434.
The black dot output QIJ is obtained from the flip-flop 434 as shown in FIG.

In the enlargement operation, for example, an enlargement rate of 0.5 is
2 to adders 416 , 417 , 421 , and 422 . In this case, Q12. The number of ``Pi'' is twice the number of ``Pi,'' and the image quality information is expanded twice.

Next, FIG. 11 shows the display interface 15. A refresh memory 60 has a storage area of 1024 bits (X direction) x 1400 lines (Y direction). (The CRT display 16 has a display area of 1024 pits x 700 lines). 61 is 16
The bit register is reduced and supplied by the size conversion circuit 14.

The image information to be displayed is refreshed every 16 bits in the memory 6.
0. Reference numeral 62 denotes a selector for selecting the output of the 16-bit register 1 or the pattern information from the 4-turn generator 6.

63 is a write address counter that temporarily holds the image information write start address supplied from the CPU 2;
The size conversion circuit 14 (clock from the flip-flop y7' 434 shown in FIG. 8) divides it by 1/16, and
The X-direction and Y-direction addresses of the refresh memory 60 are designated by counting up using a clock signal supplied through the counter 64 and the AND circuit 65. Further, this write address counter 63 is supplied with a pattern information write address corresponding to a specific area at the lower right end of the refresh memory 60 from the CPU 2 when writing of the image information is completed. In this case, the other input terminal of the AND circuit 65 has the CPU 2
The tt Os signal is supplied from the write address counter 63, so that no clock signal is supplied to the write address counter 63. Reference numeral 66 denotes a CRT controller, which consists of a counter 67, an address register 68, a 700 line detection circuit 69, etc., and when reading image information from the refresh memory 60, it controls the X and Y directions of the refresh memory 60.
Addressing is performed in a direction. Here, the counter 67 counts the clock signal supplied from the oscillation circuit 10 via the 1/16 counter 71.
It consists of a /64 counter 67a and a counter 67b that performs a carry count of this counter 67&.
The contents of b are the X direction designation address. Further, the address register 68 holds a read start address (line address) supplied from the CPU 2. The 700 line detection circuit 69 has a counter 6
Detects whether 7b has counted 700" and
0'', the counter 67b is made to newly set the start address of the address register 68. 72 is a selector that selects the X-direction specified address of the address counter 63 and the counter at the time of writing and reading. It selects either the X-direction specified address of 67b. 73 is a selector that selects either the X-direction specified address of the address counter 63 or the X-direction specified address of the counter 67 & during writing and reading. 74 is a 16-bit register, and 16 bits are read from the refresh memory 60.
Bit image information is serially output using the output of the oscillation circuit 70 as a clock signal. 80 is a cursor setting circuit which receives a horizontal synchronization signal Hsync, which is supplied from the CRT controller 66 to the CRT display 16;
A cursor video signal corresponding to a predetermined cursor (frame) K is generated in synchronization with the vertical synchronization signal v8ync and the clock signal from the oscillation circuit 70. The cursor video signal generated from the cursor setting circuit 80 and the video signal output from the 16-bit register 74 are supplied to the CRT display 16 via the OR circuit 200.

Here, FIG. 12 shows the cursor setting circuit 80. In FIG. 12, reference numeral 81 is an X-direction cursor memory, which holds position information on both left and right sides of the cursor in accordance with write code information JK from the CPU 2. Reference numeral 82 denotes a Y-direction cursor memory, which holds position information of the upper and lower sides of the cursor in accordance with the write code information J from the CPU 2, respectively. 83 is an X-direction address counter that counts the clock signal shown in FIG. 14 (,) (supplied from the oscillation circuit 70 shown in FIG. 11). A Y-direction address counter 84 counts the horizontal synchronizing signal Hayne shown in FIG. 14(b) supplied from the CRT controller 66. 85 is a decoder, and when the contents of the counter 83 match the position information on both sides respectively, as shown in FIG. 14(c)
It outputs a logic "1" signal shown in FIG. 86 is a decoder which outputs a logic "1" signal shown in FIG. 14(d) K when the contents of the counter 84 match the position information of the upper and lower sides, respectively. 87,118 is T
-Flip frog, respectively Fig. 14 (fHg
) are output respectively. 89 is an OR circuit), which outputs the signal shown in FIG. 14 (0). 90. ．． 90
2903 is an AND circuit, among which AND circuit 90
,．． 902 outputs the signals shown in FIG. 14(,)(h). W is a pulling signal, and Cv is a cursor video signal.

On the other hand, in FIG. 13, 92 is a cursor key provided on the keyboard 10. And 93°94.95.
Reference numeral 96 is a movement key, which emits a movement pulse while being pressed. C
The PU 2 detects this nozzle and moves the image or cursor in the direction of the arrow. 97 is a movement key for moving the cursor or the display area of the CRT display 16 for image information in the flexible memory 60 to the upper left end. 98 is an enlargement key, and 99 is a reduction key.

In such a configuration, how image information is displayed will be explained.

When a document 8 is set on the two-dimensional scanning device 7, image information on the document is read and the size of the document is detected. And it was read ii! ii f& information is stored in the page/graph memory 5C with sizes corresponding to the respective sizes as shown in FIG. At this time, if the document size is B4, the CPU 2 sets the reduction rate of the size conversion circuit 14 to 1/4. For A4, the reduction rate is 1/3.3, and for BII, the reduction rate is 1/3.
2.7, if it is AS, the reduction rate is set to 1/2. In this way, the image information in the page buffer 5 is reduced by the size conversion circuit 14 and stored in the refresh memory 60. When image information is stored in the refresh memory 60,
CPU' displays the characters and characters corresponding to the original size of the image information.
Nine turns are read from the pattern generator 6 and added to a specific area of image information in the refresh memory 60. Therefore, Fig. 16 (a) (b) (c)
As shown in (d), the entire image information is displayed on the CRT display 16 at a constant size regardless of the size of the opposite side.
, and the display area of the CRT display 16 is used as effectively as possible. Moreover, in this case, since the document size is added to the lower right portion of the image information that is displayed once, the document size of each image information can be easily recognized. In addition, -1 buffer memory 5, refresh memory 6ρ
And if the manuscript 8 is used in landscape orientation,
Since the image information is displayed over the entire display area of the CRT display 16 as shown in FIGS. 17(a), (b), (c), and (d), the display area can be used more effectively.

By the way, when such image information is displayed in its entirety, the reduction ratio for the image information is reduced to a certain extent, so there is a problem in terms of resolution.

Therefore, by operating the cursor keys 92 of the keyboard 10, the displayed image and cursor are moved to the desired position, and in this state, the desired image is specified with the cursor, and the specified image is enlarged and displayed. It is now possible to do so.

In this case, the CPU,' performs control according to the flowchart shown in FIG. In CPU 2, first, CRT
Set '1' in the address register 68 of the controller 66 and read 700 lines from 1 line of the refresh memory 60.
It reads out up to the line and displays it on the CRT display 16 (Stella 7'S1).

That is, as shown in FIG. 19(,), image information of the upper half area (solid line in the figure) of the refresh memory 60 is displayed. Further, the CPU 2 sets the address of the cursor S in the cursor setting circuit 80 as shown by the dashed line in FIG. In this state, cursor key 9
When the movement key 96 of 2 is turned on (Stella 7'S2.S
3. S4. S5), the contents of the address register 68 of the CPU 2 HCRT controller 66 are set to +10, for example (step 86). In this way, each time the movement key 96 is turned on, the display area for image information in the refresh memory 60 sequentially moves downward as shown in FIGS. 19(b) and 19(c). In this case, there is no change in the corresponding position between the display area and the cursor S. After that, when the Y direction start address reaches 700" (step 35), the CPU
2 changes the Y-direction address of the cursor S in the cursor setting circuit 80 (-) every time the cursor key 96 is turned on (Stella fs7).

In this way, each time the movement key 96 is turned on, FIG.
) The cursor S moves downward as shown in (,).

When the movement key 93 is turned on from this state (steps S2.S3゜84.S8.S9), Fig. 20 (,) (
d) The display area moves upward as shown in FIG. 20(c), and then the cursor S moves upward as shown in FIG. 20(b) (, ) (Stella fS 10 ). In addition, Fig. 21 (a
), if you turn on the movement key 95, (step 82
, S3), since there is no movement range in the display area, the cursor S
moves to the right, resulting in the state shown in FIG. 21(b) (step 511). Further, if the movement key 94 is turned on in the state shown in FIG. 22(,) (step 82.83), only the cursor S moves to the left, resulting in the state shown in FIG. 22(b) (step 511).

If the enlargement key 98 is turned on in such a display state, the image information within the cursor S is enlarged and newly displayed. Moreover, if the reduction key 99 is turned on, the original display is made.

In this way, by specifying the movement of a certain area for the image information in the refresh memory 60, the image information within that certain area can be displayed immediately. There is no need to read data from the screen, and the display speed can be significantly improved. Furthermore, by performing the scale according to the above-mentioned movement specification, the reduction rate for the image information need only be adjusted to the storage capacity of the flexible memory 60. In other words, the reduction rate is larger than when it is adjusted to the display capacity of the CRT display. It is possible,
Therefore, the resolution is increased and recognition is easy.

Furthermore, since the designation of movement of a fixed area is given priority over the movement of a zoom-up area, operations for each movement specification can be handled by a single operation mechanism, which is extremely convenient in practice. .

In the above embodiment, priority is given to specifying movement of a certain area, but priority may be given to specifying movement of the cursor. In addition, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without changing the gist.

[Effects of the Invention] As described above, according to the present invention, the size of the image can be changed so that the image can be displayed in the entire display area of the display unit, and the display area of the display unit can be used effectively. It is possible to provide an excellent image display device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a storage area of a page buffer memory, FIG. 2 is a diagram showing an example of a display state of image information in FIG. 1, and FIG. 3 is an image information storage and retrieval device according to an embodiment of the present invention. 4 is a detailed configuration diagram of FIG. 3, FIG. 5 is a detailed configuration diagram of the two-dimensional scanning device, and FIG. Figure 7(a) shows the circuit configuration diagram, Figure 7(b) shows the time chart, Figure 7 shows the size detection unit shown in Figure 5, and the figures (,) show the operation control unit of Figure 5. Planar configuration diagram, the same figure (b) is a circuit configuration diagram, No. 8
The figure is a block diagram specifically showing a size conversion circuit according to an embodiment of the present invention, Figures 9 and 10 are diagrams for explaining the operation of Figure 8, and Figure 11 is an embodiment of the present invention. FIG. 12 is a configuration diagram specifically showing the display interface in FIG. 11, FIG. 13 is a configuration diagram of the cursor keys, and FIG.
The figure is a time chart for explaining the operation of Fig. 12,
Figure 15 shows the zipper memory and the various sizes stored therein. A configuration diagram showing correspondence with ili image information,
Figure 16(,)(b)(c)(d) and Figure 17(a)
) (b) (c) (d) are iil! in one embodiment of this invention! Figure 18 showing the overall display state of image information
The figure is a flowchart showing display control in the same embodiment,
Figure 19 (a) (b) (e) (d) (e),
Figure 20 (a) (b) (C) (d) (e), Figure 21 (,) (b) and Figure 22 (a) (b) are examples of image information and cursor display in the same embodiment. FIG. 2...CPU, 5...KN buffer memory, 6...
... Pattern generator, 13... Image information display device, 14... Size conversion circuit, 15... Display interface, 16... CRT display, 60...
・Refresh memory, 80... cursor setting circuit,
92... Cursor key Figure 1 Figure 50 A (a) (b) Engraving of Figure 3 and Figure 7 (no changes in content) Figure 9 Figure 10 Figure 13 Figure 14 Figure 15 (a>'60 (b) (C) (d) (e) Fig. 19 Fig. 20 Fig. 21 Fig. 22 Procedural amendment (method) % formula % Name of the invention Double image table Small device 3゜n city Relationship with the person who corrects the case

Claims (1)

[Scope of Claims] A reading means for reading images having various document sizes, a first storage means for storing images read by the reading means, and a size of the image written in the first storage means. A conversion means for converting, a second storage means for storing the image whose size has been converted by the conversion means, and a display means having a display area for displaying the image stored in the second storage means, control means for setting a size conversion rate by the conversion means so that the entire image displayed on the display means is displayed at a substantially constant size regardless of the original size of the image read by the reading means; An image display device comprising: