JPH021065A - Picture display device - Google Patents

Abstract

PURPOSE:To display a picture on the whole of the display area of a display part by converting the size of either read picture information or other picture information retrieved from an optical storing means regardless of the original size of the picture and displaying the size-converted picture information. CONSTITUTION:An original 8 is read by a two-dimensional scanner 7, and the read picture information is stored in the page buffer memory of a main control unit 1. Further, the picture information retrieved from an optical disk device 9 is similarly stored in the page buffer memory. According to designation from a keyboard 10, the CPU of the main control unit 1 outputs the picture information stored in the page buffer memory to a display device 13 and sets a size converting ratio so that the whole of the picture to be displayed on a CRT display 16 can be displayed with an approximately fixed size on the approximately whole of the display area regardless of the original size read by either the two-dimensional scanner 7 or the optical disk device 9. Thus, the display area of the display part can be effectively used.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention stores image information such as documents in a storage device, and extracts required image information from among various image information stored in the storage device as needed. The present invention relates to an image display device of an image information storage and retrieval device that searches for and reads out the information, and outputs it in a visible state.

[Technical background of the invention and its problems] Recently, image information such as documents, etc., which is generated in large quantities, is
The read image is read by dimensional scanning and stored in a FW information storage device, such as an optical disk device, and all required image information is searched as needed from among the various image information stored in this storage device. An image information storage and retrieval device has been developed and put into practical use, which reads out the image information and outputs it in a form that can be viewed with a hard copy device.

In such an image information storage and retrieval device,
In order to deal with the difference between reading speed and storage speed, or reading, one unit of read image information (-page) or one unit of read image information sound- It is equipped with an image information display device consisting of a display interface and a CRT display, so that the image information in the page buffer memory can be displayed on all monitors.

By the way, as shown in FIG. 1, the page buffer memory has a storage area of 2048 bits x 280 Q lines, whereas the refresh memory in the display interface has a storage area of 1024 bits x 280 Q lines.
It has a storage area of only 700 lines, so it is impossible to display all the image information in the page buffer memory at once on a CRT display.

Therefore, in the past, the S/F conversion circuit was installed inside the display interface. By reducing the image information read from the page buffer memory to 174 and storing it in the refresh memory, all the image information in the page buffer memory is displayed on the CRT display at once as shown in FIG. It was set to display as follows.

However, in this case, since the reduction ratio is constant regardless of the size of the image information, the size of the image information displayed on the CRT display varies, and the display area on the CRT display is not used effectively. there were.

[Object of the invention] This invention was made in view of the above circumstances,
The purpose of this is to convert the size of the image so that it can be displayed in the entire display area of the display unit.
An object of the present invention is to provide an excellent image display device that can effectively utilize the display area of a display section.

[Summary of the Invention] This invention converts image information read by a reading means stored in a page memory or image information retrieved and output from an optical storage means by a size conversion means and stores it in a refresh memory, and In a device that displays the image information in the refresh memory on the display means, by setting the conversion rate of the size conversion means by the control means regardless of the size of the document, the image information can be displayed at a constant size and the entire image can be displayed on the display means. This allows the display area to be displayed all at once.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to all the drawings. 3 and 4, reference numeral 1 is a main control device, which includes a CPU 2 that performs various controls, various file sets (a collection of optical disks to be described later), and each azuki file (
A management information storage device, such as a floppy disk device 3, which stores management information for managing optical disks (optical disks); a title memory 4, which temporarily stores title information read from an optical disk device 9 (to be described later); The storage area (2 pages) corresponding to the image information of the original
It consists of a page buffer memory 5 having 048 bits x 2800 lines), a pattern generator 6 in which pattern information such as characters and symbols is stored, and the like. Also,
7 is a reading device, for example, a two-dimensional scanning device, which scans originals (documents);
A video signal corresponding to the image information on the original document 8 is obtained by performing two-dimensional scanning on the original document 8. Reference numeral 9 denotes an optical disk device which is a large-capacity storage device, and sequentially stores image information read by the two-dimensional scanning device and image information created by the main controller 1 in a storage medium, that is, a dedicated storage area of an optical disk. It is something. Reference numeral 10 is a key for inputting a unique title and various operation commands corresponding to image information. Reference numeral 11 denotes a hard copy device as an output device, which outputs image information read by the two-dimensional scanning device 7 or image information read from the optical disk device 9 as a complete hard copy 12. Reference numeral 13 denotes an image display device which is an output device, and includes a size conversion circuit 14, a display interface 15, a cathode ray tube display device (hereinafter referred to as CRT display) 16, etc., and image information read by the two-dimensional scanning device 7. Alternatively, all the image information read from the optical disc storage 9 is displayed.

A floppy disk device 3, a title memory 4, a page buffer memory 5, a turn generator 6, a two-dimensional scanning device 7, an optical disk device 9, a key date 10, a hard copy device 11, a size conversion circuit 14, and a display device. The interfaces 15 are each connected to a data bus 20 from the CPU 2. Mana, title memory 4,
Page buffer memory 5, Nogturn generator 6.
Two-dimensional scanning device 7, original disk device 9, hard copy device 1, size conversion circuit 14, display interface varnish 15
are connected to the image bus 21, respectively, so that information can be transferred to each other.

Here, FIG. 5 specifically shows the two-dimensional scanning device 7. As shown in FIG. In other words, 31 is a paper feed tray, and the originals set on this tray 31 are taken in by rollers 32 and 32.
is taken into the main body by the transport rollers 33, 3.
3 onto a document table (glass plate) 34. The original that has passed through this original platen 34 is transported by transport rollers 35 and 3.
5 and the paper ejection tray 37 by the paper ejection rollers 36, 36.
is discharged to the top. 1 at the position corresponding to the document table 34 above.
A pair of exposure rungs 38.38 are provided, and the light emitted from these lamps 38.38 is irradiated onto the conveyed document, and the reflected light is transmitted to the CCD line sensor 41 via a mirror 39 and a projection lens 40f. be projected. In this way, a video signal corresponding to the image information on the document can be obtained from the line sensor 41. A photocoupler consisting of a light emitting diode 42 and a phototransistor 43 is disposed near the taking-in rollers 32, 32 to detect all the documents being taken in, and also to detect all sizes of the documents taken in. Light emitting diodes 41 & (44b, 44e, 44d) and phototransistors 45IL (45b, 44c) for

A photocoupler consisting of 44d) is provided.

FIG. 6 (jL) (b) shows the phototransistor 43
This figure shows the configuration and operation of an operation control circuit based on the output of the circuit. That is, the output of the phototransistor 43 is transmitted through the inverter 45 to the first timer 46 and the second timer 4.
7, supplied to the third timer 48.

The first timer 46 outputs a full oscillation signal to operate each roller and run f38.degree.38f for a certain period of time after the leading edge of the document is detected. The second timer 47 starts the line sensor 4 after a predetermined time after the leading edge of the document is detected.
1 Output a reading start signal for full operation. The third timer 48 is configured to output a precise reading end signal that completely stops the operation of the line sensor 41 after a predetermined period of time after the leading edge of the document is detected.

In addition, FIG. 7(a) a shows the phototransistor 45.
& (45b, 45e, 45d) and the configuration of a size detection circuit based on their outputs. That is, each light emitting diode and its corresponding phototransistor 45 are arranged in a direction perpendicular to the conveying direction of the document.
*, 45b, 45c, and 4561 are arranged at regular intervals, and the output of each phototransistor differs depending on the size of the document inputted as a reference for the side edges on the conveyance path. , 51.52, A, detection signal % B4 detection signal, A4 detection signal, and Bs detection signal are obtained, respectively.

Here, the operations performed in the above configuration will be briefly explained.

When all the originals 8 are set on the two-dimensional scanning device 7, the originals 8
The above image information is read and sequentially stored in the page buffer memory 5. At this time, the document size detected by the two-dimensional scanning device 7 is supplied to the CPU 2.
It is stored in the RAM in the 1.

When the - unit of image information is stored in the 4-di-buffer memory 5, the CPU 2 reads the size conversion $ (reduction rate) corresponding to the detected document size from the ROM,
It is set in the size conversion circuit 14. In this way, the image information in the page buffer memory 5 is transferred to the size conversion circuit 14.
is reduced to the specified size and displayed in the display interface 1.
5 is stored in the refresh memory. The image information in the refresh memory is then displayed on the CRT 7'' display 16.

Further, when image information is read from the optical disk device 9,
The read image information is sequentially stored in the page buffer memory 5. At this time, document size information included in advance in the index information corresponding to the read image tW information is supplied to the CPU 2, and the RAM in the CPo 2 is
is memorized. Therefore, when the - unit of image information is stored in the page buffer memory 5, CPtJ' is determined by the size conversion rate (reduction") corresponding to the stored document size information.
4) 'e Read from the ROM and set it in the size conversion circuit 14.

In this way, the image information in the page buffer memory 5 is reduced to a predetermined size by the size conversion circuit 14 and stored in the refresh memory in the display interface 15. Then, the image information in the refresh memory is CR
It is displayed on the T display 16.

Next, the above-mentioned size conversion circuit 14 and display interface 15 will be explained in detail. First, FIG. 8 shows the size conversion circuit 14 in its entirety.

That is, one line of image information in the di-buffer memory 5 is supplied to the data input terminal 400.

In this case, one line of image information consists of 2048 pits. Image information supplied to the terminal 400 is stored in the RAM 401
and is supplied to a 6-bit latch circuit 406. RAM
401 has 2×1 pits, and its address is designated by the output of the counter 413. However, 5
1 RAM 401-405 and 7 latch circuits 4
06 to 412 are provided. These RAMs 402-4
05 and latch circuits 406-412 are all operated by a clock signal supplied from a main clock generator 414 via a signal path te shown by a solid line and a signal path shown by a chain double-dashed line. In this case, the signal path indicated by the solid line is used when the circuit functions as a reduction circuit, and the signal path indicated by the two-dot chain line is used when the circuit functions as an expansion circuit.

Under the address control of the counter 413, the image information of the first line of 2048 pits is stored in the first RAM 40.
It is stored in 1. Then, when the first bit of the second line of image information is provided to RAM 40 J, the RAM
(The first bit of the first line image information stored in RAM 401 is read from there and latched in latch circuit 406.
is stored in the first memory o case. The second bit of the second line is then stored in RAM 401 and the second bit of the first line is read therefrom and latched into latch circuit 406. At the same time, latch circuit 406
The first pit of the psychokinesis 1 line is latched to RAM402.
and stored there. In this way, when the last (2048th) bit of the second line is stored in the RAM, the image information of the first line of 2048 pits is stored in the RAM.
Shifted to M 402.

Therefore, each 1-line image information of 2048 pits is R
AM 401-405 are shifted sequentially. Finally, the image information for the 1st to 5th lines is stored in RAM 4.
05 to 401, the first bit of the image information of each of the first to fifth lines is latched in the latch circuit 406, and the first bit of the image information of the sixth line, which is simultaneously supplied to the terminal 400, is latched in the latch circuit 407. supplied to

When the second bit of the sixth line is supplied to terminal 400,
The first bits of the first to sixth lines latched by the latch circuit 401 are supplied to the next latch circuit 408, and the second bits of the first to sixth lines are latched by the latch circuit 407. Similarly, when the seventh pit of the sixth line of image information is supplied to the terminal 400, each of the first
~ The first bit of the sixth line is latched by the latch circuit 412, the second bit is latched by the latch circuit 411, the third bit is latched by the latch circuit 410, and the fourth bit is latched by the latch circuit 410.
The pit is latched into latch circuit 409, the fifth bit is latched into latch circuit 408, and the sixth bit is latched into latch circuit 407. Therefore, when the respective bits latched by latch circuits 407-412 are rearranged into a matrix array, the original image is reproduced as a dot image as shown in FIG. In Figure 9,
The black dots represent l-bits and the white dots represent 0-bills. Therefore, the local image information of 6 bits) (X direction) x 6 lines (Y direction) is latched, and towers 405 to 41
2 to the calculation ROM 415.

Two adders 416, 417 and two latch circuits 41
8,419, comparator 420, and counter 413
A directional distance calculation circuit 430 is configured, and an adder 421 of 2
．． 422, two latch circuits 423 and 424, a comparator 425, and a counter 426 constitute a distance calculation circuit 431 in the Y direction. These distance calculation circuits 430, 43
1 is X.

It is used to calculate all the dot positions of the size-converted image in the Y direction. X supplied from CPU 2,
Size conversion (enlargement 1.reduction) rate setting in the Y direction 7”
- is supplied to adders 416, 417, 421 and 422. In FIG. 8, the reduction rate f is shown as an example. The integer part of the reduction rate is added to the adder 416.42.
1 and decoder 427, the fractional part of which is M
It is supplied to Jn units 417 and 422. Adder 416,4
The output of 17°421.422 is the latch circuit 418, 41
9°423 and 424 respectively. The outputs of the latch circuits 418 and 423 are supplied to the negative input terminals of comparators 420 and 425 degrees, respectively, and fed back to the input sides of adders 416 degrees and 421 degrees. The other side of comparators 420, 425 has inputs from counters 413, 426°.

The outputs of the latch circuits 419 and 424 are output to the adder 41, respectively.
It is fed back to the input side of 7,422.

The upper three bits of the decimal part output data of the circuit 430 and the upper three bits of the decimal part output data of the circuit 431 are taken out from the respective latch circuits 419 and 424 and supplied to the operation ROM 4J5 as an address designation signal. This R.O.
The pixel level before reduction is stored in M415. The output data read from the arithmetic ROM 415 is supplied to the input side of a comparator 432, and the other end of the comparator 432 is supplied with slice level data obtained from a slice level data excavator 433. The match signal of comparator 432 is applied to the D input terminal of flip-frog 434, and the output of AND gate 435 is applied to the clock terminal CL of the flip-frog. andf −) 4 J
One input terminal of 5 is supplied with the coincidence output XC0M of the comparator 420, and the other input terminal is supplied with the input YCOM from the comparator 425.

Here, the entire operation of the size conversion circuit 14 is described as follows.
This will be explained in detail using the figure. Assume that the reduction ratio specified by CPU 2 is 1/4.5. In this case, the integer part of the reduction ratio is 4, while the decimal part is 0.5. Each digitally formed numerical data is added to an adder 416.
, 417 and 421422.

In FIG. 10, the image dot positions of the original image are designated by the symbol "X", while the image dot positions of the size-converted image are designated by black dots.

The image dot at position (1, j) on the original image is (Pl, j), and the image dot at position (1, J) on the reduced image is (Q,,
, ) is defined.

The distance between two adjacent image dots of the original image is defined as one. Then, the distance between the two reduced dots on the original image is equal to the reduction rate R,.

L = Rr In this case, the constant R is set as 4.5. If an LXL region with center position Q,,,t- is designated as S, then the average gray level of S is the image driver belonging to region S) (
It is calculated based on the fact whether Pl,j) exists or not. Original position P1. j and the transformation position Qf, the distance t between J
rt,j, the average gray level φ11.
Totally calculated weighting factor α1. j is determined to be inversely proportional to the distance rt,j.

Therefore, the factor αl, J is 1 at the position of total Q, ,
, and set it as 0.5 at a position L/2 apart, the factor α1. ” can be displayed as .

Therefore, the average gray level φ09. Ha, it becomes. The transformed image dots Ql,J are then obtained by using a predetermined slice level θ.

Thus, the integer part 4 of the reduction ratio supplied from the CPU 2 is supplied to the latch circuit 418 through the adder 416. When the content of the counter 413 becomes 4, the match signal
C0M is sent out from comparator 420 and latch circuit 418
, 419 and an AND gate 435. On the other hand, the decimal part 0.5 is sent to the latch circuit 4 via the adder 4 no i.
It is latched at 19. Therefore, when the signal XC0M is supplied to the latch circuits 418 and 419, 0.5 + 0
．． An operation of 5=1 is performed in adder 417 and a carry of 1 is provided to adder 416. Therefore, 4+4+1
=9 is performed in the adder 416, and new data "
91 is set by the latch circuit 418. At this time, when the content of the counter 413 becomes 9, the output XC0M is obtained as the output of the comparator 420. Then, 9+4=13 is set in latch circuit 418.

Output XC0M is obtained when counter 413 reaches 13. At this time, the adder 416 performs an operation of 13+4+1, and new data "18" is set in the latch circuit 418.

In this way, the contents of the counter 413 become "4.9°13.1".
8.22.27. .

The same operation as circuit 430 is performed in circuit 431 as well. The output YCOM shows that the content of the counter 426 is "4".
．． 9.13.18.22.27. ...Every time it becomes 1,
It is supplied from comparator 425 to the other input of AND gate 435. When both inputs XC0M and YCOM are fed to AND gate 435, the output
is supplied to the clock terminal of At this time, the output level φ
1. ．． exceeds the output level of the slice level generator 433, the output is sent from the comparator 432 to the flip-flop f43.
The output QIJ of the black dot is obtained from the 7-rig flag 434 as shown in FIG.

In the enlargement operation, for example, an enlargement rate of 0.5 is
2 to adders 416 , 417 , 421 , and 422 . In this case, %QI, the number of J is 2 of the number of "P5"
The image information is magnified twice.

Next, FIG. 11 shows a display interface 15. A refresh memory 60 has a storage area of 1024 bits (X direction) x 1400 lines (Y direction). (CRT f″Isgray 161024
(has a display area of 700 bits x 700 lines). 61 is 1
The 6-bit register supplies the image information reduced and supplied by the size conversion circuit 14 to the refresh memory 60 every 16 bits. A selector 62 selects the output of the 16-bit register 61 or the pattern information from the four-turn generator 6. A write address counter 63 temporarily holds the image information write start address supplied from the CPU 2, divides it by 1716 of the size conversion circuit 14 (clock from the flip-flop f434 shown in FIG. By counting up the clock signal supplied through the AND circuit 65, the X-direction and Y-direction addresses of the refresh memory 60 are specified. Further, this write address counter 63 is supplied with a pattern information write address corresponding to a specific area at the lower right end of the refresh memory 60 from the CPU 2 when writing of the image information is completed. In this case, the other input terminal of the AND circuit 65 has CP
The IIO'' signal is provided from U2, which does not provide a clock signal to write address counter 63.

Reference numeral 66 denotes a CRT controller, which is composed of a counter 67, an address register 68, a 700-line inspection circuit 69, etc., and when reading 'bTb image information from the refresh memory 60, controls the CRT controller in the X and Y directions of the refresh memory 50. There are seven steps to specify the address. Here, the counter 62 consists of a 1/64 power counter 67m that counts a clock signal supplied from the excavation circuit 70 through a 1/16 counter 71t, and a counter 67b that performs a carry count of this counter 67a. Contents of counter 67a? Specify the address in the X direction, and specify the color y
The contents of 67b are 'tY direction, direction designation address.

Further, the address register 68 holds a read start address (line address) supplied from the CPU 2. The 700 line detection circuit 69 is
It detects whether the counter 67b has fully counted 1700#, and if it has counted 1700'', the counter 67b is set to all the start addresses of the address register 68. 22 is a selector for writing. It selects either the Y-direction specified address of the address counter 63 or the Y-direction specified address of the counter 67b at the time of writing and at the time of reading.73 is a selector, and the address counter 63 is selected at the time of writing and at the time of reading.
This selects either the X-direction designation address of the counter 67a or the X-direction designation address of the counter 67a. 74
is a 16-bit register which serially outputs 16-bit image information read out from the refresh memory 60 as a total clock signal output from the oscillation circuit 70.

80 is a cursor setting circuit, which is connected to the CRT controller 6 above.
A cursor video signal corresponding to a predetermined cursor (frame) is generated in synchronization with a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, and a clock signal from an excavation circuit 20, which are supplied from the CRT display 16 to the CRT display 16. Therefore, the cursor video signal generated from this cursor setting circuit 80 and the 16-bit register 7
The video signal outputted from the CRT f4 is supplied to the CRT f4 screen 16 via an OR circuit 200f.

Here, FIG. 12 shows the cursor setting circuit 80. In FIG. 12, reference numeral 81 denotes an X-direction cursor memory, which stores positional information @t on both left and right sides of the cursor in accordance with write code information J from the CPU 2. 82 is the Y direction cursor memory, CPU! The position information of the upper and lower sides of the cursor is held in accordance with the write code information J from '. 83 is an X-direction address counter which counts the clock signal shown in FIG. 14(a) (supplied from the excavation circuit 70 shown in FIG. 11). Reference numeral 84 denotes a Y-direction address counter, which counts the horizontal synchronizing signal Hiync t shown in the 14th axis) supplied from the CRT controller 66. 85 is a decoder, and when the contents of the counter 83 match the position information on both sides respectively, as shown in FIG. 14(c)
A decoder 86 outputs a logic ``1m'' signal shown in FIG. This is what is output. 87.88 is T-
14 (f) (g), respectively.
) Outputs each signal tone shown in the figure below. 89 is an OR circuit which outputs the signal shown in FIG. 14(1). 901.9
0. .

90 is an AND circuit, among which AND circuit 901
．． 90. outputs the signals shown in FIG. 14(e)). W is a pulling signal, and Cv is a cursor video signal.

On the other hand, in FIG. 13, a cursor key 92 is provided on the key gate 10. As shown in FIG. And 93°94.95.
Reference numeral 96 is a movement key, which emits a movement pulse while being pressed. C
The PU 2 detects this pulse and moves the image or cursor in the direction of the arrow. Reference numeral 92 denotes a movement key for moving the cursor or the display area of the CRT display gray 16 for image information in the flexible memory 60 to the upper left corner. 98 is an enlargement key, and 99 is a reduction key.

A complete explanation will be given of how image information is displayed in such a configuration.

When a document 8 is set on the two-dimensional scanning device 7, image information on the document is read and the size of the document is detected. Then, the read image information is stored in the page back memory 5 (with a size corresponding to each size as shown in FIG. 15). At this time, if the W draft size is B4, the CPU 2 Set the reduction rate of the conversion circuit 14 to 174. For A4, the reduction rate is 1/
3.3, B5, the reduction rate is set to 1/2.7, and if it is As, the reduction rate is set to 1/2. In this way, the image information in the page buffer 5 is reduced by the size conversion circuit 14 and stored in the refresh memory 60. When the image information is stored in the refresh memory 60, the CPU 2 reads a character pattern corresponding to the document size of the image information from the pattern generator 6, and adds it to a specific area of the image information in the refresh memory 60. therefore,
As shown in Figure 16 (&) (b) (e) (d),
Regardless of the document size, each piece of image information is displayed in its entirety on the CRT r4 display 16 at a constant size, and the display area of the CRT display 16 is utilized to the maximum extent possible. Furthermore, in this case, since the document size is added to the lower right portion of the displayed image information, the document size of each image information can be easily recognized. Note that if the page backup memory 5, refresh memory 60, and document 8 are used in landscape orientation, the image information is
CR as shown in Figure 7 (a) (b) (c) (d)
Since the image is displayed over the entire display area of the T-display 16, the display area can be used more effectively.

By the way, when such image information is displayed in its entirety, the reduction ratio for the image information is reduced to some extent, which poses a problem in terms of resolution.

Therefore, by operating all the cursor keys 92 of key date 10, the displayed image and cursor can be changed to PJ.
It is possible to move to a desired position, specify a desired image using the cursor in this state, and display the specified image in full enlargement.

In this case, the CPU 2 performs control according to the flowchart shown in FIG. In CPU 2, first, CRT
Core) "1#t" in the address register 68 of the roller 66
70 from line 1 of refresh memory 60.
Read up to line 0 and display it on the CRT f'' chair!ray 16 (step S1). That is, the 19th line
As shown in Figure (a), image information in the upper half area (solid line in the figure) of the refresh memory 60 is displayed. Also,
The CPUj sets the address of the cursor S in the cursor setting circuit 80 as shown by the dashed line in FIG. In this state, the movement key 9 of the cursor key 92
6 is turned on (step S2.S3.S4°B5)
, the CPU 2 increments the contents of the address register 68 of the CRT controller 66 by, for example, +10 (Stella 7'S6
). In this way, each time the movement key 96 is turned on, the display area for image information in the refresh memory 60 is changed to the 19th
As shown in Figures (b) and (e), it moves downward in sequence. In this case, there is no change in the corresponding position between the display area and the cursor S. Thereafter, when the Y-direction start address reaches 1700# (step S5), % cpu z is rewritten every time the Y-direction address of the cursor S in the cursor setting circuit 80 is turned on (step S7). . In this way, each time the movement key 96 is turned on, the cursor S moves downward as shown in FIG. 19(d) (,).

When the movement key 93 is turned on from this state (step S2.B3.B4.B8.B9), as shown in FIG.
d) The display area moves upward as shown in (c), and then the cursor S moves upward as shown in Fig. 20 (b) (SL) (step 810). )
If the movement key 95 is turned on in the state (step S2.
B3), in case there is no movement range in the display area, the cursor S moves to the right and becomes the state shown in FIG. 21(b) (step 511). Furthermore, if the movement key 94 is turned on in the state shown in FIG. 22(a) (steps S2 and B3), the cursor S
only moves to the left, resulting in the state shown in Figure 22(b) (
Stella fs11).

If the enlargement key 98 is turned on in such a display state, the image information within the cursor S is enlarged and displayed as a prayer. Moreover, if the reduction key 99 is turned on, the original display is made.

In this way, by specifying that the image information in the refresh memory 6o be moved by one entire area, the image information in the tail area can be displayed immediately. This eliminates the need for reading data from the image data, resulting in a significant improvement in display speed. Furthermore, by performing the display according to the movement specification, the reduction rate for the image information only needs to match the storage capacity of the refresh memory 60. It can be made larger, thereby increasing the resolution and making it easier to recognize.

Moreover, since the movement designation of the fixed amount area is given priority over the movement designation of the zoom-up area, one operation mechanism can be used for each movement designation, which is very convenient in practice.

In the above embodiment, priority is given to specifying the movement of a certain area, but priority may be given to all cursor movement specifications. In addition, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without changing the gist.

[Effects of the Invention] As described above, according to the present invention, it is possible to completely convert the image size so that the image can be displayed in the entire display area of the display unit, and the light display area of the display unit can be used effectively. We can provide all the excellent image display devices that can.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a storage area of a page buffer memory, FIG. 2 is a diagram showing an example of a display state of image information in FIG. 1, and FIG. 3 is an image information storage and retrieval device according to an embodiment of the present invention. 4 is a block diagram showing the full details of Figure 3, Figure 5 is a detailed diagram of the two-dimensional scanning device, and Figures 6 (a) and 6 (b) are Figure 5. The figure (IL) shows the circuit configuration diagram, the figure (b) shows the time chart, and Figure 7 shows the size detection section of Figure 5.
FIG. 8(a) is a plan configuration diagram, FIG. 8(b) is a circuit configuration diagram, FIG. 8 is a configuration diagram specifically showing a size conversion circuit in an embodiment of the present invention, and FIGS. 9 and 10 are FIG. 8 is a diagram for explaining the operation, FIG. 11 is a configuration diagram specifically showing the entire display interface in an embodiment of the present invention,
Fig. 12 is a block diagram specifically showing the entire cursor setting circuit in Fig. 11; Fig. 13 is a block diagram of the cursor keys;
Fig. 4 is a time chart for explaining the entire operation of Fig. 12, Fig. 15 is a configuration diagram showing the correspondence between the 4-jivanofa memory and image information of various sizes stored therein, and Fig. 16 (a) (b). ) (e) (d) and Figure 17 (a) (
b) (e) (d) are diagrams showing the entire display state of image information in one embodiment of the present invention, FIG. 18 is a flowchart showing display control in the same embodiment, and FIG. 19 (&)
(b) (e) (d) (e) IFigure 20 (a)
(b) (e) (d) (e), Figure 21 (a) (
b) and FIG. 22(b) are diagrams showing an example of image information and cursor display in the same embodiment. 2... CPU, 5... Target buffer memory, 6.
...Noya turn generator, 13... Image information display device, 14... Size conversion circuit, 15... Display interface, 16... CRT display, 60
...Refresh memory, 80...Cursor setting circuit, 92...Cursor key Fig. 1 Fig. 50 Fig. (a) (F-) Se? T7 Engraving of Figure 7 drawing (no change in content) Figure 9 Figure 10 Figure 13 Figure 14 = 2048 7 1 Hint Figure 15 Procedural amendment (method) % formula % 1. 63 No. 329744 2゜Title of the invention $19 Drawings, figures, omissions, and equipment 3゜Relationship with the person making the amendment

Claims (1)

[Scope of Claims] Reading means for reading images having various original sizes; optical storage means for storing images read by the reading means; and retrieval from the images read by the reading means or from the optical storage means. a page memory for temporarily storing the converted image; a conversion means for converting the size of the image stored in the page memory; a refresh memory for storing the image whose size has been converted by the conversion means; a display means having a display area for displaying an image read by the reading means or an image displayed on the display means regardless of the original size of the image read by the reading means or the image stored in the optical storage means; An image display comprising: control means for setting a size conversion rate by the conversion means so that the entire image is displayed in a substantially constant size and in substantially the entire display area of the display means; Device.