JPH05122932A - 1-transistor voltage resonance converter - Google Patents

1-transistor voltage resonance converter

Info

Publication number
JPH05122932A
JPH05122932A JP7641692A JP7641692A JPH05122932A JP H05122932 A JPH05122932 A JP H05122932A JP 7641692 A JP7641692 A JP 7641692A JP 7641692 A JP7641692 A JP 7641692A JP H05122932 A JPH05122932 A JP H05122932A
Authority
JP
Japan
Prior art keywords
voltage
fet1
semiconductor switching
winding
switching element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7641692A
Other languages
Japanese (ja)
Other versions
JP3081055B2 (en
Inventor
Tetsuya Matsumoto
哲也 松本
Kiyomi Watanabe
清美 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Origin Electric Co Ltd
Original Assignee
Origin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Origin Electric Co Ltd filed Critical Origin Electric Co Ltd
Priority to JP04076416A priority Critical patent/JP3081055B2/en
Publication of JPH05122932A publication Critical patent/JPH05122932A/en
Application granted granted Critical
Publication of JP3081055B2 publication Critical patent/JP3081055B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To reduce the switching loss of a semiconductor switching element such as FET by providing a time-constant circuit between the drive winding of a transformer and the semiconductor switching element and by turning ON the semiconductor switching element at the time when the value of drain voltage of the semiconductor switching element becomes zero. CONSTITUTION:When FET1 is turned ON, electric current flowing through the FET1 rises rectilinearly so that magnetic energy is stored in the exciting inductance of the primary winding N1 of a transformer T and the FET is turned OFF. When the FET1 is turned OFF, the exciting inductance of the primary side winding N1 and a capacitor C1 resonate and respective voltages of the primary side winding N1, secondary side winding N2 and drive winding N3 rise so that output current is supplied to a load 70. When the energy of the exciting inductance of the primary side winding N1 moves to the load side, the voltage of the primary side winding N1 changes in the zero direction and a time-constant circuit 60 turns ON the FET1 at the time when the drain current of the FET1 becomes zero.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は,直流電源電圧を半導体
スイッチング素子でオン,オフすることによって,共振
回路要素を有するトランスの出力巻線に交流電圧を発生
させ,この交流電圧を整流,平滑して所定の電圧を得る
一石電圧共振コンバータに関するものである。このコン
バータは,高効率が得られるので,たとえば,バッテリ
48Vを入力とし,進行波管のコレクタ電圧を得るポー
タブル形の衛星通信用電源に最適である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generates an AC voltage in an output winding of a transformer having a resonance circuit element by turning a DC power supply voltage on and off by a semiconductor switching element, and rectifies and smoothes this AC voltage. The present invention relates to a single-stone voltage resonant converter that obtains a predetermined voltage. Since this converter can obtain high efficiency, it is most suitable for a portable power supply for satellite communication which receives a collector voltage of a traveling wave tube, for example, using a battery of 48V as an input.

【0002】[0002]

【従来の技術】直流電源電圧を半導体スイッチング素子
でオン,オフすることによって,共振回路要素を有する
トランスの出力巻線に交流電圧を発生させ,この交流電
圧を整流,平滑して所定の電圧を得る共振コンバータと
しては,一石電圧共振形コンバータが知られている。
2. Description of the Related Art A semiconductor switching element turns on and off a direct-current power supply voltage to generate an alternating-current voltage in an output winding of a transformer having a resonance circuit element. The alternating-current voltage is rectified and smoothed to a predetermined voltage. As a resonant converter that can be obtained, a one-stone voltage resonant converter is known.

【0003】この従来の一石電圧共振形コンバータは,
共振動作によって半導体スイッチング素子であるMOS
FETのターンオン,ターンオフロスを減らし,効率を
向上させている。
This conventional one-stone voltage resonant converter is
MOS which is a semiconductor switching element by resonance operation
It reduces the turn-on and turn-off loss of the FET and improves the efficiency.

【0004】[0004]

【発明が解決しようとする課題】しかし,上記従来例に
おいては,他励式であるので,MOSFETのドレイン
電圧の零点を検出してそのターンオンのタイミングをと
らねばならず,したがって,共振モードで動作させるた
めの制御回路が複雑になるという問題がある。
However, in the above-mentioned conventional example, since it is of the separately excited type, it is necessary to detect the zero point of the drain voltage of the MOSFET to determine the turn-on timing thereof, and therefore operate in the resonance mode. There is a problem in that the control circuit for this becomes complicated.

【0005】本発明は,簡単な制御回路によって,FE
T等の半導体スイッチング素子のスイッチングロスを減
らすことができる自励式の一石電圧共振コンバータを提
供することを目的とするものである。
The present invention provides a FE with a simple control circuit.
An object of the present invention is to provide a self-excited one-wheel voltage resonant converter capable of reducing the switching loss of a semiconductor switching element such as T.

【0006】[0006]

【課題を解決するための手段】本発明は,直流電源と,
トランスの励磁インダクタンスと共振する共振コンデン
サと,半導体スイッチング素子と,この半導体スイッチ
ング素子と並列に接続されたダイオードと,整流・平滑
回路とを有し,上記半導体スイッチング素子をオン,オ
フすることによって,上記トランスの出力巻線に交流電
圧を発生させ,この交流電圧を上記整流・平滑回路によ
って整流,平滑して所定の電圧を得る共振コンバータに
おいて,上記トランスの駆動巻線と半導体スイッチング
素子の制御極との間に,所定の時定数回路を設け,この
時定数回路は,半導体スイッチング素子の両端電圧が零
になるタイミングで,その半導体スイッチング素子をオ
ンさせるものである。
The present invention comprises a DC power supply,
By having a resonant capacitor that resonates with the exciting inductance of the transformer, a semiconductor switching element, a diode connected in parallel with this semiconductor switching element, and a rectifying / smoothing circuit, by turning on and off the semiconductor switching element, In a resonant converter for generating an AC voltage in the output winding of the transformer and rectifying and smoothing the AC voltage by the rectifying / smoothing circuit to obtain a predetermined voltage, a drive winding of the transformer and a control pole of a semiconductor switching element. A predetermined time constant circuit is provided between and, and this time constant circuit turns on the semiconductor switching element at the timing when the voltage across the semiconductor switching element becomes zero.

【0007】[0007]

【実施例】図1は,本発明の一実施例を示す回路図であ
る。
FIG. 1 is a circuit diagram showing an embodiment of the present invention.

【0008】この実施例は,直流電源E1と,1次巻線
N1と2次巻線N2と駆動巻線N3とを有するトランス
Tと,トランスTの励磁インダクタンスと共振する共振
コンデンサC1と,この共振コンデンサC1と並列に接
続された半導体スイッチング素子としてのFET1とを
有する。
In this embodiment, a DC power source E1, a transformer T having a primary winding N1, a secondary winding N2 and a drive winding N3, a resonance capacitor C1 which resonates with the exciting inductance of the transformer T, and It has FET1 as a semiconductor switching element connected in parallel with the resonance capacitor C1.

【0009】また,起動回路10は,直流電源E1の投
入時に,電源E1の電圧Eが所定値に達したときにFE
T1を起動させる回路であり,トランジスタT2,T3
を有し,直流電源E1の投入時にその電圧Eが所定値に
達していないときにトランジスタT3がオフし,トラン
ジスタT2がオンするように設定されている。
Further, the starting circuit 10 is arranged so that when the DC power source E1 is turned on, when the voltage E of the power source E1 reaches a predetermined value, the FE
A circuit for starting T1, which includes transistors T2 and T3
The transistor T3 is turned off and the transistor T2 is turned on when the voltage E does not reach a predetermined value when the DC power source E1 is turned on.

【0010】ピーク電流検出回路20は,FET1がオ
ンしているときにFET1に流れる電流のピーク値を検
出する回路であり,FET1と直列に接続された電流検
出抵抗R9と,抵抗R10とコンデンサC3とで構成さ
れる時定数回路とを有する。この時定数回路は,いわゆ
るヒゲ等のノイズ成分を除去するものである。なお,ピ
ーク電流検出回路20の代りに変流器を使用してもよ
い。
The peak current detection circuit 20 is a circuit for detecting the peak value of the current flowing through the FET1 when the FET1 is on, and the current detection resistor R9, the resistor R10 and the capacitor C3 connected in series with the FET1. And a time constant circuit configured by. This time constant circuit removes noise components such as so-called beard. A current transformer may be used instead of the peak current detection circuit 20.

【0011】駆動回路30は,検出された上記ピーク電
流の値が所定値に達したときにFET1をオフさせる回
路であり,等価的にサイリスタと同一に接続されたPN
PトランジスタT4とNPNトランジスタT5と抵抗R
7,R8とを有する。
The drive circuit 30 is a circuit for turning off the FET 1 when the detected peak current value reaches a predetermined value, and is equivalently connected to a thyristor in a PN circuit.
P transistor T4, NPN transistor T5 and resistor R
7 and R8.

【0012】出力電圧の誤差検出回路40は,倍電圧整
流回路50によって整流,平滑された直流電圧(出力電
圧)を基準電圧源E2の電圧と比較して出力電圧の誤差
電圧を検出し,この検出された誤差をバイアスとして駆
動回路30に与える回路であり,出力電圧を分割する抵
抗R11,R12と,基準電圧源E2と,差動増幅器A
MPとを有する。差動増幅器AMPは,抵抗R11,R
12による分圧値と基準電圧源E2の値との差(出力電
圧の誤差)を出力する増幅器である。
The output voltage error detection circuit 40 detects the error voltage of the output voltage by comparing the DC voltage (output voltage) rectified and smoothed by the voltage doubler rectifier circuit 50 with the voltage of the reference voltage source E2. A circuit for applying the detected error as a bias to the drive circuit 30, resistors R11 and R12 for dividing the output voltage, a reference voltage source E2, and a differential amplifier A.
With MP. The differential amplifier AMP includes resistors R11 and R
It is an amplifier that outputs the difference (error in output voltage) between the divided voltage value by 12 and the value of the reference voltage source E2.

【0013】さらに,時定数回路60は,トランスTの
駆動巻線N3とFET1のゲートとの間に設けられ,抵
抗RgとFET1のゲート入力容量Cgとで構成され,
FET1のドレイン電圧(両端電圧)が零のタイミング
で,そのFET1をオンさせるように設定されている。
実際には,時定数回路60は,抵抗Rgとゲート入力容
量Cgとの他に,直流カット用のコンデンサC2とで構
成されている。なお,ゲート入力容量Cgと並列に接続
されているツェナーダイオードZDは,駆動巻線N3に
発生した逆電流を放電させるループを形成すると共に,
FET1のゲートを保護するものである。駆動巻線N3
に発生した逆電流を放電させるためだけならば,ツェナ
ーダイオードZDの代わりに,通常のダイオードを使用
してもよい。
Further, the time constant circuit 60 is provided between the drive winding N3 of the transformer T and the gate of the FET1, and is composed of a resistor Rg and a gate input capacitance Cg of the FET1.
The FET1 is set to turn on at the timing when the drain voltage (voltage across both ends) of the FET1 is zero.
In practice, the time constant circuit 60 is composed of a resistor Rg, a gate input capacitance Cg, and a DC cut capacitor C2. The Zener diode ZD connected in parallel with the gate input capacitance Cg forms a loop for discharging the reverse current generated in the drive winding N3, and
It protects the gate of the FET1. Drive winding N3
A normal diode may be used instead of the Zener diode ZD only for discharging the reverse current generated in the above.

【0014】また,FET1はその内部にダイオード成
分を有しているので,FET1と並列にダイオードを接
続する必要はないが,内部にダイオード成分を有しない
半導体スイッチング素子(トランジスタ,静電誘導トラ
ンジスタ等の素子)を使用する場合には,その半導体ス
イッチング素子と並列にダイオードを接続する必要があ
る。
Further, since FET1 has a diode component inside, it is not necessary to connect a diode in parallel with FET1, but a semiconductor switching element (transistor, static induction transistor, etc.) having no diode component inside is provided. Element), it is necessary to connect a diode in parallel with the semiconductor switching element.

【0015】さらに,上記実施例においては,Vo>n
・2・Eになるように,トランスTの2次巻数と1次巻
数との比である巻数比nを設定してある。なお,Voは
出力電圧を示し,Eは電源E1の電圧を示している。
Further, in the above embodiment, Vo> n
The winding ratio n, which is the ratio between the secondary winding number and the primary winding number of the transformer T, is set so as to be 2.E. Note that Vo indicates the output voltage, and E indicates the voltage of the power supply E1.

【0016】次に,上記実施例の動作について説明す
る。
Next, the operation of the above embodiment will be described.

【0017】図2は,上記実施例におけるタイムチャー
トである。
FIG. 2 is a time chart in the above embodiment.

【0018】まず,起動時に,電源E1の電圧が低い場
合には,トランジスタT3がオフし,トランジスタT2
がオンし,FET1がオフしている。この状態から電源
E1の電圧が次第に上昇し,所定の値に達すると,トラ
ンジスタT3がオンし,トランジスタT2がオフし,起
動抵抗R1を介してFET1のゲートが充電され,FE
T1がオンし始める。なお,抵抗R5は,トランジスタ
T2のコレクタからトランジスタT3のベースに正帰還
をかけて,オン,オフ動作を高速化するための抵抗であ
る。
First, at startup, if the voltage of the power source E1 is low, the transistor T3 is turned off and the transistor T2 is turned on.
Is on and FET1 is off. From this state, when the voltage of the power source E1 gradually rises and reaches a predetermined value, the transistor T3 is turned on, the transistor T2 is turned off, the gate of the FET1 is charged through the starting resistor R1, and the FE
T1 begins to turn on. The resistor R5 is a resistor for performing positive feedback from the collector of the transistor T2 to the base of the transistor T3 to speed up on / off operation.

【0019】FET1がオンし始めると,1次巻線N1
の黒点側を+として電源E1の電圧が1次側巻線N1に
印加され,駆動巻線N3にも黒点側を+とする電圧が発
生し,コンデンサC2,抵抗Rgを介してFET1のゲ
ートに正帰還がかかり,FET1が完全にオンする。こ
のときにFET1を流れる電流は,0からほぼ直線的に
上昇する。FET1がオンしている間(t0−t1の
間),2次側巻線N2には黒点を+としてほぼnEの電
圧が発生し,図示の極性でコンデンサC4をnEに充電
する。同時に,1次側巻線N1の励磁インダクタンスに
磁気エネルギーが蓄えられる。このFET1の電流は,
電流検出抵抗R9で検出され,この電流が増加すると,
抵抗R10を介してトランジスタT5のベースに流れる
電流が増加し,トランジスタT5がオンする。
When the FET1 starts to turn on, the primary winding N1
The voltage of the power source E1 is applied to the primary winding N1 with the black dot side of + as +, and a voltage with + on the black dot side is also generated in the drive winding N3, and is applied to the gate of FET1 via the capacitor C2 and the resistor Rg. Positive feedback is applied and FET1 is completely turned on. At this time, the current flowing through the FET1 rises almost linearly from zero. While FET1 is on (between t0 and t1), a voltage of approximately nE is generated in the secondary winding N2 with the black dot as +, and the capacitor C4 is charged to nE with the polarity shown. At the same time, magnetic energy is stored in the exciting inductance of the primary winding N1. The current of this FET1 is
It is detected by the current detection resistor R9, and if this current increases,
The current flowing to the base of the transistor T5 via the resistor R10 increases, and the transistor T5 turns on.

【0020】トランジスタT5がオンすると,トランジ
スタT4もオンし,トランジスタT5,T4が互いにオ
ン状態を保持して,FET1のゲート電荷を放電し,F
ET1が高速でターンオフする。FET1がオフする
と,駆動巻線N3の電圧が反転するので,コンデンサC
2,抵抗Rg,R9を介して,トランジスタT5,T4
に逆バイアスがかかり,トランジスタT5,T4がオフ
し,FET1の次のターンオンに備える。
When the transistor T5 is turned on, the transistor T4 is also turned on, the transistors T5 and T4 are kept in the on state with each other, the gate charge of the FET1 is discharged, and F
ET1 turns off at high speed. When the FET1 is turned off, the voltage of the drive winding N3 is inverted, so that the capacitor C
2. Transistors T5 and T4 via resistors Rg and R9
Is reverse-biased, the transistors T5 and T4 are turned off, and the next turn-on of the FET1 is prepared.

【0021】FET1がオフすると,1次側巻線N1の
励磁インダクタンスとコンデンサC1とが共振し,1次
側巻線N1,2次側巻線N2,駆動巻線N3の各電圧が
非黒点を正として上昇し,2次側巻線N2の電圧とコン
デンサC4の電圧との和が出力電圧V0を越えると,ダ
イオードD2がオンし,出力電流を供給する。したがっ
て,このときの2次側巻線N2の電圧はV0−n・E,
1次側巻線N1の電圧は(Vo/n)−Eであり,FE
T1のドレイン電圧は,電源E1の電圧Eと1次側巻線
N1の電圧との和であるから,Vo/nである。
When the FET1 is turned off, the exciting inductance of the primary winding N1 and the capacitor C1 resonate, and each voltage of the primary winding N1, the secondary winding N2 and the drive winding N3 shows a non-black dot. When the voltage rises as a positive value and the sum of the voltage of the secondary winding N2 and the voltage of the capacitor C4 exceeds the output voltage V0, the diode D2 turns on and supplies the output current. Therefore, the voltage of the secondary winding N2 at this time is V0-n · E,
The voltage of the primary winding N1 is (Vo / n) -E, and
The drain voltage of T1 is Vo / n because it is the sum of the voltage E of the power supply E1 and the voltage of the primary winding N1.

【0022】1次側巻線N1の励磁インダクタンスのエ
ネルギーが負荷側に移り,ダイオードD2がオフする
と,1次側巻線N1の電圧は零方向に変化する。1次側
巻線N1の共振電圧が,黒点側を+として電源E1の電
圧Eと等しくなったときに,FET1のドレイン電圧が
零になる。また,時定数回路60は,上記のようにFE
T1のドレイン電圧が零になるタイミングでFET1に
ゲート電圧を与え,したがって,FET1のドレイン電
圧が零になった後にFET1がターンオンする。このよ
うに,FET1のドレイン電圧が零になるタイミングで
FET1がターンオンするので,理論的には,FET1
のターンオンロスが生じない。
When the energy of the exciting inductance of the primary winding N1 moves to the load side and the diode D2 is turned off, the voltage of the primary winding N1 changes in the zero direction. When the resonance voltage of the primary winding N1 becomes equal to the voltage E of the power source E1 with the black dot side as +, the drain voltage of the FET1 becomes zero. In addition, the time constant circuit 60 uses the FE as described above.
The gate voltage is applied to the FET1 at the timing when the drain voltage of T1 becomes zero, so that the FET1 turns on after the drain voltage of the FET1 becomes zero. Thus, since the FET1 is turned on at the timing when the drain voltage of the FET1 becomes zero, theoretically, the FET1
No turn-on loss occurs.

【0023】また,時刻t2で,1次側巻線N1の電圧
が電源E1の電圧Eよりも大きくなり,このときに,F
ET1の電圧は負になる筈であるが,FET1内にダイ
オード成分が存在するので,FET1の電圧がほぼ0V
(ダイオードの順電圧分−0.6V)になる。このよう
にFET1の電圧がほぼ0Vであるときに,FET1の
ゲート電圧がその閾値を越えるように,時定数回路60
の時定数を設定すれば,ターンオン損失が無い共振動作
が行なわれる。なお,図2において,FET1の電流の
うちで負の成分は,FET1内のダイオードに流れる電
流を示したものである。
At time t2, the voltage of the primary winding N1 becomes larger than the voltage E of the power source E1. At this time, F
The voltage of ET1 should be negative, but since the diode component exists in FET1, the voltage of FET1 is almost 0V.
(Forward voltage of diode is -0.6 V). Thus, when the voltage of the FET1 is almost 0V, the time constant circuit 60 is set so that the gate voltage of the FET1 exceeds the threshold value.
By setting the time constant of, resonant operation without turn-on loss is performed. In FIG. 2, the negative component of the current of the FET1 indicates the current flowing through the diode in the FET1.

【0024】ところで,負荷70の変化に応じて出力電
圧も変化し,この出力電圧の変化を誤差として誤差検出
回路40が出力し,駆動回路30のトランジスタT5に
バイアス電流を流す。つまり,出力電圧が設定値よりも
高くなれば,その高くなった分に応じてバイアス電流が
多くなり,トランジスタT5,T4がオンするタイミン
グが早くなり,FET1がターンオフするタイミングも
早くなる。したがって,FET1のオン時間が短くな
り,出力電圧が低下する方向に制御される。これとは逆
に,出力電圧が設定値よりも低くなれば,その低くなっ
た分に応じてバイアス電流が少なくなり,トランジスタ
T5,T4がオンするタイミングが遅くなり,FET1
がターンオフするタイミングも遅くなる。したがって,
FET1のオン時間が長くなり,出力電圧が上昇する方
向に制御される。このようにして,出力電圧の値が設定
値に自動制御される。
By the way, the output voltage also changes in accordance with the change of the load 70, and the error detection circuit 40 outputs the change of the output voltage as an error, and the bias current flows through the transistor T5 of the drive circuit 30. That is, when the output voltage becomes higher than the set value, the bias current increases in accordance with the increase, the timing at which the transistors T5 and T4 turn on becomes earlier, and the timing at which the FET1 turns off also becomes earlier. Therefore, the ON time of the FET1 is shortened, and the output voltage is controlled to decrease. On the contrary, when the output voltage becomes lower than the set value, the bias current decreases according to the lowering value, the timing of turning on the transistors T5 and T4 is delayed, and the FET1
Will turn off later. Therefore,
The on-time of the FET1 becomes longer and the output voltage is controlled to increase. In this way, the output voltage value is automatically controlled to the set value.

【0025】なお,出力電圧の設定値を高くするには,
誤差検出回路40内の基準電源E2の電圧値を大きくす
ればよい。逆に,出力電圧の設定値を低くするには,基
準電源E2の電圧値を小さくすればよい。
In order to increase the set value of the output voltage,
The voltage value of the reference power supply E2 in the error detection circuit 40 may be increased. On the contrary, in order to lower the set value of the output voltage, the voltage value of the reference power source E2 may be decreased.

【0026】なお,倍電圧整流回路の段数がmである場
合には,Vo>n・m・2・Eになるように,巻数比n
を設定すれば共振モードが保証される。また,倍電圧整
流回路50の代りに,半波整流回路,両波整流回路を使
用してもよい。半波整流回路を使用した場合には,Vo
>n・Eになるように,巻数比nを設定すればよく,両
波整流回路を使用した場合には,Vo>2・n・Eにな
るように,巻数比nを設定すればよい(Voは出力電圧
であり,Eは直流電源E1の電圧である)。実際の電源
では,電源電圧変動があるので,最低入力電圧を,電源
E1の電圧Eに選択する必要がある。
When the number of stages of the voltage doubler rectifier circuit is m, the winding ratio n is adjusted so that Vo> n · m · 2 · E.
By setting, the resonance mode is guaranteed. Further, instead of the voltage doubler rectifier circuit 50, a half-wave rectifier circuit or a double-wave rectifier circuit may be used. If a half-wave rectifier circuit is used, Vo
The winding ratio n may be set so that> n · E, and when the double-wave rectifier circuit is used, the winding ratio n may be set so that Vo> 2 · n · E ( Vo is the output voltage, and E is the voltage of the DC power supply E1). In an actual power supply, since the power supply voltage fluctuates, it is necessary to select the lowest input voltage as the voltage E of the power supply E1.

【0027】次に,図3は駆動回路30をFET1のゲ
ートに直接接続することにより,図1の実施例に比べて
FET1のターンオフを速めることのできる別の実施例
である。
Next, FIG. 3 shows another embodiment in which the drive circuit 30 is directly connected to the gate of the FET 1 so that the turn-off of the FET 1 can be accelerated as compared with the embodiment of FIG.

【0028】また,上記実施例では共振コンデンサC1
をFET1に並列接続しているが,コンデンサC1を設
ける代わりに,図1及び図3に破線で示すように,1次
側巻線N1と並列にコンデンサC1aを接続するように
しても,原理的には同一である。
In the above embodiment, the resonance capacitor C1
Is connected in parallel to the FET1, but instead of providing the capacitor C1, the capacitor C1a may be connected in parallel with the primary winding N1 as shown by the broken lines in FIGS. 1 and 3 in principle. Are the same.

【0029】[0029]

【発明の効果】本発明によれば,共振コンバータにおい
て,FET等の半導体スイッチング素子のターンオンロ
スを低下させる場合,共振モードで動作させるための制
御回路を簡単にすることができるという効果を奏する。
According to the present invention, in the resonance converter, when the turn-on loss of the semiconductor switching element such as the FET is reduced, the control circuit for operating in the resonance mode can be simplified.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing an embodiment of the present invention.

【図2】上記実施例におけるタイムチャートである。FIG. 2 is a time chart in the above embodiment.

【図3】本発明の他の一実施例を示す回路図である。FIG. 3 is a circuit diagram showing another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

C1…共振用コンデンサ T…トランス E1…直流電源 1…FET 10…起動回路 20…ピーク電流検出回路 30…駆動回路 40…出力電圧の誤差検出回路 50…倍電圧整流回路 60…時定数回路 C1 ... Resonance capacitor T ... Transformer E1 ... DC power supply 1 ... FET 10 ... Start-up circuit 20 ... Peak current detection circuit 30 ... Drive circuit 40 ... Output voltage error detection circuit 50 ... Double voltage rectification circuit 60 ... Time constant circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 直流電源と,トランスの励磁インダクタ
ンスと共振する共振コンデンサと,上記トランスの入力
巻線と直列に接続された半導体スイッチング素子と,整
流・平滑回路とを有し,上記半導体スイッチング素子を
オン,オフすることによって,上記トランスの出力巻線
に交流電圧を発生させ,この交流電圧を整流,平滑して
所定の電圧を得る共振コンバータにおいて, 上記半導体スイッチング素子が上記トランスの入力巻線
と直列に接続され,上記トランスが駆動巻線を有し,上
記駆動巻線と上記半導体スイッチング素子の制御極との
間に所定の時定数回路を設け,この時定数回路は,上記
半導体スイッチング素子の両端電圧がほぼ零になるタイ
ミングで上記半導体スイッチング素子をオンさせるもの
であることを特徴とする一石電圧共振コンバータ。
1. A semiconductor switching device comprising a DC power supply, a resonance capacitor that resonates with an exciting inductance of a transformer, a semiconductor switching device connected in series with an input winding of the transformer, and a rectifying / smoothing circuit. By turning on and off, an AC voltage is generated in the output winding of the transformer, the AC converter is rectified and smoothed to obtain a predetermined voltage. In the resonant converter, the semiconductor switching element is an input winding of the transformer. And the transformer has a drive winding, and a predetermined time constant circuit is provided between the drive winding and the control pole of the semiconductor switching element. The time constant circuit is the semiconductor switching element. It is characterized in that the semiconductor switching element is turned on at the timing when the voltage across both ends becomes almost zero. And compression common vibration converter.
JP04076416A 1991-03-01 1992-02-27 One-stone voltage resonance converter Expired - Lifetime JP3081055B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04076416A JP3081055B2 (en) 1991-03-01 1992-02-27 One-stone voltage resonance converter

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP5968291 1991-03-01
JP3-59682 1991-03-01
JP04076416A JP3081055B2 (en) 1991-03-01 1992-02-27 One-stone voltage resonance converter

Publications (2)

Publication Number Publication Date
JPH05122932A true JPH05122932A (en) 1993-05-18
JP3081055B2 JP3081055B2 (en) 2000-08-28

Family

ID=26400755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04076416A Expired - Lifetime JP3081055B2 (en) 1991-03-01 1992-02-27 One-stone voltage resonance converter

Country Status (1)

Country Link
JP (1) JP3081055B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009229102A (en) * 2008-03-19 2009-10-08 Nec Microwave Inc Current measurement device, voltage measuring device, and power supply device with the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009229102A (en) * 2008-03-19 2009-10-08 Nec Microwave Inc Current measurement device, voltage measuring device, and power supply device with the same

Also Published As

Publication number Publication date
JP3081055B2 (en) 2000-08-28

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