JPH04322162A - Voltage resonance converter - Google Patents

Abstract

PURPOSE:To reduce a switching loss of a semiconductor switching element such as a FET, etc., by providing a predetermined time constant circuit between a driving winding and a control pole of the element, and turning ON the element at the timing in which a voltage at both terminals of the element becomes substantially zero. CONSTITUTION:A time constant circuit 60 is provided between a driving winding N3 of a transformer T and a gate of a FET 1. A semiconductor switching element FET is turned ON and OFF thereby to generate an AC voltage at an output winding of a transformer, and the AC voltage is rectified and smoothed to obtain a predetermined voltage. In this case, if a time constant of the circuit 60 is so set that the gate voltage of the FET 1 exceeds its threshold value when the voltage of the FET 1 is substantially 0V, a resonance operation having no turning ON loss is performed.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention generates an alternating current voltage in the output winding of a transformer having a resonant circuit element by turning on and off a direct current power supply voltage using a semiconductor switching element, and rectifies and smooths this alternating voltage. This invention relates to a voltage resonant converter that obtains a predetermined voltage. This converter has high efficiency, so for example, the battery 48
It is ideal for a portable satellite communication power supply that takes V as an input and obtains the collector voltage of a traveling wave tube.

0002

[Prior Art] By turning a DC power supply voltage on and off using a semiconductor switching element, an AC voltage is generated in the output winding of a transformer having a resonant circuit element, and this AC voltage is rectified and smoothed to produce a predetermined voltage. As a resonant converter that can be obtained, a single-channel voltage resonant converter is known.

[0003] This conventional single-stone voltage resonant converter is
MOS, which is a semiconductor switching element due to resonance operation
It reduces FET turn-on and turn-off losses and improves efficiency.

0004

[Problems to be Solved by the Invention] However, in the above conventional example, since it is a separately excited type, it is necessary to detect the zero point of the drain voltage of the MOSFET to determine the turn-on timing, and therefore the MOSFET is operated in a resonance mode. There is a problem that the control circuit for this becomes complicated.

[0005] The present invention enables the FE to be controlled by a simple control circuit.
It is an object of the present invention to provide a self-excited voltage resonant converter that can reduce switching loss of semiconductor switching elements such as T-type semiconductor switching elements.

[0006]

[Means for Solving the Problems] The present invention provides a direct current power supply,
It has a resonant capacitor that resonates with the excitation inductance of the transformer, a semiconductor switching element, a diode connected in parallel with the semiconductor switching element, and a rectification/smoothing circuit, and by turning on and off the semiconductor switching element, In the resonant converter, an alternating current voltage is generated in the output winding of the transformer, and the alternating current voltage is rectified and smoothed by the rectifying/smoothing circuit to obtain a predetermined voltage. A predetermined time constant circuit is provided between the semiconductor switching element and the semiconductor switching element, and this time constant circuit turns on the semiconductor switching element at the timing when the voltage across the semiconductor switching element becomes zero.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing an embodiment of the present invention.

This embodiment includes a DC power source E1, a transformer T having a primary winding N1, a secondary winding N2, and a drive winding N3, a resonant capacitor C1 that resonates with the excitation inductance of the transformer T, and It has a resonance capacitor C1 and an FET1 as a semiconductor switching element connected in parallel.

[0009] Furthermore, when the DC power supply E1 is turned on, the startup circuit 10 turns on the FE when the voltage E of the power supply E1 reaches a predetermined value.
This is a circuit that starts T1, and transistors T2 and T3
The transistor T3 is turned off and the transistor T2 is turned on when the voltage E of the DC power supply E1 does not reach a predetermined value when the DC power supply E1 is turned on.

The peak current detection circuit 20 is a circuit that detects the peak value of the current flowing through the FET1 when the FET1 is on, and includes a current detection resistor R9 connected in series with the FET1, a resistor R10, and a capacitor C3. and a time constant circuit. This time constant circuit removes noise components such as so-called whiskers. Note that a current transformer may be used instead of the peak current detection circuit 20.

The drive circuit 30 is a circuit that turns off the FET 1 when the detected peak current value reaches a predetermined value, and is equivalent to a PN connected to the thyristor.
P transistor T4, NPN transistor T5 and resistor R
7, R8.

The output voltage error detection circuit 40 compares the DC voltage (output voltage) rectified and smoothed by the voltage doubler rectifier circuit 50 with the voltage of the reference voltage source E2 to detect an error voltage in the output voltage. This circuit provides the detected error as a bias to the drive circuit 30, and includes resistors R11 and R12 that divide the output voltage, a reference voltage source E2, and a differential amplifier A.
It has MP. The differential amplifier AMP has resistors R11, R
This amplifier outputs the difference (output voltage error) between the voltage divided by E.12 and the value of the reference voltage source E2.

Furthermore, the time constant circuit 60 is provided between the drive winding N3 of the transformer T and the gate of the FET1, and is composed of a resistor Rg and a gate input capacitance Cg of the FET1.
The FET 1 is set to be turned on at the timing when the drain voltage (voltage at both ends) of the FET 1 is zero. In reality, the time constant circuit 60 includes a resistor Rg, a gate input capacitor Cg, and a DC cut capacitor C2. Note that the Zener diode ZD connected in parallel with the gate input capacitance Cg forms a loop that discharges the reverse current generated in the drive winding N3, and
This protects the gate of FET1. Drive winding N3
An ordinary diode may be used instead of the Zener diode ZD if the purpose is only to discharge the reverse current generated.

Furthermore, since FET1 has a diode component inside, there is no need to connect a diode in parallel with FET1, but it is possible to connect a semiconductor switching element (transistor, static induction transistor, etc.) that does not have a diode component inside. When using a semiconductor switching element), it is necessary to connect a diode in parallel with the semiconductor switching element.

Furthermore, in the above embodiment, Vo>n
The turns ratio n, which is the ratio between the number of secondary turns and the number of primary turns of the transformer T, is set so that ・2・E. Note that Vo indicates the output voltage, and E indicates the voltage of the power source E1.

Next, the operation of the above embodiment will be explained.

FIG. 2 is a time chart in the above embodiment.

First, at startup, if the voltage of the power supply E1 is low, the transistor T3 is turned off, and the transistor T2 is turned off.
is on and FET1 is off. From this state, the voltage of the power supply E1 gradually increases and when it reaches a predetermined value, the transistor T3 is turned on, the transistor T2 is turned off, the gate of FET1 is charged via the starting resistor R1, and the FE
T1 starts to turn on. Note that the resistor R5 is a resistor for applying positive feedback from the collector of the transistor T2 to the base of the transistor T3 to speed up the on/off operation.

When FET1 starts to turn on, the primary winding N1
The voltage of the power supply E1 is applied to the primary winding N1 with the black dot side set to +, and a voltage with the black dot side set to + is also generated in the drive winding N3, which is applied to the gate of FET1 via the capacitor C2 and resistor Rg. Positive feedback is applied and FET1 is completely turned on. At this time, the current flowing through FET1 increases almost linearly from 0. While the FET1 is on (between t0 and t1), a voltage of approximately nE is generated in the secondary winding N2, with the black dot being positive, and the capacitor C4 is charged to nE with the polarity shown. At the same time, magnetic energy is stored in the excitation inductance of the primary winding N1. This current of FET1 is detected by current detection resistor R9, and when this current increases, the current flowing to the base of transistor T5 via resistor R10 increases, turning on transistor T5.

When the transistor T5 is turned on, the transistor T4 is also turned on, and the transistors T5 and T4 keep each other on, discharging the gate charge of the FET1, and discharging the gate charge of the FET1.
ET1 turns off at high speed. When FET1 turns off, the voltage of drive winding N3 is reversed, so capacitor C2
, the transistors T5 and T4 are reverse biased through the resistors Rg and R9, and the transistors T5 and T4 are turned off in preparation for the next turn-on of the FET1.

When FET1 is turned off, the excitation inductance of the primary winding N1 and the capacitor C1 resonate, and the voltages of the primary winding N1, secondary winding N2, and drive winding N3 reach the non-black point. When the sum of the voltage across the secondary winding N2 and the voltage across the capacitor C4 exceeds the output voltage V0, the diode D2 turns on and supplies an output current. Therefore, the voltage of the secondary winding N2 at this time is V0-n・E,
The voltage of the primary winding N1 is (Vo/n)-E, and FE
The drain voltage of T1 is the sum of the voltage E of the power source E1 and the voltage of the primary winding N1, so it is Vo/n.

When the energy of the excitation inductance of the primary winding N1 is transferred to the load side and the diode D2 is turned off, the voltage of the primary winding N1 changes toward zero. When the resonant voltage of the primary winding N1 becomes equal to the voltage E of the power source E1 with the black dot side being +, the drain voltage of the FET 1 becomes zero. Further, the time constant circuit 60 is configured using an FET as described above.
A gate voltage is applied to FET 1 at the timing when the drain voltage of FET 1 becomes zero, and therefore, FET 1 is turned on after the drain voltage of FET 1 becomes zero. In this way, at the timing when the drain voltage of FET1 becomes zero, F
Since ET1 is turned on, theoretically, no turn-on loss of FET1 occurs.

Further, at time t2, the voltage of the primary winding N1 becomes larger than the voltage E of the power supply E1, and at this time, F
The voltage of ET1 should be negative, but since there is a diode component in FET1, the voltage of FET1 is almost 0V.
(Diode forward voltage -0.6V). In this way, when the voltage of FET1 is approximately 0V, the time constant circuit 60 is configured so that the gate voltage of FET1 exceeds the threshold value.
By setting the time constant of , resonant operation without turn-on loss is performed. Note that in FIG. 2, the negative component of the current of FET1 indicates the current flowing through the diode within FET1.

By the way, the output voltage also changes in response to changes in the load 70, and the error detection circuit 40 outputs this change in output voltage as an error, causing a bias current to flow through the transistor T5 of the drive circuit 30. In other words, when the output voltage becomes higher than the set value, the bias current increases accordingly, the timing at which the transistors T5 and T4 turn on becomes earlier, and the timing at which the FET1 turns off also becomes earlier. Therefore, the ON time of FET1 is shortened, and the output voltage is controlled to decrease. Conversely, if the output voltage becomes lower than the set value, the bias current decreases accordingly, and the transistor T
5. The timing at which T4 is turned on is delayed, and the timing at which FET1 is turned off is also delayed. Therefore, F
The ON time of ET1 becomes longer, and the output voltage is controlled to increase. In this way, the value of the output voltage is automatically controlled to the set value.

[0025] In order to increase the set value of the output voltage,
The voltage value of the reference power supply E2 in the error detection circuit 40 may be increased. Conversely, in order to lower the set value of the output voltage, the voltage value of the reference power source E2 may be lowered.

Note that when the number of stages of the voltage doubler rectifier circuit is m, the turns ratio n is set so that Vo>n・m・2・E.
Setting , the resonance mode is guaranteed. Furthermore, instead of the voltage doubler rectifier circuit 50, a half-wave rectifier circuit or a double-wave rectifier circuit may be used. When using a half-wave rectifier circuit, Vo
The turns ratio n should be set so that Vo>n・E. If a double-wave rectifier circuit is used, the turns ratio n should be set so that Vo>2・n・E ( Vo is the output voltage and E is the voltage of the DC power supply E1). In an actual power supply, since there is a power supply voltage fluctuation, it is necessary to select the lowest input voltage as the voltage E of the power supply E1.

Furthermore, in the above embodiment, the resonant capacitor C1
is connected in parallel to FET1, but instead of providing capacitor C1, the primary winding N
Even if the capacitor C1a is connected in parallel with 1,
They are the same in principle.

[0028]

According to the present invention, in a resonant converter, when the turn-on loss of a semiconductor switching element such as an FET is reduced, the control circuit for operating in a resonant mode can be simplified.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a time chart in the above embodiment.

[Explanation of symbols]

C1...resonance capacitor, T...Trance, E1...DC power supply, 1...FET, 10...Starting circuit, 20...Peak current detection circuit, 30...drive circuit, 40...Output voltage error detection circuit, 50...voltage doubler rectifier circuit, 60...Time constant circuit.

Claims (1)

[Claims] 1. A DC power supply, a resonant capacitor that resonates with the excitation inductance of the transformer, and a semiconductor switching element connected in series with the input winding of the transformer,
a resonant converter, which has a rectifier/smoothing circuit, generates an alternating current voltage in the output winding of the transformer by turning on and off the semiconductor switching element, rectifies and smoothes the alternating voltage to obtain a predetermined voltage; wherein the semiconductor switching element is connected in series with an input winding of the transformer, the transformer has a drive winding, and a predetermined time constant circuit is provided between the drive winding and a control pole of the semiconductor switching element. A voltage resonant converter characterized in that the time constant circuit turns on the semiconductor switching element at a timing when the voltage across the semiconductor switching element becomes approximately zero.