JPH05122182A - Signal bit phase adjusting circuit - Google Patents

Abstract

PURPOSE:To automatically match the phases of signal bits in a signal bit phase adjusting circuit to be used in the case of multiplexing data in plural sequences and transmitting the multiplexed data. CONSTITUTION:The signal bit phase adjusting circuit is constituted of a 1st and 2nd n-stage shift registers 2, 3 for forming a 1st and 2nd n-phase frame bits from inputted a 1st and 2nd frame bits, a phase difference detecting means 4 for detecting a phase difference between the 1st and 2nd n-phase frame bits sent from the shift registers 2, 3, and in the case of detecting that the phase difference between the 1st and 2nd frame bits is zero, sending a detection output with a prescribed level and a selecting means 5 for selecting the 1st and 2nd frame bits generating a phase difference '0' out of the 1st and 2nd n-phase frame bits based upon the detection output with the prescribed level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal bit phase adjusting circuit used when, for example, a plurality of series of data are multiplexed for data transmission.

For example, when receiving a plurality of series of data,
Since the propagation delay differs depending on the distance of each transmission line, the phases of these data are not aligned. Therefore, when multiplexing these data, the phase of the frame bit inserted in the received data and the phase of the data must be matched.

At this time, it is necessary to automatically match the phases of the signal bits.

[0004]

2. Description of the Related Art FIG. 8 is a block diagram of a conventional example. In the figure, frame pulse # 1 (hereinafter abbreviated as FP # 1) and data # 1, and FP # 2 and data # 2 are synchronized, respectively.
FP # 1 and FP # 2 are out of phase.

Therefore, using a measuring instrument such as a synchroscope, the phase difference between FP # 1 and FP # 2 is confirmed, and the FP extracted from the shift registers 11 and 13 so that the phase difference is minimized.
Switch the positions of # 1 and FP # 2. In addition, in response to this, the shift register 12 for taking out the data # 1 and the data # 2,
Switch position 14 too.

As a result, FP # 1 and FP # 2 and data
The phase difference between # 1 and data # 2 is the smallest.

[0007]

DISCLOSURE OF THE INVENTION As described above,
Since the bit adjustment was performed by manually changing the extraction point of the shift register by the amount corresponding to the phase difference between FP # 1 and FP # 2, there was a problem that adjustment took time.

It is an object of the present invention to automatically match the phases of signal bits. This facilitates the adjustment.

[0009]

FIG. 1 is a block diagram showing the principle of the first and second aspects of the present invention. In the figure, 2 and 3 are first and second n-stage shift registers for generating n-phase first and second frame bits from the input first and second frame bits.

Reference numeral 4 detects the phase difference between the n-phase first and second frame bits sent from the first and second n-stage shift registers, but detects the phase difference between the first and second frame bits. It is a phase difference detecting means for sending a detection output of a predetermined level when it is detected that the phase difference is zero.

A reference numeral 5 uses the detection output of the predetermined level to select a phase difference of 0 from the first and second frame bits of the n phase.
Is a selecting means for selecting and outputting the first and second frame bits that have become.

Numeral 6 is a protection function which sends out the detection output of the above predetermined level when the phase difference 0 between the first and second frame bits is detected a predetermined number of times consecutively, and is added to the phase difference detecting means. It

[0013]

According to the first aspect of the present invention, the input first frame bit is applied to the first n-stage shift register, and the first frame bit is extracted from each stage of the first n-stage shift register. Generate the first frame bit of the n phase.

Also for the second frame bit, the n-phase second frame bit is generated in the same manner as described above. Then, the phase difference detecting means detects all the phase differences (denoted by ±) between the first and second frame bits of the n phase, but the positions of the first and second frame bits are detected. When it is detected that the phase difference is 0, a detection output of a predetermined level (for example, H level) is sent to the selecting means.

The selecting means selects the first and second frame bits having a phase difference of 0 from the n-phase first and second frame bits by using the applied H level detection output. And output.

By utilizing the above-mentioned H level detection output, the data synchronized with the extracted first and second frame bits is also selected and output. According to a second aspect of the present invention, when the phase difference between the first and second frame bits is continuously detected a predetermined number of times by the phase difference detecting means, the detection output of the predetermined level is sent to the selecting means. Added a protection function.

Thus, the phases of the signal bits can be automatically matched.

[0018]

FIG. 2 is a block diagram of the first and second embodiments of the present invention, FIG. 3 is an example of a block diagram of the shift register portion in FIG. 2, and FIG. 4 is a phase difference detecting portion in FIG. An example of the configuration, FIG.
2 is an example of a configuration diagram of a protection function portion in FIG. 2, FIG. 6 is an example of a configuration diagram of a selector in FIG. 2, and FIG. 7 is an operation explanatory diagram of FIG.

Here, the symbols on the left side of FIG. 7 indicate the waveforms of the portions having the same symbols in the corresponding drawings. Also, the same reference numerals denote the same objects throughout the drawings. Below, the frame bit (F
The operation of FIG. 2 will be described with reference to FIGS. 3 to 7, assuming that the phase of P) # 2 is delayed by one bit with respect to the frame bit (FP) # 1.

First, in the shift registers 21, 22 and the shift registers 31, 32 of FIG.
1) and data # 1 synchronized with FP # 1 (hereinafter abbreviated as data # 1) and FP # 2 delayed by 1 bit from FP # 1 and data # 2 synchronized with FP # 2. Input (see Figure 3-- in Figure 7).

It is assumed that FP # 1 and data # 1 are synchronized with each other, and FP # 2 and data # 2 are synchronized with each other. As shown in FIG. 3, the shift registers 21, 12, 31, and 32 described above are connected in cascade with two or three flip-flops (hereinafter, FF).
And abbreviated).

For example, input FP # 1 (FP # 1-IN in the figure
Is added to the three-stage shift registers 211 to 213, so FP # 1 delayed by 1 bit from FF 211 (indicated by φ ₁ ) and 2 bits delayed from FF 212 (this is changed to φ
FP # 1 which is shown by ₂ ) and FP # 1 which is delayed by 3 bits (shown by φ ₃ ) is taken out from FF 213.

Similarly, from the input data # 1, FF 221,
Data # 1 of φ ₁ and φ ₂ is obtained by FF 222. Also, from the input FP # 2 and data # 2, the FP of φ ₁ and φ ₂
# 2, data # 2 are obtained.

Now, the shift registers 211 to 213 and 311, 3
FP # 1 and phi ₁ of phi ₁ to [phi] ₃ sent from 12, phi ₂ of the FP # 2
Is applied to NAND gates 411-413 in FIG. Here, NAND gate 412 for detecting a phase difference between the NAND gate 411, the phi ₁ both FP # 1 and FP # 2 for detecting a phase difference between the FP # 2 of phi ₁ of FP # 1 and phi _2, phi ₂ FP # 1 and φ ₁ FP
It is composed of the NAND gate 413 that detects the phase difference of # 2. As mentioned above, FP # 2 is delayed by 1 bit from FP # 1. 1 for 2
If the phases are compared with a bit delay, the phases of both FPs should match.

[0025] In other words, FP # of φ ₂ to the NAND gate 413 of FIG. 4
Since 1 and FP # 2 of φ ₁ are applied, H from here is applied to RS-FF 433 via OR gate 423 and latched. Therefore, RS-FF 433 sends H level (Phase 3) to the protection function part in Fig. 5.

The outputs of the other NAND gates 411 and 412 are in the L level state because their phases do not match, and the phases 1 and 2 are also in the L level state. Also, FP # 1 of φ ₃ inputs to NOR gate 442 via inverter 441,
Only at this time, clock CK is NOR gate 442, inverter 44
Since the RS-FF 433 is reset via 3, the H level of the face 3 described above returns to the L level and the state for waiting for the next FP is entered (see FIG. 4 to FIG. 7).

Here, the protection function portion shown in FIG. 5 has three protection stages, but since the configuration of the protection function portion for each phase is the same, only the phase 1 is shown. As shown in the figure, for example, H level phase 1 is 3
When the inputs are input consecutively, all the outputs of FF611 to 613 become H, and the AND gate 614 applies H to RS-FF616. Therefore, H is sent from RS-FF 616 to the selector of FIG. 6 as a control signal (CONT ₁ ), but this signal is disconnected three times in succession when phase 1 becomes L.

The above operation is the same in the phases 2 and 3. Now, when the H-level phase 3 is input to this protection function part three times in succession, a control signal (CONT ₃ ) is sent from this part to the selector of FIG. 6 (see FIG. 5 of FIG. 7). AND gates 513, 523, 533, 5 in Figure 6
43 turns on.

As a result, the FP # 1 of φ ₂ and the data # 1 are O
Output via R gates 514, 524 and FF 515, 525, and FP # 2 and data # 2 of φ ₁ are also OR gates 534, 54
4, output via FF535, 545 (Fig. 6-
See).

Since there is no protection function portion in the first aspect of the present invention, for example, phase 3 transmitted from the phase difference detection portion of FIG. 4 is transmitted to the selector of FIG. 6 as a control signal (CONT ₃ ). , Same as above FP # 1, data # 1, FP # 2,
Data # 2 is selected. However, since there is no protection, if the phase difference detection part of FIG.
Immediately, it switches to the corresponding control signal (CONT ₂ ).

That is, when matching the bit phases of two series of signals having different signal bit phases, the bit phases can be automatically adjusted without manually checking the phase difference.

[0032]

As described in detail above, according to the present invention, there is an effect that the phases of signal bits can be automatically matched.

[Brief description of drawings]

FIG. 1 is a principle block diagram of first and second aspects of the present invention.

FIG. 2 is a configuration diagram of the first and second embodiments of the present invention.

FIG. 3 is an example of a configuration diagram of a shift register portion in FIG.

FIG. 4 is an example of a configuration of a phase difference detection portion in FIG.

5 is an example of a configuration diagram of a protection function portion in FIG.

FIG. 6 is an example of a configuration diagram of a selector in FIG.

FIG. 7 is an operation explanatory diagram of FIG. 2;

FIG. 8 is a configuration diagram of a conventional example.

[Explanation of symbols]

2 first n-stage shift register 3 second n-stage shift register 4 phase difference detection means 5 select means 6 protection function

Claims (2)

[Claims] 1. A first and second n-stage shift register (2, 2) for generating n-phase (n is a positive integer) first and second frame bits from input first and second frame bits. 3)
And n transmitted from the first and second n-stage shift registers,
The phase difference between the first and second frame bits of the phase is detected, but when the phase difference between the first and second frame bits is detected to be 0, a detection output of a predetermined level is transmitted. Using the phase difference detection means (4) and the detection output of the predetermined level, the first and second n-phase
And a selecting means (5) for selecting and outputting the first and second frame bits having a phase difference of 0 from among the frame bits. 2. A protection function for transmitting a detection output of the predetermined level when the phase difference detecting means detects a phase difference 0 between the first and second frame bits for a predetermined number of times in succession. 6. The signal bit phase adjusting circuit according to claim 1, wherein 6) is added.