JPH05121703A - Gate array - Google Patents

Abstract

PURPOSE:To cut down the period required for the processes following a wiring process without increasing the area of a chip, or in other words, the title gate array can be developed in a short period. CONSTITUTION:A plurality of basic cell columns consisting of a plurality of paralleled basic cells 200 are formed, two wirings with which each basic cell 200 is connected with each other, consisting of the upper layer wiring 300 and the lower wiring 100m are formed, and the lower wiring 100 is formed inside the basic cell 200 in advance.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a gate array, and more particularly to a gate array which can be developed in a short period of time.

[0002]

2. Description of the Related Art In a conventional gate array, when the operation of a circuit to be constructed can be confirmed, each basic cell is constructed in order to construct the circuit on a wafer in which a plurality of basic cells are formed in advance. A wiring step is performed to wire each other. At this time, in consideration of the wiring efficiency, the connection wiring is performed by a multilayer wiring having two or more layers.

For example, 2 consisting of lower layer wiring and upper layer wiring
If the wiring is formed by the layer wiring, the lower layer wiring is formed in the channel region, the interlayer insulating film is formed on the lower layer wiring,
Further, an upper layer wiring is formed on this interlayer insulating film. Then, if necessary, a VIA hole is opened in the interlayer insulating film,
The lower layer wiring and the upper layer wiring are connected through this VIA hole. This wiring process requires at least four masks for forming a lower layer wiring, forming a contact for connecting the lower layer wiring to the diffusion layer or the polysilicon layer, forming an upper layer wiring, and forming a VIA hole. ~ 4
It takes a week period.

In order to shorten the period required for the processes after the wiring process, there has been proposed a gate array in which a plurality of lower layer wirings are previously formed in the channel region.

[0005]

However, when the lower layer wiring is formed in the channel region in advance, the wiring to be formed inside the basic cell, for example, the wiring connecting the connection request terminals in the same basic cell, Since it is formed by using the lower layer wiring, a channel region larger than the conventional one is required, and as a result, the chip area increases.

The present invention was devised in view of the above circumstances, and it is possible to shorten the period required for the processes after the wiring process without increasing the chip area.
That is, the object is to provide a gate array that can be developed in a short period of time.

[0007]

A gate array according to the present invention is a gate array in which a plurality of basic cells are regularly formed, and a wiring for connecting the basic cells to each other is a multilayer wiring having two or more layers. The lowermost wiring of the multilayer wiring is formed in advance inside the basic cell.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic plan view of a basic cell used in a gate array according to an embodiment of the present invention, and FIG. 2 is a pattern showing a part of a JKRS type flip-flop constructed using this gate array. It is a figure.

In the following description, the gate array will be described as consisting of two wirings, an upper wiring 300 and a lower wiring 100.

In the gate array according to the present embodiment, a plurality of basic cell rows are formed by arranging a plurality of basic cells 200 in parallel, and the wiring connecting each basic cell 200 to each other is two wirings, that is, an upper layer. The wiring 300 and the lower layer wiring 100 are formed, and the lower layer wiring 100 is previously formed inside the basic cell 200.

In the basic cell 200 shown in FIG. 1, six lower layer wirings 100 parallel to each other are formed in advance.

Basic cell configured in this way
The 200 cells are arranged in the horizontal direction to form a basic cell array. Feed-through wirings 500 used for vertical connection are formed between the basic cells 200 forming the basic cell row.

When forming a circuit in such a gate array, since the lower layer wiring 100 is previously formed inside the basic cell 200, it is provided between the upper layer wiring 300 and the upper layer wiring 300 and the lower layer wiring 100. It is sufficient to form the inter-layer insulating film to be formed, and the VIA hole 400 opened in the inter-layer insulating film for connecting the upper layer wiring 300 and the lower layer wiring 100. Therefore, the mask required in the wiring process is the upper layer wiring 30.
Since only two, one used for forming 0 and the one used for forming the VIA hole 400, are sufficient, it is possible to simplify the conventional wiring process which requires at least four masks. Therefore, shortening of the development period can be achieved.

Wiring of this gate array will be described by using a part of the JKRS type flip-flop shown in FIG. The wiring formed on the upper side is the V _CC wiring, and the wiring formed on the lower side is the GND wiring. In the basic cell 200 on the left end of the drawing, the lower layer wiring 100, which is the second from the bottom of the drawing, is connected to the upper layer wiring 300 via the VIA holes 400 (shown by white circles in the drawing). Explaining only this part, since the lower layer wiring 100 is formed in the basic cell 200 in advance, it is not necessary to form it by using a mask in the wiring process. The same applies to the second, third, and fourth lower layer wirings 100 from the top of the second basic cell 200 from the left. VIA
The lower layer wiring 100 in which the hole 400 is not formed, for example, the first lower layer wiring 100 from the top of the left basic cell 200
Does not have a function as a wiring.

Although the gate array in the above-described embodiment is composed of two wirings, the present invention is not limited to this, and may be composed of three or more wirings as required. It may be one. For example, in the case of including three wirings of an upper layer wiring, a middle layer wiring, and a lower layer wiring, a VIA hole is formed in a mask for forming the middle layer wiring and a first interlayer insulating film formed between the lower layer wiring and the middle layer wiring. A total of four masks are required: a mask for forming an upper layer wiring on the middle layer wiring, a mask for forming a VIA hole in the second interlayer insulating film formed between the middle layer wiring and the upper layer wiring. However, it is possible to reduce the number of masks as compared with the conventional one which requires a total of five masks. Therefore, even in this case, it is possible to reduce the number of masks required for the circuit configuration, which in turn shortens the development period.

[0016]

The gate array according to the present invention is a gate array in which a plurality of basic cells are regularly formed, and the interconnections for connecting the basic cells to each other are formed of multilayer interconnections of two or more layers. Since the wiring of the lowermost layer of the multilayer wiring is formed inside the basic cell in advance, in the wiring process after confirming the operation of the circuit to be configured, the mask for forming the wiring of the lowermost layer and the wiring of the lowermost layer are formed. A mask is unnecessary because a contact for connecting to a diffusion layer or the like is formed. Therefore, the period of the wiring process can be shortened, and the semiconductor device can be manufactured in a shorter period than in the past.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a basic cell used in a gate array according to an embodiment of the present invention.

FIG. 2 is a pattern diagram showing a part of a JKRS type flip-flop configured by using this gate array.

[Explanation of symbols]

 100 Lower layer wiring (lowermost layer wiring) 200 Basic cell 300 Upper layer wiring

Claims (1)

[Claims] 1. In a gate array in which a plurality of basic cells are regularly formed and wirings connecting the basic cells to each other are formed of multilayer wirings of two or more layers, the wiring of the bottom layer of the multilayer wirings is previously formed. A gate array formed inside a basic cell.