JPH05235298A - Dynamic random access memory - Google Patents

Abstract

PURPOSE:To eliminate a deviation in layout density by a plurality of active region lines arranged and deviated by 1/3 pitch in X-axis direction, by forming each bit line contact co-owned by two transistors in two regions perpendicular to a plurality of word lines and by connecting them through capacitors on diagonal lines. CONSTITUTION:Two rows of active regions arranged in X-axis direction at a predetermined intervals on a semiconductor substrate is deviated by 1/3 interval respectively and a plurality of lines are also arranged in Y-axis direction. Also, two transistors are formed at two portions perpendicular to the word line 1. In addition, a bit line contact 6 commonly possessed by two transistors is formed. Also, a transistor formed on one side of active region 2 is connected to a transistor arranged the closest to the Y-axis direction above the transistors via capacitor 3 erected on a diagonal line from X-axis to Y-axis.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory (DRAM), and more particularly to a dynamic random access memory having a displacement arrangement.

[0002]

2. Description of the Related Art Conventionally, in a DRAM composed of two transistors and one capacitor, as shown in FIG. 5, active regions 21 are X-shaped at a predetermined pitch on a semiconductor substrate.
The active regions are arranged in the axial direction. A plurality of active region rows are arranged every two rows with a 1/2 pitch shift in the X-axis direction. Further, a plurality of word lines are formed so as to be substantially orthogonal to the active regions 21.

In the active region 21, two transistors are formed in two portions which are orthogonal to the word line, and a bit line contact 22 shared by these two transistors is further formed. In addition, each active area 2
The transistor formed in one of the two includes a transistor formed in the active region 21 arranged adjacent to the active region in the Y-axis direction and a capacitor 23 formed above these two transistors. It is configured to be connected via.

[0004]

According to the above DRAM, the arrangement of the word line 20 and the bit line contact 22 formed between the word line 20 and the capacitor 23 arranged above the two transistors. Unbalanced density will be formed. That is, the columns in which the bit line contacts 22 are formed and the columns in which the capacitors 23 are arranged are in a state of being alternately arranged in the X-axis direction. While there is a space between the bit line contacts 22 and the bit line contact 22, there is no space between the capacitors 23 and 23 in the column in which the capacitors 23 are formed. There were challenges.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a DRAM capable of eliminating a bias in the arrangement density of bit line contacts and capacitors.

[0006]

In order to solve the above-mentioned problems, according to the present invention, an active region row composed of a plurality of active regions arranged in parallel at a predetermined pitch in the X-axis direction on a semiconductor substrate is provided. A plurality of columns are arranged in the Y-axis direction with a shift of 1/3 pitch in the X-axis direction, and a plurality of word lines are formed so as to be substantially orthogonal to the active region. Two transistors are formed in two regions orthogonal to the word line, and bit line contacts shared by these transistors are formed. One of the transistors formed in the active region is closest to the Y-axis direction. And the transistors arranged in
There is provided a DRAM configured by connecting these two transistors via a capacitor that is provided above the two transistors and on a diagonal line with respect to the X-Y axis direction.

The active region row in the present invention is 1 in the X-axis direction.
A plurality of rows are arranged in the Y-axis direction with a shift of / 3 pitch, and the layout is repeated in three cycles in the Y-axis direction to achieve high integration. In the present invention, the transistor formed on the active region is 100% as a gate insulating film.
Is formed through a SiO ₂ film of about 150 Å,
Polysilicon is preferable for the gate electrode to be the word line, and its film thickness is preferably about 1500 to 2500 Å.

Further, the lower electrode and the upper electrode of the capacitor which is provided above the two transistors and diagonally with respect to the X-Y axis direction are preferably formed of polysilicon, tungsten or the like. Thickness is 15
00-4000Å and 500-1500Å are preferred. Further, as the capacitor insulating film, a ferroelectric film, a paraelectric film or the like can be used, but preferably Si ₃ N ₄ /
SiO ₂ film with a thickness of 40-60 Å in terms of SiO ₂
A degree equivalent is preferable.

Further, the local wiring connecting hole for connecting the transistor and the capacitor and the through hole for forming the bit line contact may be formed at the same time. The local wiring connecting hole is formed and the local wiring is connected. After that, bit lines may be wired by forming through holes for forming bit line contacts. The local wiring can be formed of polysilicon, tungsten or the like, and the film thickness thereof is preferably 500 to 1500Å. The bit line is formed with a bit line contact pad in advance, and polysilicon, TiW, TiN, tungsten, etc. It can be formed by laminating about 5000 Å.

[0010]

According to the above structure, the bit line contact formed between the word lines,
X with a capacitor placed above the two transistors
The bias of the arrangement density in the −Y axis direction is eliminated.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A DRAM according to the present invention will be described with reference to the drawings. As shown in FIG. 1, in a DRAM including two transistors and one capacitor, active regions 2 are arranged on a semiconductor substrate at a predetermined pitch in the X-axis direction to form two rows of active regions. There is. The two rows of the active regions are arranged in the Y-axis direction so as to be shifted by 1/3 pitch in the X-axis direction. Further, a plurality of word lines 1 are formed so as to be substantially orthogonal to the active regions 2.

In the active region 2, two transistors are formed in two portions orthogonal to the word line 1, and a bit line contact 6 shared by these two transistors is further formed. Further, a transistor formed in one of the active regions 2 is a transistor arranged closest to the Y-axis direction and a transistor above these two transistors and on a diagonal line with respect to the XY-axis direction. It is configured to be connected via the erected capacitor 3.

That is, the active region 2 is repeated in the Y-axis direction at three cycles. Here, each transistor is configured to be controllable by a word line 1 which constitutes a gate electrode, and this gate electrode is covered with a SiO ₂ protective film. The capacitor 3 includes, for example, a lower electrode 4 made of a polysilicon film and an S equivalent to 60Å in terms of SiO _2.
An i ₃ N ₄ / SiO ₂ film (not shown) and an upper electrode 5 made of a polysilicon film are stacked and connected to the transistor via the impurity diffusion regions formed in the active region 2, respectively. Has been done.

The DRAM configured as described above is shown in FIG.
It can be manufactured as shown in FIG. FIG. 2 shows A of FIG.
2A is a cross-sectional view taken along line A. First, as shown in FIG. 2A, an active region is secured by forming an element isolation region made of a field oxide film 11 on a silicon substrate 12, and then silicon is formed. A SiO ₂ film 15 of about 100 Å is formed on the entire surface of the substrate 12 as a gate insulating film. Then Si
About 2000 Å of polysilicon is laminated on the O ₂ film 15 and etched by a known method to form a gate electrode to be the word line 1, and then SiO ₂ is formed by, for example, the CVD method.
Of the protective film 1 on the gate electrode by depositing and etching back
9 is formed. Then, the gate electrode and the protective film 19
By using as a mask, ion implantation is performed to form an n-type impurity diffusion region 16. Then, in order to form a contact 9 between the impurity diffusion region 16 and the capacitor lower electrode 4 which will be formed in a later step, the SiO ₂ film 15 on a part of the impurity diffusion region 16 is removed.

Next, as shown in FIG. 2B, about 2500 Å of polysilicon is laminated on the gate electrode and the protective film 19 and patterned into a desired shape to form the capacitor lower electrode 4. Then, as shown in FIG. 2C, a Si ₃ N ₄ film of about 100 Å, for example, is deposited as a capacitor insulating film on the capacitor lower electrode 4 by the CVD method and then thermally oxidized to be converted into SiO _2. At 60Å
A corresponding Si ₃ N ₄ / SiO ₂ film 13 is formed. Then, about 1500 Å polysilicon is laminated and patterned to form the capacitor upper electrode 5.

Then, as shown in FIG. 2D, an interlayer insulating film 17 is formed over the entire surface of the capacitor upper electrode 5, for example, HTO (high temperature SiO using the CVD method).
₂ ) is laminated about 1000Å. Then, a local wiring connection hole (7 in FIG. 1) for connecting the impurity diffusion region 16 and the capacitor upper electrode 5 is opened in the interlayer insulating film 17, and, for example, polysilicon is deposited to about 1500 Å and patterned. To form the local wiring 8. As a result, the impurity diffusion region 16 and the capacitor upper electrode 5 are connected. Further, over the entire surface of the local wiring 8, as the interlayer insulating film 14, for example, NSG of 150 is formed.
After depositing about 0Å and about 4000Å of BPSG, the bit line contact 6 is opened in the interlayer insulating film 14. Then, for example, W of about 4000 Å is deposited and etched back, and then a wiring material such as Al or TiW is laminated to form a bit line (not shown).

Therefore, the two transistors Tr1 and Tr
As shown in FIG. 3, the unit cell that stores 2-bit information by two and one capacitor C is a transistor Tr.
1 is connected to the lower electrode 4 of the capacitor C,
The upper electrode 5 opposed to is connected to the transistor Tr2 through a local wiring. When applied in this way actually memory fabricated with DRAM, the 4/3 of the sense amplifier is required to be applied to the case of the conventional arrangement, as shown in FIG. 4, a ternary converter from 2 ⁿ This is done, and the system is switched in cycle 3.

[0018]

According to the DRAM of the present invention, the arrangement density in the XY direction of the bit line contacts formed between word lines and the capacitors arranged above the two transistors. The bias of can be eliminated.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing a cell arrangement of a DRAM according to the present invention.

FIG. 2 is a schematic cross-sectional view showing an example of a method of manufacturing a DRAM according to the present invention.

FIG. 3 is a peripheral circuit diagram of a DRAM according to the present invention.

FIG. 4 is an equivalent circuit diagram showing a unit cell of a DRAM according to the present invention.

FIG. 5 is a schematic plan view showing a cell arrangement of a conventional DRAM.

[Explanation of reference numerals] 1 word line (gate electrode) 2 active region 3 capacitor 6 bit line contact

Claims (1)

[Claims] 1. An active region row comprising a plurality of active regions arranged in parallel on the semiconductor substrate at a predetermined pitch in the X-axis direction is arranged in a plurality of rows in the Y-axis direction with a shift of 1/3 pitch in the X-axis direction. And a plurality of word lines are formed so as to be substantially orthogonal to the active region. In the active region, two transistors are formed in two regions orthogonal to the word line, and these transistors are further formed. A bit line contact shared by the two transistors is formed, and one of the transistors formed in the active region is arranged closest to the Y-axis direction, and X- above the two transistors. A dynamic random access memory, which is configured to be connected via a capacitor installed diagonally with respect to the Y-axis direction.