JPH05121415A - Production of semiconductor substrate - Google Patents

Production of semiconductor substrate

Info

Publication number
JPH05121415A
JPH05121415A JP31176491A JP31176491A JPH05121415A JP H05121415 A JPH05121415 A JP H05121415A JP 31176491 A JP31176491 A JP 31176491A JP 31176491 A JP31176491 A JP 31176491A JP H05121415 A JPH05121415 A JP H05121415A
Authority
JP
Japan
Prior art keywords
wafer
film
reaction
polycrystalline
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP31176491A
Other languages
Japanese (ja)
Other versions
JP2723725B2 (en
Inventor
Shinichi Tomizawa
進一 富沢
Naoyuki Takamatsu
直之 高松
Katsunori Koarai
克典 小荒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Priority to JP3311764A priority Critical patent/JP2723725B2/en
Publication of JPH05121415A publication Critical patent/JPH05121415A/en
Application granted granted Critical
Publication of JP2723725B2 publication Critical patent/JP2723725B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PURPOSE:To reduce the warpage even if a wafer is subjected to the specular grinding and suppress the reduction of device characteristics and yield when forming a polycrystalline silicon film on a semiconductor wafer. CONSTITUTION:When a wafer composed of Si (silicon) single crystal is processed to produce a semiconductor substrate, the surface to form semiconductor elements is a mirror surface, and its rear side is provided with a polycrystalline Si film. The Si film is formed by using a material gas whose composition is mainly 10-100wt.% SiH4 (monosilane) and an invent gas for remaining part, whereas its reaction temperature is 600-700 deg.C and the pressure is within 0.01-0.3 Torr during reaction.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置(以下デバ
イスと云う)製造用のSi単結晶からなるウェーハ(以
下単にウェーハと云う)に関し、半導体素子形成を行う
面とは反対側の面に多結晶Si膜を形成せしめることに
より、エクストリンシックゲッタリング効果を付与した
半導体基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer (hereinafter referred to simply as "wafer") made of Si single crystal for manufacturing a semiconductor device (hereinafter referred to as "device"), which is provided on a surface opposite to a surface on which a semiconductor element is formed. The present invention relates to a method for manufacturing a semiconductor substrate having an extrinsic gettering effect by forming a polycrystalline Si film.

【0002】[0002]

【従来の技術】デバイスの製造工程において、半導体基
板は種々の熱処理を受ける。この熱処理過程において、
同基板中に存在している炭素や金属不純物、あるいはデ
バイス製造工程中に同基板表面を汚染した金属不純物
は、その基板以において析出して様々の結晶欠陥を発生
させる。これらの欠陥は半導体基板の表面及びその近傍
にも発生し、リーク電流を増大させたり基板のライフタ
イムを低下させ、これより製造されるデバイスの特性や
歩留に対し悪影響を及ぼす。
2. Description of the Related Art A semiconductor substrate is subjected to various heat treatments in a device manufacturing process. In this heat treatment process,
Carbon and metal impurities existing in the substrate, or metal impurities that contaminate the surface of the substrate during the device manufacturing process, are deposited on the substrate and cause various crystal defects. These defects also occur on the surface of the semiconductor substrate and in the vicinity thereof, increasing the leak current and decreasing the lifetime of the substrate, which adversely affects the characteristics and yield of the device manufactured.

【0003】一方、ウェーハの裏面または内部に作った
微小結晶欠陥や歪みは、デバイス特性に有害な影響を与
える不純物を捕獲、固着したり、または欠陥発生に関与
している点欠陥などを除去する作用がある。この作用は
ゲッタリングと呼ばれ、前者はエクストリンシックゲッ
タリング(EG)、後者はイントリンシックゲッタリン
グ(IG)と呼ばれている。
On the other hand, minute crystal defects and strains formed on the back surface or inside of the wafer trap impurities that have a harmful effect on device characteristics, fix them, or remove point defects that are involved in the generation of defects. It has an effect. This action is called gettering, the former is called extrinsic gettering (EG) and the latter is called intrinsic gettering (IG).

【0004】このEGの一つとして、ウェーハの裏面に
多結晶Si膜を形成し、この多結晶Si膜の粒界に発生
する歪場や格子不整合による歪場をゲッタリング源とし
て利用する手法が知られている(特開昭52−1207
77号公報、特開昭55−113318号公報、特開昭
57−136331号公報等)。
As one of the EGs, a method of forming a polycrystalline Si film on the back surface of a wafer and using a strain field generated at a grain boundary of the polycrystalline Si film or a strain field due to lattice mismatch as a gettering source. Is known (Japanese Patent Application Laid-Open No. 52-1207).
77, JP-A-55-113318, JP-A-57-133331, etc.).

【0005】ここで使用するウェーハは、通常シリコン
単結晶棒よりスライスされた円板を、研磨後にエッチン
グした段階のものである。また多結晶Si膜をウェーハ
表面に形成させるには、SiH4 のようなSi含有ガス
の熱分解反応、或いはSiHx Cl4-x (クロルシラ
ン)の水素還元反応を利用したCVD法がある。しか
し、どの方法であっても、ウェーハ表面上にSi多結晶
膜を形成させる際には、片側表面のみ膜付する際に起き
るウェーハの変形を防止するため、その全表面に対して
できるだけ均一な質と厚さを有する膜を形成させ、その
後で片側表面のSi多結晶を除去して鏡面研磨すること
により半導体基板は製造される。しかし、このようにし
て得られる半導体基板は、やはり鏡面側が凹となる反り
を発生し、それがある値以上になるとデバイス製造上の
障害となる。また初期において反りが無い基板でも、以
後のデバイス製造工程中の熱処理等により新たな反りを
発生し、デバイスの品質や製造歩留を低下させることも
ある。
The wafer used here is usually one obtained by etching a disk sliced from a silicon single crystal ingot after polishing. Further, to form a polycrystalline Si film on the wafer surface, there is a CVD method utilizing a thermal decomposition reaction of a Si-containing gas such as SiH 4 or a hydrogen reduction reaction of SiH x Cl 4-x (chlorosilane). However, in any method, when forming a Si polycrystalline film on the wafer surface, in order to prevent the deformation of the wafer that occurs when only one surface is applied, the entire surface should be as uniform as possible. A semiconductor substrate is manufactured by forming a film having quality and thickness, and then removing the Si polycrystal on one surface and performing mirror polishing. However, the semiconductor substrate obtained in this manner also causes a warp in which the mirror surface side is concave, and if it exceeds a certain value, it becomes an obstacle in device manufacturing. Further, even if the substrate does not warp in the initial stage, a new warp may occur due to heat treatment or the like in the subsequent device manufacturing process, which may deteriorate the quality of the device and the manufacturing yield.

【0006】[0006]

【発明が解決しようとする課題】本発明は、ウェーハ上
に多結晶シリコン膜を形成するに際し、当該ウェーハが
鏡面研磨処理を受けても反りの発生が少なく、デバイス
特性や歩留の低下が生じないようにした半導体基板の製
造方法を提供することを目的とする。
According to the present invention, when a polycrystalline silicon film is formed on a wafer, warpage is less likely to occur even if the wafer is subjected to mirror polishing treatment, resulting in a decrease in device characteristics and yield. It is an object of the present invention to provide a method for manufacturing a semiconductor substrate that does not include the above.

【0007】[0007]

【課題を解決するための手段】上記課題を解決するため
に、本発明の半導体基板の製造方法においては、Si単
結晶からなるウェーハに関して、半導体素子形成を行う
面は鏡面であり、その裏面側には多結晶Si膜を形成せ
しめた構造を有する半導体基板の製造において、前記多
結晶Si膜の形成は、原料ガスの組成をSiH4 10〜
100重量%で残部は不活性ガスとし、その反応温度を
600〜700℃、反応時の圧力を0.01〜0.3T
orrの範囲内としたものである。
In order to solve the above-mentioned problems, in the method for manufacturing a semiconductor substrate of the present invention, the surface on which a semiconductor element is formed is a mirror surface and the back surface side of the wafer made of Si single crystal. In manufacturing a semiconductor substrate having a structure in which a polycrystalline Si film is formed, the formation of the polycrystalline Si film is performed by changing the composition of the source gas to SiH 4 10
The balance is 100% by weight and the balance is an inert gas, the reaction temperature is 600 to 700 ° C., and the reaction pressure is 0.01 to 0.3 T.
It is within the range of orr.

【0008】上記モノシランガス組成が10重量%に満
たないと、本発明の低い圧力条件による多結晶Si膜形
成の反応速度は著しく低下し、しかも多数の並列ウェー
ハを同時処理する場合の膜厚制御は困難になる。また1
00重量%の場合、本発明の反り防止の効果はいかんな
く発揮されるが、やはり多数のウェーハを同時処理する
場合の膜厚制御は幾分困難となるので、希釈用の不活性
ガスを併用し、ガス圧力やガス流量等を制御して操業す
る方が好ましい。
If the composition of the monosilane gas is less than 10% by weight, the reaction rate of forming a polycrystalline Si film under the low pressure condition of the present invention is remarkably reduced, and the film thickness can be controlled when a large number of parallel wafers are simultaneously processed. It will be difficult. Again 1
When the amount is 00% by weight, the effect of preventing warpage of the present invention is exhibited at all. However, since the film thickness control becomes somewhat difficult when a large number of wafers are simultaneously processed, an inert gas for dilution is also used. However, it is preferable to operate by controlling the gas pressure and the gas flow rate.

【0009】反応温度が600℃以下の場合、モノシラ
ンの熱分解速度は低下し、結果として膜形成の生産効率
は悪くなり、反りは増大する傾向がみられる。また70
0℃以上の温度では熱分解速度は上昇し、その結果、多
数の並列ウェーハを同時処理する場合の膜厚を均一化す
るための制御は困難になる。
When the reaction temperature is 600 ° C. or lower, the thermal decomposition rate of monosilane decreases, and as a result, the production efficiency of film formation deteriorates and the warpage tends to increase. Again 70
At a temperature of 0 ° C. or higher, the thermal decomposition rate increases, and as a result, it becomes difficult to control the film thickness to be uniform when a large number of parallel wafers are simultaneously processed.

【0010】本発明方法における最大の特徴は、反応圧
力を従来に比較して極めて低い0.01〜0.3Tor
rにしたことである。SiH4 の減圧熱分解CVD法に
おける圧力条件は、通常1.0Torr以下より0.5
Torr位の範囲であり、その主なる理由は所定の生産
性を維持するためであると考えられる。しかし、この条
件においては、反りの大きな半導体基板をしばしば発生
する。半導体基板においては、基板の平坦度と同時に、
反りのような変形のないことが要件であり、とりわけ素
子集積度の高密度化はこの要求をますます厳しくし、こ
の要件を満たさない半導体基板は規格外となり、結果的
には半導体基板の製造歩留を低下させる原因となる。
The most significant feature of the method of the present invention is that the reaction pressure is extremely low as compared with the conventional method, that is, 0.01 to 0.3 Tor.
That is r. The pressure condition in the low pressure pyrolysis CVD method of SiH 4 is usually 1.0 Torr or less to 0.5
It is in the range of Torr, and it is considered that the main reason for this is to maintain a predetermined productivity. However, under these conditions, a semiconductor substrate with a large warp is often generated. In a semiconductor substrate, at the same time as the flatness of the substrate,
The requirement is that there be no deformation such as warpage, and especially the higher density of device integration makes this requirement even more stringent, and semiconductor substrates that do not meet this requirement are out of specification, and as a result, semiconductor substrate manufacturing It causes a decrease in yield.

【0011】又、本発明は複数枚のウェーハに関し、そ
の全表面が原料ガスと接触するように所定の間隔で一様
に配列し、原料ガスはそのウェーハ並びの一方側より導
入し、その他方側より排出するようにした多結晶Si膜
を形成させる方法において、ウェーハ並びの原料ガスの
流れ方向に対して、段階的に反応温度を上昇させること
により、全数のウェーハに関し多結晶Si膜の厚さの均
一化を図ることができる。この場合の中心温度及び温度
勾配は装置全体の構造寸法、処理されるウェーハのサイ
ズと枚数、原料ガスの組成流量等の諸条件により決定さ
れるので特定できないが、反応の中心設定温度に対して
は±20℃以内とするのか好ましい。
Further, the present invention relates to a plurality of wafers, in which the entire surface is uniformly arranged at a predetermined interval so as to come into contact with the raw material gas, and the raw material gas is introduced from one side of the wafer arrangement and the other side. In the method of forming a polycrystalline Si film to be discharged from the side, the reaction temperature is increased stepwise in the flow direction of the raw material gas in a row of wafers to increase the thickness of the polycrystalline Si film for all wafers. Can be made uniform. The central temperature and temperature gradient in this case cannot be specified because they are determined by various conditions such as the structural dimensions of the entire apparatus, the size and number of wafers to be processed, the composition flow rate of the raw material gas, etc. Is preferably within ± 20 ° C.

【0012】以下に本発明を実施する際に用いられる反
応炉について添付図面とともに説明する。
A reactor used in carrying out the present invention will be described below with reference to the accompanying drawings.

【0013】図1において、2は本発明を実施するため
の縦型の反応炉である。該反応炉2は、石英製のアウタ
ーチューブ4及びインナーチューブ6の二重壁構造をな
しており、中央に設置されたサセプター8に複数枚のウ
ェーハWがセットされるようになっている。
In FIG. 1, 2 is a vertical reactor for carrying out the present invention. The reaction furnace 2 has a double wall structure of an outer tube 4 and an inner tube 6 made of quartz, and a plurality of wafers W are set on a susceptor 8 installed at the center.

【0014】該反応炉2の下部に設けられたガス導入口
10から炉内に導入される反応ガスはガス排出口12か
ら図示しない真空ポンプによって吸引されて排気され
る。なお、Hはヒーターである。
The reaction gas introduced into the furnace from the gas inlet 10 provided in the lower part of the reactor 2 is sucked and exhausted from the gas outlet 12 by a vacuum pump (not shown). In addition, H is a heater.

【0015】上記反応炉2は、下方から上方に反応ガス
は流れるために、下部のガス導入口10からのみ反応ガ
スを導入した場合には、反応炉2内部の反応ガスの濃度
は導入口10に近接する下部は濃く、上部にいくに従っ
て、反応ガスの濃度は薄くなるものである。この状態で
は、反応炉内の温度が上下ともに等しく設定すると下部
のウェーハには多結晶シリコン膜が厚く生成し、上部の
ウェーハには多結晶シリコン膜が薄く生成してしまう。
Since the reaction gas flows from the lower part to the upper part in the reaction furnace 2, when the reaction gas is introduced only from the lower gas introduction port 10, the concentration of the reaction gas inside the reaction furnace 2 is the introduction port 10. The lower part close to is thicker, and the concentration of the reaction gas becomes thinner as it goes to the upper part. In this state, if the temperature in the reaction furnace is set to be the same in the upper and lower sides, a thick polycrystalline silicon film is formed on the lower wafer and a thin polycrystalline silicon film is formed on the upper wafer.

【0016】この不都合を解消するために、反応炉2の
上部の温度を下部の温度よりも高く設定して上部の反応
速度を速め、反応ガスが薄い状態では反応速度を速め、
反応ガスが濃い状態では反応速度を速めないようにして
生成する多結晶シリコン膜の膜厚を均一にすることがで
きる。
In order to eliminate this inconvenience, the temperature of the upper part of the reaction furnace 2 is set higher than the temperature of the lower part to accelerate the reaction rate of the upper part, and when the reaction gas is thin, the reaction rate is increased.
When the reaction gas is rich, the film thickness of the polycrystalline silicon film produced can be made uniform without increasing the reaction rate.

【0017】図1に示した反応炉2を用い、反応ガス組
成が80%SiH4及び20%SiH4 の場合で、かつ
反応圧力を0〜0.6Torrに変化させた場合の反り
変化量の値の変化を図2に示した。この反り変化量は、
多結晶シリコン膜を生成したウェーハについて、鏡面研
磨後の反りと多結晶シリコン膜形成前のウェーハの反り
とを光干渉縞反り測定機によって測定し、その差、即ち
反り変化量(μm)=鏡面研磨処理後のウェーハの反り
(μm)−多結晶シリコン膜形成前のウェーハの反り
(μm)を示すものである。
Using the reaction furnace 2 shown in FIG. 1, when the reaction gas composition is 80% SiH 4 and 20% SiH 4 and the reaction pressure is changed to 0 to 0.6 Torr, The change in value is shown in FIG. This warp change amount is
For a wafer on which a polycrystalline silicon film is formed, the warp after mirror-polishing and the wafer before the formation of the polycrystalline silicon film are measured by an optical interference fringe warpage measuring machine, and the difference, that is, the warp change amount (μm) = mirror surface It shows the warp (μm) of the wafer after the polishing treatment-the warp (μm) of the wafer before the formation of the polycrystalline silicon film.

【0018】上記した多結晶シリコン膜の膜厚の均一化
の手法は、図1に示した縦型の反応炉2について説明し
たが、横型の反応炉についても同様に適用できることは
勿論である。
Although the above-mentioned technique for making the thickness of the polycrystalline silicon film uniform has been described for the vertical reaction furnace 2 shown in FIG. 1, it is needless to say that it can be similarly applied to a horizontal reaction furnace.

【0019】即ち、ウェーハ並びの反応ガス流の進行方
向に対して、段階的に反応温度を上昇させるように構成
することによって、生成する多結晶シリコン膜の膜厚の
均一化を図ることができる。
That is, the reaction temperature is increased stepwise with respect to the direction of flow of the reaction gas flow along the wafer, whereby the thickness of the polycrystalline silicon film produced can be made uniform. ..

【0020】上記反応炉2のサセプター8にセットされ
るウェーハWは、通常は一枚ずつセットされるため、多
結晶シリコン膜はウェーハWの全面に形成される。この
多結晶シリコン膜付きのウェーハの片面を鏡面研磨する
ことにより、ウェーハの裏面には多結晶シリコン膜が残
存形成され、前記したEG作用を果たすものである。
Since the wafers W set in the susceptor 8 of the reaction furnace 2 are usually set one by one, the polycrystalline silicon film is formed on the entire surface of the wafer W. By mirror-polishing one surface of the wafer with the polycrystalline silicon film, the polycrystalline silicon film remains on the back surface of the wafer, and the EG function described above is achieved.

【0021】多結晶シリコン膜の形成の手段としては、
上記した手段以外に、2枚のウェーハを重ね合わせてセ
ットし、多結晶シリコン膜を形成させることもできる。
この場合、2枚のウェーハのそれぞれの片面のみに多結
晶シリコン膜が形成されるから、それだけ鏡面研磨処理
を容易に行うことができる。しかも、この場合も従来の
条件方法に較べて、半導体基板の反り変形は小さいこと
が確認されている。
As means for forming a polycrystalline silicon film,
In addition to the above-mentioned means, two wafers may be superposed and set to form a polycrystalline silicon film.
In this case, since the polycrystalline silicon film is formed on only one surface of each of the two wafers, the mirror-polishing process can be easily performed. Moreover, in this case as well, it has been confirmed that the warp deformation of the semiconductor substrate is small as compared with the conventional method.

【0022】[0022]

【作用】半導体基板における反りの発生は、CVD法に
より形成されるSi多結晶内、又は同多結晶とウェーハ
のSi単結晶界面部分で生じる応力が原因であると考え
られる。
The warpage of the semiconductor substrate is considered to be caused by the stress generated in the Si polycrystal formed by the CVD method or at the interface between the polycrystal and the Si single crystal of the wafer.

【0023】この応力のある部分は熱処理に際し、基板
境界における転位や積層欠陥を発生せしめ、本発明の半
導体基板のEG源として作用する。ところでこのような
Si多結晶膜がウェーハの全表面に対して均一な膜厚と
結晶質でカバーされる場合、これらの応力は全表面に対
して均一に作用するため、外観上のウェーハ変形は起こ
らないが、その片側面のSi多結晶膜を除去して鏡面加
工した半導体基板においては、前記膜に起因の応力のバ
ランスが崩れ、鏡面側が凹状態の変形を生じる。本発明
者等は、この変形防止について検討した結果、本発明の
ように反応圧力を所定の圧力範囲に低下させることによ
り、ウェーハの反りの増大が防止されることを見出し本
発明を完成したものである。
During the heat treatment, this stressed portion causes dislocations and stacking faults at the substrate boundary, and acts as an EG source for the semiconductor substrate of the present invention. By the way, when such a Si polycrystalline film is covered with a uniform film thickness and crystallinity on the entire surface of the wafer, since these stresses act uniformly on the entire surface, the wafer deformation in appearance does not occur. Although it does not occur, in a semiconductor substrate in which the Si polycrystalline film on one side surface is removed and mirror processing is performed, the stress balance due to the film is lost and the mirror surface side is deformed in a concave state. As a result of studying the prevention of deformation, the present inventors have completed the present invention by finding that an increase in wafer warpage is prevented by reducing the reaction pressure to a predetermined pressure range as in the present invention. Is.

【0024】その理由をさらに検討したところ、本発明
の低圧条件においては、顕微鏡によるSi多結晶表面の
凹凸状態で観察される結晶粒が大きく成長していること
があり、この結晶粒の大小と反り発生の大小の因果関係
が確認されたことである。即ち、結晶粒の成長が大きい
場合、同結晶粒とウェーハのSi単結晶面との接触面積
は小さくなり、しかも結晶粒相互間の応力は減少する
が、従来の条件のように結晶粒が小さい場合には前記応
力は増大し、ウェーハの反り発生を大きくするものと推
定される。この結晶粒は、反応原料ガスの濃度及び反応
温度を高めると大きくなるが、この場合は形成されるS
i多結晶の膜厚分布が乱れはじめ、結果的に半導体基板
の品質と製造歩留を低下させることになる。
Upon further studying the reason for this, under the low pressure condition of the present invention, the crystal grains observed in the concavo-convex state of the Si polycrystal surface under the microscope sometimes grow large. That is, the causal relationship between the occurrence of warpage and the occurrence of warpage was confirmed. That is, when the growth of the crystal grains is large, the contact area between the crystal grains and the Si single crystal surface of the wafer is small, and the stress between the crystal grains is reduced, but the crystal grains are small as in the conventional condition. In this case, it is estimated that the stress increases and warpage of the wafer increases. The crystal grains become larger as the concentration of the reaction raw material gas and the reaction temperature increase, but in this case, S formed.
The film thickness distribution of i-polycrystal begins to be disturbed, and as a result, the quality and manufacturing yield of the semiconductor substrate are reduced.

【0025】しかし、原料ガスの圧力を非常に低くする
本発明方法は、半導体基板の反り発生を減少せしめ、結
果としてその製造歩留を向上させるので、多少の生産性
を犠牲にしても産業上の利用効果は十分に発揮される。
However, the method of the present invention in which the pressure of the raw material gas is made extremely low reduces the occurrence of warpage of the semiconductor substrate and consequently improves the production yield thereof, so that it is industrially possible even if some productivity is sacrificed. The use effect of is fully demonstrated.

【0026】[0026]

【実施例】次に、本発明の実施例を比較例とともにあげ
て説明する。なお、実施例中の%は重量%を意味する。 実施例1 図1と同様の反応炉を用い、直径150mmの80枚の
ウェーハを炉内にセットし、反応温度635℃の全領域
均熱、真空度0.18Torr、反応ガス組成はSiH
4 20%で残部はヘリウムガス、ガス流量0.50l/
minの条件で、多結晶シリコン膜の膜厚を反応炉の底
部で0.8μmねらいとして多結晶シリコン膜の生成反
応を行った。
EXAMPLES Next, examples of the present invention will be described together with comparative examples. In the examples,% means% by weight. Example 1 A reaction furnace similar to that shown in FIG. 1 was used, 80 wafers having a diameter of 150 mm were set in the furnace, the reaction temperature was 635 ° C., the entire area was soaked, the degree of vacuum was 0.18 Torr, and the reaction gas composition was SiH.
4 20%, balance helium gas, gas flow 0.50 l /
Under the condition of min, the polycrystalline silicon film generation reaction was performed with the thickness of the polycrystalline silicon film set at 0.8 μm at the bottom of the reaction furnace.

【0027】生成した多結晶シリコン膜の膜厚をエリプ
ソメーターによって測定し、炉内のウェーハのセット位
置との関連を図3に示した。以下の図3〜図7におい
て、横軸のウェーハ位置の左端が底部(BTM)、右端
が頂部(TOP)を示している。図3の結果から、反り
変化量の値は35μm以内であり、ウェーハの反りが改
善されていることが確認できた。
The thickness of the produced polycrystalline silicon film was measured by an ellipsometer, and the relationship with the set position of the wafer in the furnace is shown in FIG. In FIGS. 3 to 7 below, the left end of the wafer position on the horizontal axis indicates the bottom (BTM) and the right end indicates the top (TOP). From the result of FIG. 3, the value of the amount of change in warp was within 35 μm, and it was confirmed that the warp of the wafer was improved.

【0028】比較例1 真空度0.50Torrとした以外は、実施例1と同様
にして多結晶シリコン膜の生成反応を行い、膜厚と反り
変化量とを測定して図4に示した。同図の結果から、反
り変化量の値は60μmを越え、ウェーハの反りは大き
いことがわかる。
Comparative Example 1 A polycrystalline silicon film formation reaction was performed in the same manner as in Example 1 except that the degree of vacuum was 0.50 Torr, and the film thickness and the amount of change in warpage were measured and shown in FIG. From the results shown in FIG. 6, it can be seen that the amount of change in warp exceeds 60 μm and the warp of the wafer is large.

【0029】実施例2 真空度0.10Torr、反応ガス組成はSiH4 80
%で残部はヘリウムガス、ガス流量0.24l/min
とした以外は、実施例1と同様にして多結晶シリコン膜
の生成反応を行い、膜厚と反り変化量とを測定して図5
に示した。同図の結果から、反り変化量の値は40〜5
5μm程度であり、ウェーハの反りは改善されているこ
とが確認できた。
Example 2 A vacuum degree of 0.10 Torr and a reaction gas composition of SiH 4 80
% Balance helium gas, gas flow 0.24 l / min
5A and 5B, the polycrystalline silicon film formation reaction was performed in the same manner as in Example 1 except that the above was used, and the film thickness and the amount of change in warpage were measured.
It was shown to. From the result of the figure, the value of the warp change amount is 40 to 5
It was about 5 μm, and it was confirmed that the warp of the wafer was improved.

【0030】比較例2 真空度0.50Torrとした以外は、実施例2と同様
にして多結晶シリコン膜の生成反応を行い、膜厚と反り
変化量とを測定して図6に示した。同図の結果から、反
り変化量の値は60〜120μmと増大している。
Comparative Example 2 A polycrystalline silicon film formation reaction was performed in the same manner as in Example 2 except that the degree of vacuum was 0.50 Torr, and the film thickness and the amount of change in warpage were measured and shown in FIG. From the result of FIG. 5, the value of the amount of change in warpage increases to 60 to 120 μm.

【0031】実施例3 図1における反応炉の底部(BTM)、中央部(CT
R)及び頂部(TOP)の温度をそれぞれ、640℃、
650℃及び665℃と設定した以外は、実施例1と同
様にして多結晶シリコン膜の生成反応を行い、膜厚と反
り変化量とを測定して図7に示した。同図の結果から、
反り変化量の値は底部、中央部及び頂部の全てにおいて
10〜20μmの範囲で均一であり、かつ膜厚も均一で
あることが確認された。
Example 3 The bottom (BTM) and the center (CT) of the reactor shown in FIG.
R) and the temperature of the top (TOP) are 640 ° C. and
A polycrystalline silicon film formation reaction was performed in the same manner as in Example 1 except that the temperatures were set to 650 ° C. and 665 ° C., and the film thickness and the amount of change in warpage were measured and shown in FIG. From the result of the figure,
It was confirmed that the amount of change in warpage was uniform in the range of 10 to 20 μm in all of the bottom, center and top, and the film thickness was also uniform.

【0032】[0032]

【発明の効果】以上のべたごとく、本発明によれば、ウ
ェーハ上に多結晶シリコン膜を形成するに際し、当該ウ
ェーハが鏡面研磨処理を受けても反りが増大することが
なく、デバイスの特性や歩留の低下が生じないようにす
ることができる。
As described above, according to the present invention, when a polycrystalline silicon film is formed on a wafer, warpage does not increase even if the wafer is subjected to mirror polishing, and the device characteristics and It is possible to prevent the yield from decreasing.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明方法に用いられる縦型反応炉の一例を示
す概略説明図である。
FIG. 1 is a schematic explanatory view showing an example of a vertical reactor used in the method of the present invention.

【図2】本発明方法の一態様を実施した場合における反
応圧力と反り変化量の関係を示すグラフである。
FIG. 2 is a graph showing the relationship between reaction pressure and the amount of change in warp when one embodiment of the method of the present invention is carried out.

【図3】実施例1におけるウェーハ位置と、膜厚及び反
り変化量との関係を示すグラフである。
FIG. 3 is a graph showing the relationship between the wafer position and the film thickness and the amount of change in warpage in Example 1.

【図4】比較例1におけるウェーハ位置と、膜厚及び反
り変化量との関係を示すグラフである。
FIG. 4 is a graph showing a relationship between a wafer position and a film thickness and a warp change amount in Comparative Example 1.

【図5】実施例2におけるウェーハ位置と、膜厚及び反
り変化量との関係を示すグラフである。
FIG. 5 is a graph showing the relationship between the wafer position and the film thickness and the amount of change in warpage in Example 2.

【図6】比較例2におけるウェーハ位置と、膜厚及び反
り変化量との関係を示すグラフである。
FIG. 6 is a graph showing a relationship between a wafer position and a film thickness and a warp change amount in Comparative Example 2.

【図7】実施例3におけるウェーハ位置と、膜厚及び反
り変化量との関係を示すグラフである。
FIG. 7 is a graph showing the relationship between the wafer position and the film thickness and the amount of change in warpage in Example 3.

【符号の説明】[Explanation of symbols]

2 反応炉 4 アウターチューブ 6 インナーチューブ 8 サセプター 10 ガス導入口 12 ガス排出口 2 Reactor 4 Outer tube 6 Inner tube 8 Susceptor 10 Gas inlet 12 Gas outlet

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 Si(シリコン)単結晶からなるウェー
ハに関して、半導体素子形成を行う面は鏡面であり、そ
の裏面側には多結晶Si膜を形成せしめた構造を有する
半導体基板の製造において、前記多結晶Si膜の形成
は、原料ガスの組成をSiH4 (モノシラン)10〜1
00重量%で残部は不活性ガスとし、その反応温度を6
00〜700℃、反応時の圧力を0.01〜0.3To
rrの範囲内とすることを特徴とする半導体基板の製造
方法。
1. A wafer made of Si (silicon) single crystal, a surface on which a semiconductor element is formed is a mirror surface, and a back surface side thereof has a structure in which a polycrystalline Si film is formed. The formation of the polycrystalline Si film is performed by changing the composition of the source gas to SiH 4 (monosilane) 10-1.
The reaction temperature is 6
00-700 ° C., pressure during reaction 0.01-0.3 To
A method of manufacturing a semiconductor substrate, characterized in that it is within the range of rr.
【請求項2】 前記ウェーハの複数枚に関し、その全表
面が原料ガスと接触するように所定の間隔で一様に配列
し、原料ガスはそのウェーハ並びの一方側より導入し、
その他方側より排出するようにした前記多結晶Si膜を
形成させる方法において、ウェーハ並びの前記原料ガス
の流れ進行方向に対して、段階的に前記反応温度を上昇
させることを特徴とする請求項1記載の方法。
2. The plurality of wafers are uniformly arranged at a predetermined interval so that the entire surface of the plurality of wafers comes into contact with the raw material gas, and the raw material gas is introduced from one side of the wafer row,
The method for forming the polycrystalline Si film to be discharged from the other side, wherein the reaction temperature is raised stepwise with respect to the flow direction of the raw material gas in a row of wafers. The method described in 1.
JP3311764A 1991-10-29 1991-10-29 Semiconductor substrate manufacturing method Expired - Lifetime JP2723725B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3311764A JP2723725B2 (en) 1991-10-29 1991-10-29 Semiconductor substrate manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3311764A JP2723725B2 (en) 1991-10-29 1991-10-29 Semiconductor substrate manufacturing method

Publications (2)

Publication Number Publication Date
JPH05121415A true JPH05121415A (en) 1993-05-18
JP2723725B2 JP2723725B2 (en) 1998-03-09

Family

ID=18021207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3311764A Expired - Lifetime JP2723725B2 (en) 1991-10-29 1991-10-29 Semiconductor substrate manufacturing method

Country Status (1)

Country Link
JP (1) JP2723725B2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120777A (en) * 1976-04-02 1977-10-11 Ibm Ic
JPS57187941A (en) * 1981-05-14 1982-11-18 Nec Corp Manufacture of semiconductor substrate
JPS59186331A (en) * 1983-04-04 1984-10-23 モンサント・コンパニ− Method of producing semiconductor substrate
JPS61276329A (en) * 1985-05-31 1986-12-06 Mitsubishi Electric Corp Semiconductor manufacturing equipment
JPH02281614A (en) * 1989-04-21 1990-11-19 Kyushu Electron Metal Co Ltd Manufacture of polycrystalline silicon thin film

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120777A (en) * 1976-04-02 1977-10-11 Ibm Ic
JPS57187941A (en) * 1981-05-14 1982-11-18 Nec Corp Manufacture of semiconductor substrate
JPS59186331A (en) * 1983-04-04 1984-10-23 モンサント・コンパニ− Method of producing semiconductor substrate
JPS61276329A (en) * 1985-05-31 1986-12-06 Mitsubishi Electric Corp Semiconductor manufacturing equipment
JPH02281614A (en) * 1989-04-21 1990-11-19 Kyushu Electron Metal Co Ltd Manufacture of polycrystalline silicon thin film

Also Published As

Publication number Publication date
JP2723725B2 (en) 1998-03-09

Similar Documents

Publication Publication Date Title
KR100828622B1 (en) Epitaxially coated silicon wafer
JP4723446B2 (en) Epitaxial silicon wafer and method of manufacturing epitaxial silicon wafer
US8268708B2 (en) Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers
WO2018120731A1 (en) Manufacturing method for silicon epitaxial wafer
US10961638B2 (en) Method for epitaxially coating semiconductor wafers, and semiconductor wafer
WO2008075449A1 (en) Method for manufacturing deformation silicon substrate
KR101559977B1 (en) Silicon epitaxial wafer and method for manufacturing the same
JP3454033B2 (en) Silicon wafer and manufacturing method thereof
US6703290B2 (en) Growth of epitaxial semiconductor material with improved crystallographic properties
KR101364995B1 (en) Method for Manufacturing Semiconductor Substrate
WO2010035409A1 (en) Process for producing silicon epitaxial wafer
JP2911694B2 (en) Semiconductor substrate and method of manufacturing the same
JP7231120B2 (en) Epitaxial wafer manufacturing method
JPH09266212A (en) Silicon wafer
JP2723725B2 (en) Semiconductor substrate manufacturing method
JP2003188107A (en) Manufacturing method for semiconductor epitaxial wafer and the semiconductor epitaxial wafer
JPH0774114A (en) Barrel type susceptor for vapor phase epitaxy
JP2983322B2 (en) Manufacturing method of epitaxial wafer
JPS60193324A (en) Manufacture of semiconductor substrate
WO2022075369A1 (en) Method for producing silicon epitaxial wafer
CN118866710A (en) Method for improving warpage of monocrystalline silicon wafer with polycrystalline silicon back seal
CN115198352B (en) Epitaxial growth method and epitaxial wafer
JPS5928329A (en) Epitaxial growth method of silicon
KR100830997B1 (en) Method of fabricating silicon epitaxial wafer with improved flatness
JP2015204325A (en) Epitaxial wafer manufacturing method

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071128

Year of fee payment: 10

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081128

Year of fee payment: 11

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081128

Year of fee payment: 11

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 11

Free format text: PAYMENT UNTIL: 20081128

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091128

Year of fee payment: 12

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091128

Year of fee payment: 12

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 13

Free format text: PAYMENT UNTIL: 20101128

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111128

Year of fee payment: 14

EXPY Cancellation because of completion of term