JPH05120456A - Single chip microprocessor - Google Patents

Abstract

PURPOSE:To exactly measure an event clock input by storing the number of times of an overflow interruption in a memory at each time of the overflow interruption, and reading the content of the memory and the value of a count register after the completion of the measurement. CONSTITUTION:The event timer of a 1-chip-microprocessor is constituted of a counter register 1, input terminal 2 which inputs an event clock CL, data set circuit 3, and data bus 6 of the count register 1. When the event clock CL overflows the count register 1, an overflow interruption circuit 7 outputs an overflow interruption signal OV, and the number of times of the interruption is stored in a memory 5 by the overflow interruption signal OV. Therefore, even when the even clock CL overflows the count register 1, the exact value can be read in.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an event counter for a one-chip microprocessor.

[0002]

2. Description of the Related Art Conventionally, an event clock input terminal 2 and a set circuit 3 of a count register 1 as shown in FIG.
Also, an event timer including a circuit for outputting the value of the count register 1 has been informed. An event clock is input to the input terminal 2. In addition, 4 is a CPU and 6 is a data bus.

[0003]

However, the event counter of the conventional one-chip microprocessor has a problem that an accurate value cannot be read when the number of event inputs exceeds the number that can be measured by the event counter. Therefore, an object of the present invention is to solve such a problem in the related art, and an object thereof is to obtain an accurate value of the event clock input even when the event counter of the one-chip microprocessor overflows.

Another object of the present invention is to solve the conventional problems as described above, and to obtain an accurate value of the event clock input even when the event counter of the one-chip microprocessor becomes zero. It is an object.

[0005]

In order to solve the above-mentioned problems, the present invention provides an event counter of a one-chip microprocessor with an overflow interrupt circuit in a count register and a memory circuit for storing the number of overflow interrupts. In addition, even if there are more event clock inputs to the event counter than can be measured, the accurate value of the event clock input can be obtained by reading the memory value and the count register value.

According to another aspect of the invention, in order to solve the above-mentioned problems, the present invention provides a zero interrupt circuit in a count register and a memory circuit for storing the number of zero interrupts in an event counter of a one-chip microprocessor. By adding, even if there are more event clock inputs than the event counter can measure,
An accurate value of the event clock input can be obtained by reading the value of the memory and the value of the count register.

[0007]

In the one-chip microprocessor configured as described above, when the event counter has more event inputs than the count register can measure,
Each time the data overflows, an overflow interrupt is output from the count register, and the number of interrupt clocks is stored in memory for each overflow interrupt. By reading the value and the value of the count register, it is possible to measure accurately.

In another invention, in the one-chip microprocessor configured as described above, when the event counter has more event inputs than can be measured by the count register, every time the data becomes zero. Even if there are more event clock inputs than can be measured by the event counter by outputting zero interrupt from the count register to the memory and storing the interrupt count in the memory for each zero interrupt, the memory value and count register It becomes possible to measure accurately by reading the value of.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, a count register 1, an input terminal 2 to which the event clock CL is input, a data set circuit 3, and an event timer of a one-chip microprocessor configured by a data bus 6 of the count register 1 are used. However, if the count register 1 overflows, the overflow interrupt circuit 7
Outputs an overflow interrupt signal OV, and the overflow interrupt signal OV causes the memory 5 to store the number of interrupts, so that an accurate value can be read even if the count register 1 overflows.

FIG. 2 shows another embodiment of the present invention. In FIG. 2, the count register 1 and the event clock CL
In the event timer of the one-chip microprocessor configured by the input terminal 2 to which is input, the data set circuit 3, and the data bus 6 of the count register 1, the event clock CL becomes zero when the count register 1 is set to zero. The interrupt circuit 9 outputs a zero interrupt signal INT,
By storing the number of interrupts in the memory 5 with the zero interrupt signal INT, an accurate value can be read even if the count register 1 becomes zero.

[0011]

As described above, according to the present invention, even if the event clock input exceeds the count register measurable range by the event timer of the one-chip microprocessor, it overflows every time the event clock input overflows the count register. Since the overflow output signal is output from the interrupt output circuit and the number of overflow interrupts is stored in the memory for each overflow interrupt, the measurement is completed even if the count register of the event counter exceeds the event clock input range that can be measured. After that, the event clock input can be accurately measured by reading the contents of the memory and the value of the count register.

Further, another invention is, as described above, 1
Even if an event clock input exceeds the count register's measurable range with the chip microprocessor's event timer, a zero interrupt signal is output from the zero interrupt output circuit every time the count register becomes 0, and a zero interrupt signal is output. Since the number of zero interrupts is stored in the memory, even if the count register of the event counter exceeds the input range of the event clock that can be measured, the contents of the memory and the value of the count register can be read after the measurement is completed. Has the effect of accurately measuring the event clock input.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an event timer of a one-chip microprocessor of the present invention.

FIG. 2 is an explanatory diagram showing an event timer of another one-chip microprocessor of the present invention.

FIG. 3 is an explanatory diagram of a conventional event timer of a 1-chip microprocessor.

[Explanation of symbols]

 1 Count Register 2 Input Terminal 3 Data Set Circuit 4 CPU 5 Memory 6 Data Bus 7 Overflow Interrupt Circuit 8 Overflow Interrupt Signal 9 Zero Interrupt Circuit 10 Zero Interrupt Signal

Claims (2)

[Claims] 1. An overflow counter circuit and an overflow interrupt in a memory for each overflow interrupt in an event counter composed of a count register having an event clock input, a count register setting function, and a function for outputting the value of the count register. A one-chip microprocessor characterized by having a circuit for storing the number of interrupts. 2. An event counter composed of a count register having an event clock input, a count register setting function, and a count register value output function, a zero interrupt circuit, and a zero memory in each zero interrupt. A one-chip microprocessor characterized by having a circuit for storing the number of interrupts.