JP2970412B2 - Time A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time A / D converter for converting a minute time into a numerical value such as a phase difference between two pulse signals having an arbitrary phase relationship. This time A / D converter can be applied to, for example, a laser radar device that measures a distance from a reflected wave of a laser beam to an object from accurate measurement of a phase difference between two pulses.

[0002]

2. Description of the Related Art Conventionally, as this type of device, there is a time A / D converter disclosed in Japanese Patent Application Laid-Open No. 5-37378. This time A / D converter uses a pulse phase difference converting circuit as shown in FIG. In FIG. 8, a plurality of delay elements (gate delays) are connected in a ring to form a ring delay pulse generation circuit 1, and a pulse signal (first pulse signal) PA input at an arbitrary timing is circulated. At the same time, the number of orbits is counted by the counter 2 and the orbiting position of the pulse signal PA is specified by the pulse selector 3 by another pulse signal (detection pulse signal) PB input with an arbitrary phase difference, and the specified position is determined. Encoding is performed by the encoder 4. The phase difference (time difference) between the two pulse signals PA and PB is obtained as a digital value, that is, encoded, based on the encoded specific position and the count number of the counter 2. The encoded signal is latched by the latch circuit 5.

[0003] With such a configuration, the gate delay 1
Two pulse signals P with high resolution due to the delay time of the stage
The time difference between A and PB can be detected.

[0004]

However, the above-mentioned time A / D converter is used for measuring the optical round-trip time of a laser radar.
For example, when an attempt is made to measure the position of a preceding vehicle using a laser radar, a plurality of pulse signals PB indicating the input timing of reflected light are generated for each input of reflected light, and a plurality of pulses are generated at such irregular timings. For the signal PB, since the circuit performs the latch operation etc. in an unstable state,
There is a problem that accurate data cannot be obtained.

The present invention has been made in view of the above problems, and has as its object to obtain stable data for a plurality of pulse signals input at irregular timings.

[0006]

According to the present invention, in order to achieve the above object, a first pulse signal (PA) is inputted and a plurality of the first pulse signals are inputted. While passing through the delay element, a plurality of detection pulse signals (P
When B) is input, the phase difference between each of the first pulse signal and the plurality of pulse signals is encoded by the number of delay elements through which the first pulse signal has passed to obtain measurement time difference data. In the time A / D converter, the first pulse signal and the subsequent detection pulse signal are input for a subsequent detection pulse signal input within a predetermined period from the input time point of the detection pulse signal. Prohibition means (230-250) for prohibiting the operation of encoding the phase difference of
It is characterized by having provided.

According to the second aspect of the present invention, an input means (100) for inputting a pulse signal and a plurality of first pulse signals (PA) when the first pulse signal is input to the input means. And when a plurality of temporally different detection pulse signals (PB) are input to the input means after the input of the first pulse signal,
A time A / D converter that encodes the phase difference between the first pulse signal and the plurality of pulse signals by the number of delay elements that have passed the first pulse signal to obtain measurement time difference data. Wherein, during a predetermined period after the detection pulse signal is input to the input means, a prohibition means (230 to 250) for prohibiting the input operation of the input means with respect to a subsequent detection pulse signal is provided. Features.

According to a third aspect of the present invention, in the second aspect of the present invention, the prohibiting means determines a predetermined mask time based on a signal indicating that the detection pulse signal has been input to the input means. Circuit means (230 to 250) for generating a signal corresponding to the above, and the input operation of the input means within the predetermined period is inhibited by the signal from the circuit means.

According to a fourth aspect of the present invention, in the second or third aspect of the present invention, the generation timing detecting means (350) for detecting the generation timing of the subsequent detection pulse signal generated following the detection pulse signal. ~ 370,3
80 to 382, 510 to 534) and a period for changing the predetermined period for the next detection of the subsequent detection pulse signal based on the generation timing of the subsequent detection pulse signal detected by the generation timing detection means. Change means (245, 246, 260, 500-502)
It is characterized by having.

According to a fifth aspect of the present invention, in the first aspect of the present invention, the two pulse signals (S) for measuring the reference time having phases different from each other by the reference time are used.
Means (TDPA, STDPB) for encoding the phase difference between the two pulse signals based on the number of passing through the plurality of delay elements to obtain reference time difference data (pulse based on the two pulse signals from the reference signal generation circuit 170) (A part for obtaining reference time difference data by the phase difference encoding circuit 110), and a correcting means (150) for correcting the measured time difference data with the reference time difference data.

According to a sixth aspect of the present invention, in the fifth aspect of the present invention, a reference signal generating means (170) for generating the two pulse signals for the reference time measurement is provided. In the invention described in claim 7, in the invention described in claim 6, the input means includes the first
Means (300, 310) for selectively performing the input of the pulse signal and the following plurality of detection pulse signals and the input of the two pulse signals from the reference signal generating means.
And the operation of obtaining the measured time difference data and the operation of obtaining the reference time difference data are performed in a time-sharing manner using the plurality of delay elements.

According to an eighth aspect of the present invention, in the first aspect of the present invention, the means (230) for limiting the number of the plurality of detection pulse signals input to the input means. ). According to a ninth aspect of the present invention, in accordance with any one of the second to eighth aspects, a plurality of storages respectively storing a plurality of measurement time difference data obtained for the plurality of detection pulse signals. Means (120 to 122).

According to a tenth aspect of the present invention, in the first aspect of the present invention, the plurality of delay elements include a ring delay pulse generating means (1) having a ring shape. Counting means (2) for counting the number of times the first pulse signal circulates through the plurality of ring-shaped delay elements; and determining a passage position of the first pulse signal at the time when the detection pulse signal is input. A position specifying means (3, 4) for specifying, wherein the measurement time difference data is obtained from the count value of the counting means and the specific position of the position specifying means.

The reference numerals in parentheses of the above means indicate the correspondence with the concrete means described in the embodiments described later.

[0015]

According to the first aspect of the present invention, when a first pulse signal is input, the first pulse signal is passed through a plurality of delay elements. Thereafter, when a plurality of temporally different detection pulse signals are input, the phase difference between the first pulse signal and the plurality of pulse signals is determined by the number of delay elements through which the first pulse signal has passed. Is encoded to obtain measurement time difference data. Here, a phase difference between the first pulse signal and the subsequent detection pulse signal is encoded for a subsequent detection pulse signal input within a predetermined period from the input time point of the detection pulse signal. Operation is prohibited.

Therefore, if the encoding operation for the subsequent detection pulse signal is performed before the operation for encoding the phase difference between the first pulse signal and the detection pulse signal is unstable, unstable data may be obtained. However, since the encoding operation is prohibited for a subsequent detection pulse signal input within such a predetermined period, a subsequent detection pulse signal outside such a period is prohibited. By performing the encoding operation, stable measurement time difference data can be obtained.

According to the second aspect of the present invention, the input means for inputting a pulse signal is supplied to a subsequent detection pulse signal within a predetermined period from the time when the detection pulse signal is input to the input means. The input operation of the input means is prohibited. Therefore, the input operation during the predetermined period in the unstable state as described above is prohibited, and the effect as described in claim 1 is achieved.

According to a third aspect of the present invention, the predetermined period is a predetermined mask time created based on a signal indicating that the detection pulse signal has been input to the input means. Can be. In the invention described in claim 4, the predetermined period for the detection of the next subsequent detection pulse signal is changed based on the generation timing of the subsequent detection pulse signal.

Therefore, when the subsequent detection pulse signal is in a delicate positional relationship with a predetermined period in which input operation is inhibited or not, the detection pulse signal is detected in each detection. Can be eliminated by a so-called hysteresis effect. Also, in the invention according to claim 5, the reference time measuring second phase having a phase different by the reference time is used.
Using one pulse signal, the phase difference between the two pulse signals is encoded based on the number of passing through the plurality of delay elements to obtain reference time difference data, and the measured time difference data is corrected with the reference time difference data. .

Therefore, even when the plurality of delay elements are affected by fluctuations in temperature and power supply voltage, data showing a high-precision phase difference can be obtained by correction using the reference time difference data. The two pulse signals for measuring the reference time can be obtained by a reference signal generating means for generating two pulse signals for measuring the reference time.

Further, in the invention according to claim 7,
The input of the first pulse signal and the plurality of detection pulse signals following the first pulse signal and the second pulse from the reference signal generating means.
By selectively performing the input of two pulse signals and performing the operation of obtaining the measured time difference data and the operation of obtaining the reference time difference data in a time-division manner, a plurality of delay elements are provided for each operation. Because they are commonly used,
The circuit area for that purpose can be reduced.

In the invention according to claim 8, since the number of the plurality of detection pulse signals inputted to the input means is limited, unnecessary encoding operation or the like for detection pulses other than the number is prevented. However, only data for a desired detection pulse can be obtained. In addition, for a plurality of measurement time difference data obtained for a plurality of detection pulse signals as described above, the respective data are stored in a plurality of storage units, respectively. By doing so, data processing can be performed based on the plurality of stored data.

Further, in order to specify the number of the plurality of delay elements as described above, the plurality of delay elements are formed in a ring shape, and the plurality of delay elements are formed in a ring shape. Can be performed based on the number of times the first pulse signal circulates and the specific position of the passage position of the first pulse signal at the time when the detection pulse signal is input.

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. First, the basic concept of this embodiment will be described. In this type of time A / D converter, the delay time per one stage of the gate delay is easily affected by fluctuations in temperature and power supply voltage. For this reason, Japanese Patent Application Laid-Open No. 5-37
Japanese Patent Publication No. 378 discloses a configuration as shown in FIG.

That is, when detecting the time difference between the two pulse signals PA and PB, another pulse signal PC is used, and this pulse signal PC is output by a crystal oscillator and a counter exactly after a predetermined time from the generation of the pulse signal PA. It shall be output. Then, the pulse signal PB is first selected by the SEL signal, and the pulse phase difference encoding circuit 100 detects a digital value D _AB corresponding to the time difference T _AB between the two pulse signals PA and PB. Thereafter, the pulse signal PC is selected by the SEL signal, and the digital value D _AC corresponding to the time difference T _AC between the pulse signals PA and PC is detected. That is, both digital values D _AB and D _AC are detected in a time division manner. Here, since the value of T _AC is set to an accurate time by a crystal oscillator or the like, the measurement time T _AB is T _AB =
(D _AB / D _AC ) · T _AC .

In this embodiment, a digital value for measurement and a digital value for reference are obtained by pulse signal input by time division as described above, and the division (relative ratio operation)
The measurement time is determined. However, when the reference digital value is obtained, the pulse signal PA
However, in this embodiment, two pulse signals STDPA and STDPB for measuring the reference time are used. (First Embodiment) FIG. 1 shows a first embodiment of the present invention.

In FIG. 1, an input signal switching circuit 10
0, pulse phase difference encoding circuit 110, division circuit 150
Respectively correspond to the signal switching portion by the SEL signal, the pulse phase difference encoding circuit 10 and the division circuit 11 in FIG. Note that the pulse phase difference encoding circuit 110 is the same as that shown in FIG. 8, except that if the pulse signal PB is not input and the counter 2 overflows, an overflow (OV) signal is output. It is configured.

Here, the above-mentioned pulse signal STDPA,
The STDPB is output as a high-precision pulse signal by the reference signal generation circuit 170 by a crystal oscillator and a counter that counts the oscillation pulses. The configuration of this part is the same as the configuration of the crystal oscillator and the counter shown in FIG. 3 of JP-A-5-37378. This embodiment is applied to the measurement of the optical round-trip time of a laser radar, similar to the one disclosed in Japanese Patent Application Laid-Open No. 5-37378. First, the input pulse signal PA rising in response to the laser beam emission time and the input pulse signal PB rising in response to the laser beam reception time are input to the pulse phase difference encoding circuit 110 via the input signal switching circuit 100, respectively. To obtain a digital value indicating the time difference. Thereafter, the input signal switching circuit 100 is switched to the reference signal generation circuit 17.
0, the signal is switched to the signal input side, and the pulse signal STDPA,
The STDPB is input to the pulse phase difference encoding circuit 110 to obtain a digital value indicating the time difference. When the two digital values are completed, the two digital values are divided by a divider circuit 150 to obtain an accurate optical round trip time of the laser radar in which the fluctuations of the temperature and the power supply voltage are compensated.

Here, in order to repeat the above operation, the main sequencer 190, the PB measurement sequencer 18
0, furthermore, buffer registers (BFR) 120 to 122 for writing (storing) and transferring data, buffer gates (BPGT) 123 to 126, and a register (CV).
R) 140-144, transfer gate (CVGT)
145 to 148 are provided. The dividing circuit 15
The data obtained by dividing by 0 is stored in the register (DTR)
The data is written to 160 to 163 and output as measurement data from data gates (DTGT) 164 to 167.

The main sequencer 190 follows the flow shown in FIG. 4 to set MSQ0, SIGRST, START,
A SIGMPX signal or the like is output. This MSQ0 signal is for distinguishing between PB measurement and reference signal measurement.
It is at a low level during PB measurement and at a high level during reference signal measurement. The SIGRST signal is input signal switching circuit 10 for starting PB measurement and reference signal measurement.
0, for resetting the reference signal generation circuit 170 The START signal is for giving a timing for generating the pulse signals STDPA and STDPB from the reference signal generation circuit 170. The SIGMPX signal is applied to the input of the input signal switching circuit 100 as input pulse signals PA and P.
This is for selecting either the B side or the reference pulse signal STDPA or STDPB side.

The input pulse signals PA and STDPA,
The signal selected by the SIMMPX signal of the input pulse signal PB and STDPB becomes the PACK and PBCK signals. The PB measurement sequencer 180 identifies which of the PB measurement and the reference signal measurement by the MSQ0 signal from the main sequencer 190,
PACK and PBCK signals are input from 0 to control write timing of the buffers 120 to 122 and control the number of pulse signals PB to be taken. FIG. 2 shows a specific configuration of the PB measurement sequencer 180.

D type flip-flops 210-212
And the decoder 200 constitute a sequencer.
The decoder 200 is initialized by the MSQ0 and PACK signals. D-type flip-flops 210 to 212
The output state of the decoder 200 is stored and output each time the PBCK signal is input. The decoder 200 receives the outputs of the D-type flip-flops 210 to 212 and sequentially changes the outputs. Therefore, the outputs of the D-type flip-flops 210 to 212 change every time the PBCK signal is input. That is, the decoder 200 and the D-type flip-flops 210 to 212 function as a counter that counts the input of the PBCK signal and outputs a value corresponding thereto.

D type flip-flops 210-212
Are decoded by the decoders 220 to 222.
These decoded values correspond to the number of times the PBCK signal has been generated, and are stored in the buffer registers 120-1.
22 to give respective write timings. The circuits 230 to 250 are for generating a mask time for the pulse signal PB input irregularly. During this mask time, even if the next pulse signal PB is input, the rising signal is ignored. This is because when the pulse signal PB is input irregularly and the pulse signal is measured, the next pulse measurement is performed when the operation of the latch circuit 5 and the like of the pulse phase difference encoding circuit 110 is unstable. In order to prevent unstable output as a result. Therefore, for the time until the operation of the latch circuit 5 and the like is stabilized, the input of the pulse signal PB is masked, and the signal for the mask is applied to these circuits 230-2.
At 50, it is created.

In this embodiment, the input of the pulse signal PB is limited to four, so that the measurement circuit 230 detects whether four pulse signals PB have been measured during the PB measurement. . In the measurement circuit 231,
Whether or not the reference signal is being measured is detected based on the signal level of MSQ0. The measurement time end detection circuit 232 detects whether or not the pulse phase difference encoding circuit 110 has generated an OV signal indicating an overflow. Each of these circuits generates a high-level signal when the above detection is performed.

When the outputs of the circuits 230 to 232 are all low, the output of the OR circuit 233 is low. In this state, the D-type flip-flop 240 and the coincidence circuit 241 receive the PBCK signal. A toggle output is performed each time the operation is performed. With this output, the exclusive OR of both output signals is obtained by the EXOR circuit 244 through the delay circuits 242 and 243, so that a pulse signal is output after the delay time of the delay circuit 242 has elapsed. The mask by the delay time will be described later.

The output of the EXOR circuit 244 is input to the AND circuit 250 together with the CG signal (normally high level), and the next pulse signal PB fetch permission signal SSQRS
Output as T. The CG signal is a pulse signal P
This is set when only one B is measured, in which case the CG signal is fixed at a low level. FIG. 3 shows a detailed configuration of the input signal switching circuit 100. 300, 31
0 is a multiplexer circuit, and the main sequencer 19
0, the input pulse signal P
One of each of A and STDPA and the input pulse signal PB and STDPB is selected.

The selected signal is used as a clock for the D-type flip-flops 320 and 330, and PACK and PBCK are set to high level at the rise of the selected signal. That is, the D-type flip-flops 320 and 330 are rising edge detection circuits. Although the D-type flip-flops 320 and 330 are reset by the SIGRST signal from the main sequencer 190, the D-type flip-flops 330 and 330 are reset.
Is a SIGRST signal or PB measurement sequencer 18
It is reset by the SSQRST signal from 0. Therefore, during the PB measurement, the pulse signal PB
The D-type flip-flop 330 is not reset until the SSQRST signal, which is the capture permission signal, goes high, so that even if the next pulse signal PB is input during that time, that signal is ignored.

In FIG. 1, data indicating the measurement time difference output from the pulse phase difference encoding circuit 110 is as follows:
Decoders 220 to 222 in PB measurement sequencer 180
Are sequentially written to the buffer registers 120 to 122 in accordance with the output state of. After the PB measurement is completed, the transfer gates 123 to 126 are sequentially opened by the write timing output from the main sequencer 190,
Data in the buffer registers 120 to 122 is written to the registers 140 to 143.

The pulse signals STDPA and STDPB
After the reference signal measurement by, the data indicating the time difference is
The data is written to the register 144 through the bypass gate 123. Further, the data indicating the measurement time difference taken into the registers 140 to 143 is input as a dividend to the division circuit 150 via the transfer gates 145 to 148 at the read timing from the main sequencer 190. The data indicating the reference time difference written in the register 144 is input to the division circuit 150 as a divisor. The division circuit 150 divides the data indicating each measurement time difference by the data indicating the reference time difference to obtain a relative ratio, and outputs the result as corrected measurement time difference data.

The corrected measurement time difference data is written from the main sequencer 190 to the data registers 160 to 163 at the write timing, and is output as measurement data via the transfer gates 164 to 167. The operation of the above configuration will be described according to the processing flow of the main sequencer 190 shown in FIG. In addition, the timing chart of each part signal is as shown in FIG.
The numbers 1 to 13 of the main sequencer in the figure correspond to the processing flow numbers in FIG.

First, in processing procedure 1, the main sequencer 1
90, a SIGRST signal is output to the PB measurement sequencer 180 and the input signal switching circuit 100 to reset each of them, and SIMPPX is set to a high level to set the multiplexer 300 of the input signal switching circuit 100 to
310 sets the pulse signals PA and PB to the selected state.
The SQ0 signal is set to a low level to wait for the pulse signal PB.

When the pulse signal PA is input in the processing procedure 2, the PACK signal of the D-type flip-flop 320 becomes high level, and the pulse phase difference encoding circuit 110 and the PB measurement sequencer 180 operate. Thereafter, when the pulse signal PB is input, the D-type flip-flop 33
The PBCK signal of 0 becomes high level, and the pulse phase difference encoding circuit 110 outputs data DTBP indicating the time difference between the pulse signals PA and PB.

The permission to input the next pulse signal PB is realized by the circuits 230 to 250 in the PB measurement sequencer 180. Since the circuits 230 to 232 output a low level at the first pulse signal PB, the D-type flip-flop 2
The coincidence circuit 241 is a toggle output whose output is inverted every time the PACK signal is input. And the delay circuit 24
The outputs of 2, 243 are input to the EXOR circuit 244.

Here, the delay circuit 242 generates the delay time tw shown in FIG.
The delay time tr is generated by the two outputs of the third and third outputs. If the CG signal is at the high level, during the delay time tr,
The SSQRST signal becomes high level. The time T (mask time) obtained by adding the delay times tw and tr is a time T1 until the data latched in the pulse phase difference encoding circuit 110 becomes stable, and the data latched by the pulse phase difference encoding circuit 110 is buffered. The time T2 until reaching the registers 120 to 122, the D-type flip-flop 21 through the decoder 200 of the PB measurement sequencer 180
The time is set to be equal to or longer than the time T3 until reaching 0 to 212. Therefore, T is defined as the critical path (T1, T2,
By setting the mask time to be equal to or longer than the delay time of (the maximum time of T3), stable data is always latched even when the next pulse signal PB is input.

In FIG. 5, since the third pulse signal PB is within the mask time, the third pulse signal is ignored, the fourth pulse signal is internally recognized as the third signal, and the fifth signal is internally the fourth signal. Be recognized. These are all determined at the timing of the rising edge of the pulse signal PB. Further, even if the widths of the pulse signals PB are not equal, the PBCK signal is stably output as a high-level signal by the D-type flip-flop 330. Note that the third and fourth pulse signals PB are combined into one pulse, and the circuits 230 to 250 for generating the mask time and the D-type flip-flop 230 process the pulse waveform according to the mask time. It constitutes a pulse waveform processing means.

Here, by setting the setting of the mask time T equal to the delay time of the critical path, a plurality of P
The measurement between A and PB can be used to the maximum. That is, when the second pulse signal PB is input, the data latched when the first pulse signal PB is input is input to the buffer register 120, and when the third pulse signal PB is input, the data latched when the second pulse signal PB is input. Is input to the buffer register 121, and the pulse signal P
At the time of input of the fourth B4, the data latched at the time of input of the third pulse signal PB is input to the buffer register 122.

Since the output of the measuring circuit 230 goes high at the fourth pulse signal PB, the D-type flip-flop 240 does not perform a toggle output, and the SSQRST signal remains low. Therefore, the input of the next pulse signal PB is prohibited, and the fifth and subsequent pulse signals PB are ignored. Also, even if only two pulse signals PB are input, the pulse phase difference encoding circuit 1
When the overflow signal OV is output from the counter 10, that is, when the measurement range is exceeded, the output of the measurement time end detection circuit 232 becomes high level, and the pulse signal P
The measurement of B is completed by two shots.

When the measurement of the pulse signal PB is completed, the data of the fourth pulse signal PB is stored in the register 14 in the processing procedure 3.
Write to 3. In the processing procedures 4 to 6, the data of the third pulse signal PB is transferred from the buffer register 122 to the register 142, the data of the second pulse signal PB is transferred from the buffer register 121 to the register 141, and the pulse signal PB is output.
The B1 data is written from the buffer register 124 to the register 140.

In the processing procedure 7, the SIGRST signal is output to output the PB measurement sequencer 180 and the input signal switching circuit 10.
0 is reset to take in the next pulse.
Further, the SIGMPX signal is set to the low level, the multiplexers 300 and 310 of the input signal switching circuit 100 are set to the pulse signal STDPA and STDPB selection states, and
The Q0 signal is set to the high level to set the reference signal measurement state.
The high level signal of MSQ0 causes the measurement circuit 231
Output becomes low level and SS is measured during this reference signal measurement.
The QRST signal remains at low level.

In processing procedure 8, a START signal is output to reference signal generating circuit 170. Reference signal generation circuit 170
Receive pulse signals STDPA and STDP having phases different from each other by reference signal time ts in FIG.
B is output. These pulse signals STDPA, STD
The PB is input to the pulse phase difference encoding circuit 110 via the input signal switching circuit 100, and the reference signal time is measured.

In processing procedure 9, the buffer gate 123 is opened, and data DTBP indicating the time difference between the reference signals of the pulse phase difference encoding circuit 110 is written in the register 144. In processing procedure 10, the transfer gate 145 is opened, the data of the first pulse signal PB is input to the dividend of the division circuit 150, and the data indicating the time difference of the reference signal is input to the divisor. The result of the division is stored in register 160.
Write to Similarly, in the processing procedures 11 to 13, the data of the second, third and fourth pulse signals of the PB are input to the dividend of the division circuit 150, and the division results are written to the registers 161 to 163.

Thereafter, the procedure returns to the processing procedure 1, and the above-mentioned processing is repeated. The data written in the registers 160 to 163 can be taken out as measurement data by opening the data gates 164 to 167.
As described above, the pulse phase difference encoding circuit 110 is controlled by the time-division input by the multiplexer circuits 300 and 310.
Pulse signal PA-PB measurement and STDPA-STD
Since these circuits can be used commonly for PB-to-PB measurement, the circuit area can be reduced when these circuits are configured as an IC on a single chip.

In the above embodiment, the pulse signal PB is set to 4
Although the limit is shown before the start, the number may be increased. As a result, when applied to a laser radar system or the like, high performance can be achieved by measuring multiple shots. (Second Embodiment) Next, a second embodiment of the present invention will be described.

FIG. 6 shows the configuration of the second embodiment. As can be seen from FIG. 6, the second embodiment has the same general configuration as the first embodiment shown in FIG. 1, but differs in that a time measuring device is a peripheral module 197 of a microcomputer (CPU) 198. ing. That is, since the CPU normally has a division instruction, the CPU 198 performs the calculation of the relative ratio, and the division circuit 150 and the like in FIG. 1 are omitted. Of course, when the CPU load is large and the system is hindered, there is no problem even if the division circuit 150 as shown in FIG. 1 is inserted.

In the second embodiment, a transfer gate 149 is added to the output of the register 144 in which the reference time measurement data is written. Further, a control register 195 and a status register 196 are provided. In the control gate 195, TE is an interrupt enable flag, TP is a measurement range setting flag, CG is a selection flag for measuring a plurality of measurements or only one measurement, RG is a reference time difference signal generation switching flag,
TS indicates a measurement start flag. In the status register 196, TE indicates an end signal, OV indicates a signal indicating that the measurement range has been exceeded, and T4 to T1 indicate signals indicating how many pulse signals PB have been measured.

The CPU 198 controls the transfer gate 14
5 to 149, the control register 195, and the status register 196 can perform read access, and can exchange signals through a main bus including an address bus and a data bus. FIG. 7 shows a processing flow of the main sequencer 190 in the second embodiment.

The operation of the above configuration will be described. C
Various data are set in the control register 195 from the PU 198. The main sequencer 190 operates according to the state of each flag set in the control register 195. And control register 1
When the measurement start flag TS is set to “1” at 95,
The measurement by the main sequencer 190 and the like is started. This measurement processing is the same as that shown in FIG. 1 as shown in processing procedures 2 to 9 in FIG.

However, when one pulse signal PB is measured, T1 becomes "1", and when two pulses are measured, T2 becomes "1".
In the following, T3 and T4 also become "1" when the third and fourth shots are measured.If the measurement range is exceeded before four shots are measured, the OV flag becomes "1". Therefore, this T
By looking at 4 to T1 and the OV flag, it is possible to know how many times the measurement has been made.

When the measurement of the reference signal is completed, the TF becomes "".
When the TF is "1" and the interrupt enable flag of the TE is set to "1", the interrupt signal I
RQ is issued to CPU 198. In response to this, the CPU 198 performs an interruption process, for example, a process of inputting each time difference data via the transfer gates 145 to 149 and obtaining measurement data by a division process thereof.

In the above-described embodiment, the time measuring device 197 can be configured as a circuit integrated on a single chip, including a CPU, a ROM, a RAM, and peripheral circuits (such as a timer and a DAC). . (Third Embodiment) Next, a third embodiment of the present invention will be described.

When the present invention is applied to a system for automatically traveling while maintaining a certain distance while measuring the inter-vehicle distance with a laser radar or the like, environmental conditions such as operating temperature, fluctuations in power supply voltage and the like (± several nsec. Measurement time error),
There is a possibility that the distance to the target object is measured or not. For example, when the pulse signal PB is detected immediately after the SSQRST signal defining the mask time changes from the high level to the low level, distance detection for the pulse signal PB is performed. If the pulse signal PB is generated when the SSQRST signal is at a high level due to environmental conditions such as temperature or fluctuations in the power supply voltage, the pulse signal PB is not detected. That is, there is a possibility that the pulse signal PB that occurs before or after the timing when the SSQRST signal changes from the high level to the low level cannot be detected periodically.

In this embodiment, in order to solve such a problem, the SSQRST signal is provided not with one but with a hysteresis on the time axis so that two times can be selected.
In such a case, the pulse width of the SSQRST signal is shortened so that the next pulse signal PB can be reliably detected. Therefore, as shown in FIG. 10, a delay circuit 245 and an exclusive OR circuit 246 are provided in parallel with the delay circuit 243 and the exclusive OR circuit 244, and different delay times (the delay circuit 243 and the exclusive OR circuit 244) are provided. A pulse signal having a delay time shorter than 244 is generated, and one of the pulse signals is selected by the multiplexer circuit 260 to generate the SSQRST signal.

The selection signal CLRSEL is used to make the selection in the multiplexer circuit 260. This selection signal CLRSEL is supplied to the SSQRST control circuit 295.
Created by The SSQRST control circuit 295 stores information indicating the generation state of the pulse signal PB at the time of the current sampling, and generates a selection signal CLRSEL for each pulse signal PB based on the stored information at the next sampling. Like that. This is in view of the fact that the pulse signal PB is likely to be generated at the same timing in each sampling, and in the same situation as that of the pulse signal PB during the current sampling, An SSQRST signal is generated for each pulse signal PB generated at the time of sampling.

First, a description will be given of the point of storing information indicating the generation state of the pulse signal PB at the time of the above-described sampling. In order to grasp the generation state of the pulse signal PB at the time of this sampling, in this embodiment, the SSQ
The RST1, SSQRST2, and SSQRST3 signals are used. This corresponds to the previously generated pulse signal PB
Is used to check the generation timing of the next pulse signal PB.

Therefore, the SSQRST control circuit 295
Are the SSQRST1 signal, SSQRST2 signal, SSQ
It has a circuit for generating the RST3 signal. In FIG. 12, a toggle circuit is constituted by a D-type flip-flop 510 and a knot gate 511. After being reset by a SIGRST signal, an inverted output is performed every time a PBCK1 signal is generated.
Then, the SSQRST1 signal is created by the exclusive OR circuit 514. Similarly, the D-type flip-flop 52
PBCK in circuits from 0 to exclusive OR circuit 524
The SSQRST2 signal is generated based on the generation of the two signals, and the SSQRST2 signal is generated based on the generation of the PBCK3 signal in the circuits from the D-type flip-flop 530 to the exclusive OR circuit 534. PBCK1 signal, PB
The CK2 signal and the PBCK3 signal will be described later.

The delay circuits 512, 522, 532
Has the same delay time as the delay circuit 242 in FIG. 10, and the delay circuit 513 has the same delay time as the delay circuit 243 in FIG. The delay circuit 523 has a longer delay time than the delay circuit 243 in FIG.
Is set to have a longer delay time than the delay circuit 523. Therefore, the SSQRST1, SSQRST2, and SSQRST3 signals are the signals having the larger pulse widths in this order, that is, FIG.
(B), a signal having a pulse width as shown in the timing chart of FIG.

The SSQRST1 signal, SSQR
Pulse signal P using ST2 signal and SSQRST3 signal
The occurrence state of B is detected. FIG. 11 shows the configuration.
The configuration shown in FIG. 11 is different from the configuration shown in FIG.
Circuits 380 to 382, D-type flip-flop circuit 3
50 to 370 are added. As can be seen from this figure, D-type flip-flop circuits 350 to 370
Are the PBCK1 signal, PBCK, and the pulse signal PB generated after being reset by the SSQRST1, SSQRST2, and SSQRST3 signals, respectively.
Two signals and a PBCK3 signal are output. In this case, SSQ
Since the pulse widths of the RST1, SSQRST2, and SSQRST3 signals are different, the PBCK1 signal, the PBCK2 signal, and the PBCK3 signal depend on the time from the previously generated pulse signal PB to the next generated pulse signal PB.
The signal changes.

For example, as shown in FIG. 14A, the time from the generation of the first pulse signal PB to the generation of the second pulse signal PB is relatively short, and SSQRST
The second pulse signal P after one signal goes low
When B occurs, only the PBCK1 signal becomes high level, and the other PBCK2 signals and PBCK3 signals remain low level. When the second pulse signal PB is generated after the SSQRST2 signal becomes low level, the PBCK1 signal and the PBCK2 signal become high level, and the second pulse signal after the SSQRST3 signal becomes low level. When the pulse signal PB is generated, all of the signals PBCK1 to PBCK3 go high. Therefore, when the state of the PBCK1 signal to the PBCK3 signal when the second pulse signal PB is generated,
Information indicating the state of generation of the pulse signal PB at the time of the current sampling can be obtained.

The state of generation of the pulse signal PB at the time of the current sampling by the PBCK1 to PBCK3 signals is stored in the circuit shown in FIG. 12, and the above-described selection signal CLRSEL is created based on the stored information. . Among the above-mentioned SSQRST1, SSQRST2, and SSQRST3 signals, the SSQRST1 signal has the shortest pulse width, and therefore the PBCK1 signal changes to high level many times.
The control circuit 295 uses the PBCK1 signal to
The state of the BCK1 signal to the PBCK3 signal is stored.

In FIG. 12, every time the PBCK1 signal is generated, the number of occurrences is counted by the counter 500. This count value is decoded by the decoder 501. The decoding result is a write signal / measurement signal for writing and storing the PBCK1 signal to the PBCK3 signal when the next PBCK1 signal is generated. For example, PBC
When the first K1 signal is generated, the decoder 501 generates the next PBCK1 signal, that is, the second PBCK1 signal.
When a signal is generated, a write signal / measurement signal for writing and storing the PBCK1 signal to the PBCK3 signal is output.

The writing and storing of the PBCK1 to PBCK3 signals are performed by the SSQRST signal select generation circuit 502 shown in FIG. AND circuits 601 to 60
No. 3 enters a standby state in which the RS flip-flops 611 to 613 are set by the second write information. That is, as described above, after the first PBCK1 signal is generated, the second write information becomes high level. In this state, when the second PBCK1 signal is generated, the PBCK1 signal to PBCK3 signal at that time are set to R. -S flip-flops 611 to 613 are stored. For example, FIG.
In (a), when the second PBCK1 signal is generated, since both the PBCK2 signal and the PBCK3 signal are at the low level, the RS flip-flops 611 to 611-6 are output.
13 stores “1”, “0”, and “0”, respectively. This stored information is stored in the decoder and latch circuit 620 for selecting the SSQRST for the next PB measurement according to the second measurement signal.

Similarly, AND circuits 604 to 606
RS flip-flop 614 according to the first light information
６ 616 is set to the standby state. In FIG. 13, there are n stages of similar circuits, and AND circuits 607 to 609
According to the n-th write information, the RS flip-flop 61
A standby state is set in which 7 to 619 are set. Therefore, according to the second and subsequent PBCK1 signals, the PBCK1 signal to PBCK3 signal at that time are stored in the RS flip-flop corresponding to the number of occurrences, and are also stored in the decoder and latch circuit 620.

Accordingly, the decoder and latch circuit 620 has a PBCK signal corresponding to the generation timing of the PBCK1 signal.
1 signal to PBCK3 signal are sequentially stored.
The decoder and latch circuit 620 performs the current SSQRS based on the information stored at the previous measurement in the relationship shown in Table 1.
A selection signal CLRSEL for determining the T signal is output.

[0074]

[Table 1]

That is, the PBCK1 to PBCK3 signals stored for the i-th occurrence of the PBCK1 signal are:
As shown in FIG. 14A, at the time of “1”, “0”, “0”, the same signal as the SSQRST3 signal, that is, the output from the exclusive OR circuit 246 of FIG.
A multiplexer 2 outputs a selection signal CLRSEL as a T signal.
Output to 60. That is, since it is necessary to prevent detection of the pulse signal PB during such a mask period as described in the first embodiment, it is not surely detected at the next sampling. As described above, the mask time is extended.

The signals PBCK1 to PBCK3 are "1", "1", "1" as shown in FIG.
When the signal is "0", the selection signal CLRSEL is output as the same SSQRST3 signal as before.
As shown in FIG. 15, the PBCK3 signal is "1", "1".
At the time of “1”, “1”, the same signal as the SSQRST1 signal, that is, the output from the exclusive OR circuit 244 is set to SS
It outputs a selection signal CLRSEL as a QRST signal.
Therefore, in such a case, the pulse signal PB may have been generated immediately after the SSQRST signal has changed to the low level. Therefore, in order to surely detect the pulse signal PB in the next time, the SSQRST signal is used. Is shortened, that is, the mask time is shortened.

The SSQ controlled according to Table 1 above
The initial value of the RST signal is set so as to be the SSQRST3 signal. As described above, the provision of hysteresis as in the third embodiment has the effect of eliminating detection fluctuations due to power supply voltage fluctuations and the like. However, when performing a series of sampling measurements as in the above-described embodiment, the mask time is reduced. Has the effect that sampling uniformity can be achieved.

Note that the PB measurement end condition of this system is that the PBCK1 signal is used for the counter 500 to perform the measurement up to the nth time, or that the PB measurement sequencer 180
Either until the fourth shot or until the OV signal is generated. At that time, the END signal
The current PB measurement ends. In addition, this 3rd Example is
The first embodiment is modified as shown in FIGS. 10 and 11 (corresponding to FIGS. 2 and 3 in the first embodiment).
Other configurations are the same as those of the first embodiment.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a PB measurement sequencer 180 in FIG.

FIG. 3 is a circuit diagram showing a specific configuration of an input signal switching circuit 100 in FIG.

FIG. 4 is a diagram showing a processing flow of a main sequencer in FIG. 1;

FIG. 5 is a signal waveform diagram showing signal waveforms of respective units in FIG.

FIG. 6 is an overall configuration diagram showing a second embodiment of the present invention.

FIG. 7 is a diagram showing a processing flow of a main sequencer 180 in FIG. 6;

FIG. 8 is a circuit diagram showing a specific configuration of the pulse phase difference encoding circuit 110.

FIG. 9 is a configuration diagram illustrating a configuration of an A / D converter according to a conventional technique.

FIG. 10 shows a third embodiment of the present invention.
FIG. 9 is a circuit diagram in which a B measurement sequencer 180 is modified.

FIG. 11 is a circuit diagram obtained by modifying the input signal switching circuit 100 shown in FIG. 3 in the third embodiment of the present invention.

FIG. 12 is a circuit diagram showing a specific configuration of an SSQRST control circuit in FIG. 10;

13 is a circuit diagram showing a specific configuration of an SSQRST signal select generation circuit in FIG.

FIG. 14 is a timing chart for explaining the operation of the third embodiment.

FIG. 15 is a timing chart for explaining the operation of the third embodiment;

[Explanation of symbols]

 Reference Signs List 100 input signal switching circuit 110 pulse phase difference encoding circuit 150 division circuit 170 reference signal generation circuit 180 PB measurement sequencer 190 main sequencer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-11527 (JP, A) JP-A-60-253994 (JP, A) JP-A-3-220814 (JP, A) JP-A-5-205 308263 (JP, A) JP-A-3-125514 (JP, A) JP-A-3-33492 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) G04F 10/06 H03K 5 / 26

Claims (10)

(57) [Claims] 1. A first pulse signal is input to pass the first pulse signal through a plurality of delay elements, and a plurality of temporally different detection pulse signals are input after the input of the first pulse signal. The time difference between the first pulse signal and the plurality of detection pulse signals is encoded by the number of delay elements through which the first pulse signal has passed to obtain measurement time difference data. In the A / D converter, a phase difference between the first pulse signal and the subsequent detection pulse signal is input to a subsequent detection pulse signal input within a predetermined period from the input time point of the detection pulse signal. A time A / D converter, comprising a prohibition means for prohibiting an operation of encoding the time code. 2. An input means for inputting a pulse signal, and when the first pulse signal is input to the input means, the first pulse signal is passed through a plurality of delay elements, and the first pulse signal is supplied to the input means. When a plurality of temporally different detection pulse signals are inputted to the input means after the input of the first pulse signal, the first pulse signal is transmitted by the number of delay elements, and the first pulse signal is transmitted to the first pulse signal.
A time A / D converter that encodes the phase difference between the pulse signal and the plurality of detection pulse signals to obtain measurement time difference data, wherein a predetermined time from when the detection pulse signal is input to the input means A time A / D conversion device characterized in that a prohibition means for prohibiting the input operation of the input means with respect to a subsequent detection pulse signal is provided during the period of (1). 3. The method according to claim 2, wherein the prohibiting unit is configured to output the detection pulse signal based on a signal indicating that the detection pulse signal has been input to the input unit.
A circuit means for generating a signal corresponding to a predetermined mask time, wherein the input operation of the input means within the predetermined time period is inhibited by the signal from the circuit means. 3. The time A / D converter according to 2. 4. A generation timing detecting means for detecting a generation timing of the subsequent detection pulse signal generated following the detection pulse signal, and a generation timing of the subsequent detection pulse signal detected by the generation timing detection means The time A according to claim 2 or 3, further comprising a period changing means for changing the predetermined period for the next detection of the subsequent detection pulse signal based on the time A.
/ D converter. 5. Using two pulse signals for measuring a reference time, which have different phases by a reference time, encode a phase difference between the two pulse signals by the number of passing through the plurality of delay elements to obtain reference time difference data. The time A / D converter according to any one of claims 2 to 4, further comprising: a obtaining unit; and a correction unit configured to correct the measured time difference data with the reference time difference data. 6. The time A / D converter according to claim 5, further comprising a reference signal generating means for generating two pulse signals for the reference time measurement. 7. The input means includes means for selectively performing input of the first pulse signal and the subsequent plurality of detection pulse signals and input of the two pulse signals from the reference signal generation means. 7. The time A / according to claim 6, wherein the plurality of delay elements are used to perform the operation of obtaining the measured time difference data and the operation of obtaining the reference time difference data in a time division manner. D conversion device. 8. The time A / D according to claim 2, further comprising means for limiting the number of the plurality of detection pulse signals input to the input means.
Conversion device. 9. The time according to claim 2, further comprising a plurality of storage units for respectively storing a plurality of measurement time difference data obtained for the plurality of detection pulse signals. A / D converter. 10. A ring delay pulse generating means in which the plurality of delay elements are formed in a ring shape, a count means for counting the number of times the first pulse signal circulates in the ring-shaped plurality of delay elements, Position specifying means for specifying the passing position of the first pulse signal at the time when the detection pulse signal is input, wherein the measurement time difference data is obtained by the count value of the counting means and the specific position of the position specifying means. 3. The method according to claim 2, wherein
10. The time A / D converter according to any one of claims 9 to 9.