JPH05120182A - Interruption control method - Google Patents

Abstract

PURPOSE:To obtain an interruption control method to reduce the number of connection lines for interruption processing between a main control part and plural subordinate parts. CONSTITUTION:The main control part 200 is connected to the plural subordinate parts 230, 231,..., 236 with the signal line of a clock signal 206 with frame and an interruption request bus 205 which transmits an interruption request signal from each subordinate part to the main control part 200, and the main control part 200 transmits the clock signal with frame equipped with a frame signal to identify a frame at every prescribed number of clocks to all the subordinate parts, and data to designate the subordinate part from which the interruption request signal is outputted to a bus in time division is generated in common, and the subordinate part outputs an interruption request in sequence of generation to the bus, and the main control part discriminates a request origin based on the sequence. and performs the interruption processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor control system such as an exchange having a main control unit composed of a microprocessor and a plurality of subordinate units, wherein the subordinate unit controls the main control unit to execute its program processing. The present invention relates to an interrupt control method for recognizing and processing a request source when requesting a flow change.

[0002]

2. Description of the Related Art In recent years, various systems in which a plurality of subordinate units are connected to a main control unit such as an exchange are used, and the problem is to simplify means for controlling interrupt processing from each subordinate unit.

A conventional interrupt control method will be described below with reference to the drawings. FIG. 5 is a block diagram showing the configuration of a conventional system in which interrupt control is performed. In the figure, reference numeral 100 denotes a main control unit configured by a microprocessor or the like, 120, 130, ..., 190 denote slave units requesting an interrupt to the main control unit 100, 121,
Reference numerals 131, ..., 191 are interrupt request signal lines for requesting the main control unit 100 from the subordinate unit to change the flow of a program for controlling its operation.

.., 190 are interrupt request signal lines 121, 131, .., 191 respectively when it is desired to change the program flow of the main control unit 100 according to the internal states of the respective dependent parts. The change request is notified to the main control unit 100 via.

[0005]

In such a conventional interrupt control method, the main control unit individually inputs and determines the interrupt request signals from the respective slave units that are asynchronously generated, and performs the corresponding processing. Also, since the main control side has an interrupt input port for receiving an interrupt request signal for each subordinate unit, the number of connecting lines and the number of interrupt ports increase as the number of subordinate units increases. There was a problem that flexible expansion was hindered.

An object of the present invention is to solve the above problems, and an object thereof is to provide an interrupt control method in which the number of connecting lines and the number of input ports do not increase even if the number of dependent parts is increased.

[0007]

In order to achieve the above object, the present invention comprises a main control section and a plurality of subordinate sections which output an interrupt request signal to the main control section to request interrupt processing. In the system, a common clock signal line for transmitting a clock signal from the main control unit to all the subordinate units and a common interrupt request bus for transmitting an interrupt request signal from all the subordinate units to the main control unit are provided. ,
The main control unit sends the framed clock signal including a frame signal for identifying a frame for each predetermined number of clocks to all the subordinate units via the clock signal line, and the main control unit and each subordinate unit Generates at the clock timing data that designates the subordinate portions in a predetermined order in time division with reference to the frame timing of the framed clock signal, and the subordinate portion of the subordinate portions designated by the data is in that period. In this interrupt control method, an interrupt request signal is output to the interrupt request bus, and the main control unit determines the subordinate unit of the interrupt request source from the input timing of the interrupt request signal and performs interrupt processing.

[0008]

According to the present invention, in the above structure, the main control unit sends the framed clock signal to all the subordinate units, and the main control unit and all the subordinate units refer to the frame of the framed clock signal as a reference. Section generates data that specifies the order of outputting interrupt request signals to the bus in a time-sharing manner, the subordinate section outputs the interrupt request signal to the bus at the specified timing, and the main control section starts from the timing of the interrupt request signal. Determines the request source and executes interrupt processing.

[0009]

【Example】

(Embodiment 1) An interrupt control method according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a system using an interrupt control method according to an embodiment of the present invention. In the figure, reference numeral 200 is a main control unit including a microprocessor and the like, and 230, 231, ..., 236 are subordinate units. The main control unit 200 generates a main control unit processor 201 that controls the operation of the main control unit, a clock signal 206 with a frame that defines the output timing of the interrupt request signal of each subordinate unit, and a clock signal 207 that generates a timing signal 207. Circuit 202 and interrupt request bus 205
The output value of the timing signal 207 is latched by the interrupt request signal sent from the subordinate unit via the latch unit 203, and once latched, the latch unit 203 that holds the state until the activation signal 212 is input, and the latch unit 203 The latch output 208 latched by the unit 203 is used as the main control unit processor 201.
To the gate circuit unit 20 that outputs to the output via the data bus 209
4 and.

The subordinate unit 230 controls the operation of the subordinate unit,
Timing is detected by detecting a subordinate unit control unit 221 that outputs an interrupt request signal 227 when an interrupt is required to the main control unit 200 due to a situation under management, and a frame of the framed clock signal 206 output from the main control unit 200. A timing signal generation circuit 222 that outputs a signal 225;
A comparison circuit 223 that compares the timing signal 225 with a unique timing setting signal 226 given to each subordinate unit and generates an interrupt request control signal 228 that controls the timing at which the interrupt request signal 227 is output to the interrupt request bus 205. And the interrupt request signal 227 is controlled by the interrupt request control signal 228.
5 and an output gate circuit 224 which outputs the signal to the output terminal 5.

FIG. 2 is a block diagram showing the configuration of the clock signal generation circuit 202 in the main control unit 200. In the figure, a clock signal generation circuit 202 is a clock oscillator 300 that generates a clock signal serving as a reference clock between a main control unit and each subordinate unit and outputs a clock signal 304, and is updated at the fall of the clock signal 304. A counter 301 that outputs a timing signal 207, and a 3-input NAND gate 302 that generates a frame synchronization signal 305 for forming one frame of the framed clock signal 206 when the timing signals 207 are all at the H level. While the frame synchronization signal 305 is at the H level, the clock signal output 304 is transmitted, while during the L level, the transmission of the clock signal is stopped and that portion is used as a frame signal.
And a 2-input AND gate 303 for outputting 6. The timing signal 207 is the clock signal 304.
The data (3 bits data in the embodiment) that changes at the timing of (3) is given, and the numbers corresponding to the plurality of subordinate parts are given. The relationship between the clock signal 304, the timing signal 207, the frame synchronization signal 305, and the framed clock signal 206 is shown in the timing chart of FIG.

FIG. 3 is a block diagram showing the configuration of the timing signal generating circuit 222 in the subordinate unit 230. In the figure,
The timing signal generation circuit 222 does not trigger an output pulse for each frame of the framed clock signal 206, that is, for each timing when the H level of the framed clock signal 206 is missing, and outputs an output pulse that becomes an L level only at that timing. Generate and frame sync signal 402
Output as a monostable multivibrator 40
1 and a counter 4 that outputs and updates the output at the falling edge of the framed clock signal 206, and generates and outputs a timing signal 225 that is reset asynchronously with the clock input 206 when the frame synchronization signal 402 goes to L level.
00 and. The frame synchronization signal 402,
The relationship between the timing signal 225 and the timing signal 225 is shown in the timing chart of FIG.

With the above configuration, the counter 301 in the main control unit 200 and the counter 400 in the subordinate unit 230 operate synchronously, and the timing signal 207 and the timing signal 225.
Have the same timing value. In addition, another subordinate unit 23
1, ..., 236 have the same configuration as the subordinate portion 230.

The operation of the above arrangement will be described below. In each subordinate unit, a unique number is given to each subordinate unit in advance, and the timing setting signal 226 corresponding to the number is compared with the timing signal 225 by the comparison circuit 223, and the time when all the signals match is automatically detected. As the timing of outputting the interrupt request signal 227 of the subordinate unit, the interrupt request control signal 228 is set to the valid state, and the interrupt request control signal 228 is set to the invalid state at other times. For example, in the subordinate unit 230 of this embodiment, the timing setting signal 226 is set to "HLL (count value is 1)".
, And the interrupt request control signal 228 becomes valid at the time when the timing signal becomes “HLL”.

The output gate circuit 224 is formed of a tri-state gate, and the interrupt request control signal 228 from the comparison circuit 223 is in a through state when it is in a valid state, and the subordinate control unit 221 outputs the interrupt request signal 227 to the interrupt request bus 205. To be done. Further, when the interrupt request signal 228 is in the invalid state, it is in a bi-impedance output state, and the interrupt request signal 227 is not output to the interrupt request bus 205. In this way the counter 40
Depending on the state of the timing signal output by 0, 50 in FIG.
As shown in 1, the time at which the interrupt request signal is output is sequentially given to each subordinate unit. Output gate circuit 2 of each subordinate unit
The output of 24 is connected to the interrupt request bus 205, and the interrupt request signal 227 output by each subordinate control unit is output.
Is output to the interrupt request bus 205 only at the time given to each subordinate unit.

The interrupt request signal 227 output by each subordinate unit at the interrupt request signal output timing of its own subordinate unit receives the interrupt input of the main control unit processor 201 in the main control unit 200 via the interrupt request bus 205 and the latch unit 203. Is input as a latch enable signal of.
Timing signal 2 latched by the latch unit 203
It is assumed that the value of the data 07 is held until the activation signal 212 is output from the main control processor 201 to the latch unit 203 even if the next latch enable signal is input. When the interrupt request signal is output via the interrupt request bus 205, the interrupt request signal is input as the latch enable signal of the latch unit 203, so that the timing signal 207 output from the counter 301 is latched in the latch unit 203. To be done. The latch output 208 provides data equal to the unique number of the interrupt request source. The latch output 208 is connected to the data bus 209 of the main control processor 201 via the gate circuit section 204 constituted by a tri-state gate, and the main control processor 201 controls the selection signal 210 and the read signal 211, The interrupt request source can be confirmed from the output data of the gate circuit unit 204. When the activation signal 212 is output from the main controller processor 201, the latch unit 203 is again ready to latch new data.

Here, when the accuracy of the monostable multivibrator 401 is low, it is not possible to determine the timing when the output pulse becomes the L level, and therefore the counter 400 is reset (the timing signals 225 are all at the L level). Since the timing cannot be fixed, counter 400 and counter 301 are all L
There is a possibility that there will be a time lag in the timing of reaching the level, which may cause a malfunction. In order to avoid this, the "***" portion 501 shown in FIG. 4 is provided as a timing adjustment unit so that the interrupt request signal output of all the subordinate units becomes ineffective. Therefore, if a sufficiently stable monostable multivibrator is used, the timing adjustment unit can be eliminated. In this embodiment, the monostable multivibrator 40 is provided in order to secure a time width in which the subordinate unit 236 can output the interrupt request signal to the interrupt request bus at the timing when all the outputs of the counter 400 are at the H level.
The output pulse width of 1 is the clock signal 206 with frame
Is set to be 1 cycle or more and less than 1.5 cycle,
The clock of the clock signal with the frame is 0.
The time width of 5 cycles is sufficient for each subordinate unit to issue an interrupt request signal to the interrupt request bus 205.

As described above, according to the interrupt control method of the embodiment of the present invention, the main control unit generates a clock signal with a frame and transmits it to all the subordinate units via one clock signal line to perform the main control. The sub-unit and each sub-unit control unit commonly create data for designating the sub-unit that outputs the interrupt request signal from the clock signal with the frame in a time-sharing manner, and the sub-units generate one interrupt request signal at the designated timing. Only one clock signal line and one interrupt request bus are output by using the interrupt control method that outputs to the interrupt request bus and the main control unit recognizes the request source from the timing of the interrupt request signal and performs interrupt processing. The interrupt request signal can be transmitted to the main control unit without collision, and the subordinate unit can be easily added.

[0020]

As is apparent from the above embodiments, the present invention provides a system comprising a main control unit and a plurality of subordinate units for outputting interrupt request signals to the main control unit to request interrupt processing. A common clock signal line for transmitting a clock signal from the main control unit to all the subordinate units, and a common interrupt request bus for transmitting an interrupt request signal from all the subordinate units to the main control unit are provided. The control unit sends out the framed clock signal including a frame signal for identifying a frame for each predetermined number of clocks to all the subordinate units via the clock signal line, and the main control unit and each subordinate unit includes the Data for designating the dependent portion in time division in a predetermined order based on the frame timing of the framed clock signal is generated at the clock timing, and The subordinate unit designated by the data outputs an interrupt request signal to the interrupt request bus during the period, and the main control unit determines the subordinate unit of the interrupt request source from the input timing of the interrupt request signal and performs interrupt processing. With the above-described interrupt control method, the signal line relating to the interrupt request is only one interrupt request bus and one clock signal line regardless of the number of subordinate parts, and the connection between the main control part and each subordinate part is established. Since the number of lines can be reduced, a large number of subordinate units having the same level of interrupt request right can be easily connected, which is effective, for example, in an interrupt control method of a switching system in which subordinate units are frequently added.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a system using an interrupt control method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a circuit for generating a framed clock signal in a system using the interrupt control method according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a circuit that generates a timing signal for time-divisionally designating a dependent portion in a system using the interrupt control method according to the embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the interrupt control method according to the embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a system using a conventional interrupt control method.

[Explanation of symbols]

 200 Main control unit 205 Interrupt request bus 206 Clock with frame 230, 231, ..., 236 Subordinate unit

Claims (1)

[Claims] 1. A system comprising a main control unit and a plurality of subordinate units for outputting an interrupt request signal to the main control unit to request interrupt processing, wherein a clock signal is supplied from the main control unit to all the subordinate units. A common clock signal line for transmitting to the main control unit and a common clock signal line for transmitting an interrupt request signal from all the subordinate units to the main control unit.
The main control unit sends the framed clock signal including a frame signal for identifying a frame for each predetermined number of clocks to all the subordinate units via the clock signal line, and the main control unit and each subordinate unit Generates at the clock timing data that designates the subordinate portions in a predetermined order in time division with reference to the frame timing of the framed clock signal, and the subordinate portion of the subordinate portions designated by the data is in that period. An interrupt control method in which an interrupt request signal is output to the interrupt request bus, and the main control unit determines the dependent unit of the interrupt request source from the input timing of the interrupt request signal and performs interrupt processing.