JP2002041492A - Multiprocessor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiprocessor device which solves the problem of count synchronization, without making the conventional convenient configuration complicated, as much as possible. SOLUTION: N pieces of processors 1 (1-1 to 1-n) each have two interrupt terminals INT0 and INT1. A data clock DATACLK is branched by a demultiplexer 3, and each processor alternately receives an interrupt from the INT0 and INT1 in matching with the input timing of data. The same program, where processing to an interrupt at an INT0 level and processing to an interrupt at an INT1 level are described respectively, is written in each processor, and each processor selects processing according to the level of an interrupt generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor device in which a plurality of processors are arranged and a process for input data is performed in synchronization.

[0002]

2. Description of the Related Art In order to process a large amount of data in real time or to perform complicated calculations repeatedly at a high speed, a method of distributing processing by disposing a plurality of processors is widely used. FIG. 9 shows a configuration example of a data processing device having a plurality of processors. The data to be processed entering each processor may be common to each other, or may be different from each other. In any case, as a whole system,
Processes and outputs signals that come repeatedly in real time. FIG. 1B shows a configuration of an input portion of each processor. The data to be processed is taken into the processor from the BUS / PORT. A data clock signal indicating the arrival timing of the data to be processed is input to INT0 as an interrupt signal. Generally in such cases,
All processes of each processor are described by the same program,
It is not affected by the number of parallel processors and achieves flexible design and shortens development time.

[0003] In a distributed processing system, in the case of a loosely coupled processing device in which data exchange between processors is not required, it is not necessary to exchange information and control signals between processors. do not have. Even in this case, if the data input timings are synchronized, the processing of the processors can be synchronized with each other.

As described above, in the case of a loosely-coupled processing device, hardware or software for real-time synchronization between processors is not prepared, and in all cases, only the same timing of input signals is synchronized (processed). ).

[0005]

In such a processing apparatus, consider a case where a program for thinning out input data and performing a special calculation only once every three times is executed by all processors. In such a case, each processor has a counter by software, and counts up this counter for each process (every time data is input or every time an interrupt occurs) to recognize the "third time". This counter allows each processor to accurately know the repetition cycle of every three times, but whether the "third" processing timing is the "third" processing timing for other processors as well. Is unknown.

That is, when the power supplies of all the processors are turned on at the same time (started at the same time), the data input is accepted after executing the initial setting operation, that is, the interruption by the data clock is permitted. After that, there is a slight time difference (skew) between the processors until the interrupt is permitted.

[0007] This skew may cause a deviation in the count value of the counter in each processor. The interrupt permission timing and the mechanism that causes the count deviation will be described with reference to FIG. For example, when the power is turned on, each processor comes to a time to finish the initialization and release the interrupt. It is often the case that this timing slightly shifts (skew) between processors (due to the timing of power-on of the processor, the timing queue for reset release, or the timing shift due to a slight difference in description of software processing). As shown in the figure, when the input timing of the data clock, that is, the interruption occurs during the time width of the skew, some processors accept the interruption and some processors do not. In the figure, the processor i has accepted the interrupt, and the processor j has not accepted the interrupt. Therefore, these processors have a total count of subsequent interrupts of 1
It will continue to shift. Note that the deviation of the count value due to the skew is always 1 and never more than 2.

When there is such a deviation of the count value,
When processing such as another calculation is required only once every three times based on this count value, the timing of the "third time" varies among processors, and the data processing as a whole is incomplete. It becomes something.

Alternatively, the following case can be considered.
It is said that only a specific processor ignores interrupts by executing a special processing program, it is necessary to restart for some reason, or a processor that is in the middle of operation goes down, undergoes maintenance, and returns. Such is the case. In such a case, the counts of the occurrence of interrupts of the respective processors are greatly different.

[0010] In the loosely-coupled processing apparatus having the above-described simple configuration,
Since the data input count cannot be exchanged with another processor in real time, the processing count cannot be synchronized. Note that the synchronization of the processing count means that each processor performs the “m-th” processing in the same processing cycle, for example, when one processing is required every m times.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multiprocessor which has solved the problem of count synchronization without complicating a simple conventional configuration as much as possible.

[0012]

According to the present invention, there are provided a plurality of processors for simultaneously executing processing in response to an input of a notification signal for notifying data processing, and switching the notification signal to a plurality of types to simultaneously input the signals to each processor. Signal switching means;
And each processor switches the processing in accordance with the type of the input notification signal. In the present invention, the notification signal is, for example, a data clock or an enable signal for capturing data. In the case of a data clock, this may be input to each processor as an interrupt signal. In order to generate a plurality of types of notification signals using the interrupt signal, for example, a data clock is divided into a plurality of pieces and input to each processor from interrupt terminals of different levels. Each processor selects a process according to the generated interrupt level. As a result, even if the count value of the interrupt clock is shifted, it is possible to synchronize the processing of each processor at the interrupt level without relying on this.

According to the present invention, there are provided a plurality of processors for counting up a counter in response to an input of a notification signal for notifying data processing and executing processing on data to be processed, and switching the notification signal to a plurality of types to each processor. Signal processors for simultaneously inputting, wherein each processor corrects the count value of the counter according to the type of the notification signal input first after startup, and switches the processing according to the count value of the counter. Features. In the present invention, for example, a data clock or the like is used as the notification signal. In order to generate a plurality of types of notification signals using interrupt signals, data clocks are distributed to a plurality of types and input to each processor from interrupt terminals of different levels. Each processor:
The count value is corrected so that the notification signal input first, that is, the interrupt level generated first becomes the same. As a result, the count values can be matched between the processors, and the processes of the processors can be synchronized based on the count values.

According to the present invention, there are provided a plurality of processors for counting up a counter in response to an input of a notification signal for notifying data processing and executing a process for data to be processed, and an initialization of each processor after startup is completed. Gate means for simultaneously permitting each processor to input the notification signal after a sufficient time has elapsed, wherein each processor switches processing in accordance with the count value of the counter. In the present invention, for example, a data clock or the like is used as the notification signal. An initial setting operation is required in order to be able to execute processing by inputting data after the processor is started. However, the time required for the initial setting operation differs slightly for each processor (skew), which causes The count value is shifted. Therefore, the present invention prevents the notification signal (data clock) from being supplied to any of the processors until all of the processors can input data and execute processing, and after all of the processors can perform processing, At the same time, a notification signal is supplied to all processors. As a result, the count values can be matched between the processors, and the processes of the processors can be synchronized based on the count values.

According to the present invention, there are provided a plurality of processors which execute processing on data to be processed in synchronization with each other, and synthesizing means for adding information on the number of data inputs to the data to be processed by each processor and then inputting the information to each processor. Each processor switches the processing in accordance with information on the number of data inputs added to the input processing target data. According to the present invention, information relating to the number of times of data input is added to the data to be processed and input to each processor. When data to be processed is input, each processor refers to information on the number of times of data input added to the data, and selects a process in accordance with the information. Since the same information is added to data input to each processor at the same time, each processor can execute the same cycle of processing on data input at the same time and synchronize the processing of each processor.

According to the present invention, for example, reflected echo signals input from a plurality of ultrasonic transducers are processed in parallel,
The present invention can be applied to a receiving circuit of a sonar for forming an ultrasonic beam. In this case, the plurality of processors are all parallel processing processors that execute the same processing, but in the present invention, the arrangement of the processors is not limited to parallel.

[0017]

FIG. 1 is a block diagram of a parallel processing apparatus according to a first embodiment of the present invention. The parallel processing device 5 has n processors 1 (1-1 to 1-n),
Each processor 1 has two interrupt terminals INT0, INT
One. From outside, n data to be processed and a data clock DATACLK synchronized with the input timing of these data are input. DATAC
LK is a demultiplexer which is a circuit for distributing signals.
Is input to The demultiplexer 3 has two output terminals O
UT0 and OUT1. One output terminal OUT
0 is connected to the INT0 terminal of each of the processors 1-1 to 1-n, and the other output terminal OUT1 is connected to each of the processors 1-1 to 1-n.
1-n is connected to the INT1 terminal. The demultiplexer 3 outputs DATACLK input at a predetermined interval to OUT
0 and OUT1 are alternately output. Therefore, the processors 1-1 to 1-n alternately generate INT0 level and INT1 level interrupts in accordance with the data input timing.

Although not shown, each of the processors 1-1 to 1-1
-n has a data input terminal and a data output terminal, and n data to be processed are individually input to the data input terminal.

The same programs describing the processing for the INT0 level interrupt and the processing for the INT1 level interrupt are written in each of the processors 1-1 to 1-n. If necessary, information on which interrupt has been entered is stored and managed by the program.

FIG. 2 shows the algorithm of the above program. When an INT0 level interrupt occurs, a flag 0 is set (s1), and a common interrupt process is executed (s3). On the other hand, if an INT1 level interrupt has occurred, the flag 1 is set (s2), and a common interrupt process is executed (s3). If different processing is to be performed alternately in s3, the processing may be branched by referring to the flag. When performing processing on every other data by thinning out the input data, a program such as “perform data processing at the timing of INT0” may be written. In this way, even if there is a discrepancy in the total number of interrupts between the processors, a common synchronization identification can be made between INT0 and INT1, and synchronization between two types of processing performed alternately is guaranteed between the processors.

FIG. 3 is a block diagram of a parallel processing apparatus according to a second embodiment of the present invention. This embodiment is different from the first embodiment in that each processor 1 (1-1 to 1)
-n) three interrupt terminals INT0, INT1, and INT
2 in that the data clock DATACLK is sequentially input. That is, the demultiplexer 3 has three output terminals OUT0, OUT1, and OUT2, and the output terminals OUT0, OUT
1, OUT2 are connected to interrupt terminals INT0, INT1, INT2 of the processors 1-1 to 1-n.

In this configuration, each of the processors 1-1 to 1-n has I
The same program in which the processing for the NT0 level, INT1 level, and INT2 level interrupts is described is written, and information on which interrupt has been entered is stored and managed by the program as needed. In the program, when an INT0 level interrupt occurs, a flag 0 is set, and then a common interrupt process is executed. When an INT1 level interrupt occurs, a common interrupt process is executed after flag 1 is set. When an INT2 level interrupt occurs, the common interrupt process is executed after setting the flag 2. In this case, the input data is decimated to 1 out of 3 times.
In the case of performing the round processing, for example, a program “Data processing is performed at the timing of INT0” may be written.

As described above, if interrupts are generated in a number of levels corresponding to the number of processes in which a plurality of types of processes make a round, a mode in which only a specific processor ignores interrupts on the way may be used. By starting, even if the count values greatly differ between the processors, the count synchronization of the processing can always be maintained.

FIG. 4 is a block diagram of a parallel processing apparatus according to a third embodiment of the present invention. The parallel processing unit 15 is n
Processors 11 (11-1 to 11-n),
Each processor 11 has an interrupt terminal INT0. From outside, n data to be processed and a data clock DATACLK synchronized with the input timing of these data are input. DATACLK is input to the interrupt terminal INT0 of each of the processors 11-1 to 11-n via the gate 13. Although not shown, each of the processors 11-1 to 11-n has a data input terminal and a data output terminal, and the n data to be processed are individually input to the data input terminal.

The same program is written in each of the processors 11-1 to 11-n. In the program, the gate 13 is closed during the execution of the initial setting, and the gate is opened after a sufficient time has elapsed after the completion of the initial setting. Here, the time after the lapse of sufficient time is a time period in which the initialization of all processors is completed even if there is a time difference in the initialization of each processor. The output of the processor 11-1 is sent to the control terminal ena of the gate 13.
By supplying the signal as a ble signal, the first interrupt clock input to the system is accepted by all processors, and there is no discrepancy in the total counts of the processors 11-1 to 11-n. The processor connected to the gate 13 is not limited to 11-1.

FIG. 5 is a flowchart showing the operation at the time of starting the processor. When the power is turned on, an initial setting is executed (s11). During this initial setting period, en
data signal DA
TACLK is not input to the processor. When the initialization is completed, the interrupt for INT0 is released (s1
2) After a sufficient time has passed, the gate 13
The enable signal is output, the gate is opened, and the data clock DATACLK is input to all processors (s13).

FIG. 6 is a block diagram of a parallel processing apparatus according to a fourth embodiment of the present invention. This parallel processing device 5
In the parallel processing device of the embodiment of FIG. 1, a low-speed serial interface SIO is provided for each of n processors 1 (1-1 to 1-n) and connected by a serial line 6. By "communicating" via the serial line 6 whether there is a clock count shift, each processor corrects the shift of the total count value of the interrupt clock by its own program, and the total count value is calculated by all processors. Is the method of matching. That is, in the normal operation, the cause of the deviation of the total count value of each processor is due to the skew, and the discrepancy is at most 1 and therefore, whether the first interrupt was the INT0 level interrupt or the INT1 level interrupt ( The first and second interrupt levels are exchanged, and based on this, the unmatched processors increase or decrease the count by one, so that the total count values of all processors can be matched. In this way, the process is repeated not only once in two times but also in a count number higher than that (for example, 3
Synchronization is possible even with processing specifications (such as once-at-a-time thinning).

FIG. 7 is a flowchart of the count value adjusting process of the processor. When the power is turned on, an initial setting is executed (s21). When initial setting is completed, INT
0, the interrupt for INT1 is released (s22).
After that, an interrupt is generated in INT0 or INT1, and it is communicated between the processors to check whether the first generated interrupt is of INT0 level or INT1 level (s23). If all the processors have started from the same level of interrupt, it is determined that there is no deviation in the count value (s24), and the process ends. This is because the count value does not deviate by 2 due to the skew. The first interrupt generated in each processor is INT0
If there is a difference between (even number) and INT1 (odd number), processing is performed so that the count values of all processors are aligned with the value starting at INT0 (even number). Therefore, it is determined which interrupt was issued to itself (s25), and INT0
If the start is (even number), the process ends. I
If the start is NT1 (odd number), the total count value is adjusted by adding or subtracting 1 from the total count value (s
26). Whether the total count value is incremented by one or decremented by one is determined by measuring the time from when the interrupt is released to when the first interrupt is received by using an internal timer, for example, to determine whether the user is advanced or delayed. be able to.
That is, when an interrupt at the INT1 level is accepted immediately after the interrupt is released, it can be determined that the count value is one larger than the other INT0 (even) start processors. Further, when an INT1 level interrupt is accepted after a lapse of time after the interrupt is released, one processor is set higher than the other INT0 (even) -based processors.
It can be determined that the count value is small.

It is not necessary to provide a large-volume, high-speed data communication function for the communication in s23. That is, in order to match the total count value of the interrupt, it is only necessary to bring in once whether the first generated interrupt is the INT0 level or the INT1 level at the start of the system. Only one reciprocation via the serial line 6 is required. In addition, serial line 6
In addition to the method using, a method may be used in which one's own parity is written in a shared memory, and all processors refer to this, or a method in which another processor such as a host sums up.

FIG. 8 is a block diagram of a parallel processing apparatus according to a fifth embodiment of the present invention. This parallel processing device also has n processors 22-1 to 22-n connected in parallel, but has a data clock DATACL synchronized with the data input.
K are all input to INT0. In this embodiment, since the interrupt line is not the point, the interrupt line is omitted in FIG.

A data synthesizing device 23 is provided at a stage preceding the processor group 21. In the data synthesizing device 23, the data fetch unit 24 includes the processors 22-1 to 22-n
The data ADATA to be processed is taken and input to the synthesizing unit 25. The count value cc is input to the synthesizing unit 25 in accordance with the data input. Data capture unit 24
Both the counter generator 26 operates based on the same clock. The synthesizing unit 25 embeds the count value cc in the last several bits of the data ADATA and supplies it to the processor as INPDAT. The data synthesizing device 23 performs the above-described processing for all n pieces of data processed by each of the processors 22-1 to 22-n of the parallel processing device 21 within the time of one interrupt clock.

If ADATA is, for example, data output from a 12-bit AD converter, the width of the bus is 1
When there are 6 bits, 4 bits are available for this count value. Therefore, the count value generated by the counter generator 26 is embedded in these 2 to 4 bits and input to each of the processors 22-1 to 22-n.
2-1 to 22-n select the processing by referring to the value of the predetermined bit, so that the processing can be synchronized in all the processors.

The count value generated by the counter generator 26 is generally a value counted up for each data clock DATACLK. However, this count value is set to one bit, and one bit is used for several counts. By setting to be "1" every time, each processor can be synchronized by the input of "1".

In this method (synchronous method using a data bus), the data bus width is increased. However, since the configuration of a processor for performing parallel processing is simple, when the input data is preprocessed by the processor, It is extremely effective. By securing a large number of bits of cc, the problem of synchronization with a large number of counts can be dealt with, so that there is flexibility.

In the above-described embodiment, the deviation of the count value due to the skew at the time of turning on the power is eliminated. However, resynchronization can be performed during operation. For example, an interval of an interrupt signal by the data clock DATACLK may be detected. Each processor monitors the data clock interval with an internal timer, and when the interval exceeds a predetermined time (when the timer times out), the interrupt counter is cleared. In this way, even during long-term operation, by stopping the supply of the data clock when data processing is not required, the total count can be synchronized, which contributes to safe design.

In the above embodiment, the signal (data clock: DATACLK) for notifying the processing timing is input to each processor as an interrupt signal, but the method for notifying the processing timing is not limited to this. For example, the same function as the above-described interrupt can be realized also in a polling process in which a strobe signal synchronized with a timing signal is input to each processor as a status, and each processor accesses the host in response to the strobe signal.

As a method of synchronizing the count of the process without increasing the number of data bits and the interrupt level, a dummy interrupt for synchronizing the count in addition to the interrupt DATACLK for taking in the data (start of the process) is adopted. A signal can also be generated. That is, in response to an interrupt signal having an interval shorter than a predetermined threshold value, each processor is programmed not to fetch data in response thereto, and a predetermined processing count value is reached ( ), Dummy interrupt signals are generated at intervals shorter than the threshold after DATACLK is generated. Each processor resets its own count value to a predetermined value when such a dummy interrupt signal is input. This makes it possible to synchronize processing counts.

For example, in the device shown in FIG. 11A, as shown in FIG. 11B, the clock generation circuit 33 outputs DATACL every 100 ms in accordance with the data input.
K is generated, but a dummy clock signal DMCLK is generated 10 ms after DATACLK at intervals of three times. Each processor 32 (32-1 to 32-n) is a DMCL
It resets its own count value so that the next processing cycle after the processing cycle in which K was input is a cycle of another processing once every three times. As described above, the dummy clock signal DMCLK is generated in the processing cycle before the predetermined processing cycle, so that the processor starts processing after confirming whether or not DMCLK is input in each processing cycle. There is no need to provide a waiting time.

In this method, if the time measurement accuracy of the interrupt interval of each processor is high, DATACL
It is also possible to switch between a plurality of types of processing by giving meaning to the time interval from K to DMCLK.

In the above embodiment, the parallel processing device in which the processors are arranged in parallel has been described as an example. However, the present invention is not applied only to the parallel processing, and is not limited to the parallel processing. It can be applied to various processor arrangements such as types.

[0041]

As described above, according to the present invention, count synchronization between processors can be realized with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram of a parallel processing device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an algorithm for processing switching of the parallel processing device.

FIG. 3 is a block diagram of a parallel processing device according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a parallel processing device according to a third embodiment of the present invention.

FIG. 5 is a flowchart showing an operation at the time of starting the parallel processing device.

FIG. 6 is a block diagram of a parallel processing device according to a fourth embodiment of the present invention.

FIG. 7 is a flowchart showing a count value adjustment processing operation of the parallel processing device.

FIG. 8 is a block diagram of a parallel processing device according to a fifth embodiment of the present invention.

FIG. 9 is a diagram illustrating a configuration example of a conventional parallel processing device.

FIG. 10 is a diagram illustrating a mechanism in which a count value shift occurs due to interrupt permission timing.

FIG. 11 is a block diagram of a parallel processing apparatus according to a sixth embodiment of the present invention and a timing chart of an interrupt signal.

[Explanation of symbols]

1 (1-1 to 1-n) processor, 3 demultiplexer, 5 parallel processing device, 11 (11-1 to 11-n) processor, 13 gate circuit, 15 parallel processing device, 21
... Processor group, 22 (22-1 to 22-n) ... Processor, 23 ... Data synthesizing device, 24 ... Data capturing unit, 24
... Counter generation unit, 25 ... Synthesis unit, 31 ... Processor group, 32 (32-1 to 32-n) ... Processor, 33 ... Clock generation circuit

Claims (4)

[Claims] 1. A plurality of processors that simultaneously execute processing in response to an input of a notification signal that notifies data processing, and signal switching means that switches the notification signal to a plurality of types and simultaneously inputs the notification signals to each processor. A multiprocessor device in which each processor switches processing according to the type of an input notification signal. 2. A processor that counts up a counter in response to an input of a notification signal for notifying data processing and executes processing on data to be processed, and switches the notification signal to a plurality of types and simultaneously inputs the notification signal to each processor. Each processor corrects the count value of the counter according to the type of the notification signal input first after the activation,
A multiprocessor device that switches processing according to the count value of this counter. 3. A processor that counts up a counter in response to an input of a notification signal for notifying data processing and executes processing on data to be processed, and that, after startup, sufficient initialization of each processor is completed. A gate means for simultaneously permitting each processor to input the notification signal after a lapse of a predetermined time, wherein each processor switches processing according to the count value of the counter. 4. A plurality of processors for synchronously executing processing on data to be processed, and synthesizing means for adding information on the number of data inputs to the data to be processed by each processor and then inputting the information to each of the processors. A multiprocessor device in which each processor switches processing according to information on the number of data inputs added to the input processing target data.