JPH07200486A - Information processor - Google Patents

Abstract

PURPOSE:To efficiently perform synchronous processing among tasks allocated to respective processors in a multiprocessor system. CONSTITUTION:A synchronous counter 14 indicates the number of processors which are not synchronized yet among processors that its processor should be synchronized with. A comparator 16 compares the current value 26 of the synchronous counter with a constant 0, and generates a synchronization completion signal 21 when the value of the synchronous counter 16 is 0. A simultaneous request signal generation part 10 receives a synchronous process request signal 20 from a processor and generates a synchronous request signal 24. A synchronous request signal transmission part 11 sends the synchronous request signal 24 out to the processor to be synchronized through an inter-processor network N.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system for efficiently performing a synchronization process between tasks assigned to each processor of the multiprocessor system.

[0002]

2. Description of the Related Art A basic problem that must be guaranteed in parallel processing is data transfer between tasks assigned to each processor and maintenance of an execution order. A hardware mechanism or software operation is required.

Usually, such synchronization between processors is realized through the shared memory of the system. That is, an area for confirming synchronization between tasks is set in the shared memory, and tasks that need to synchronize with other tasks can read and write while locking this area, so that the invoking task can read The other task is notified that the synchronization position is reached, or the other task confirms that the synchronization position in the instruction sequence is reached. The reason why the synchronization area in the memory is locked is that the values may become inconsistent between tasks if the values are written in or read from the same memory location at the same timing.

The inter-task synchronization performed via such a shared memory is effective in an application having a small degree of parallelism and a relatively small number of inter-task synchronizations because the hardware mechanism dedicated to the synchronization processing is small.

However, in an application in which the number of times of synchronization between tasks is large, accesses to the same memory area are concentrated from many processors, so the above-described method of synchronization between tasks via shared memory is not always necessary. Not valid.

That is, since access is concentrated on the same memory area from many processors, tasks operating in parallel are serialized by the synchronous processing. Further, since the traffic of the network between the processor and the shared memory increases, the influence on the task that is not related to the synchronization processing becomes large. For this reason, the execution performance of the entire multiprocessor system is reduced.

The rate of such performance deterioration increases as the number of times synchronization is performed in the application increases and as the interval between instructions for synchronization in one task decreases.

In order to solve such a problem, there is a technique of providing a dedicated register for synchronization processing between tasks and a communication dedicated between tasks and a dedicated path between these synchronization / communication registers and a processor in addition to the shared memory. It is disclosed in Japanese Patent No. 238553. In this technique, the register accessed by the synchronous processing and the path used are different from those of the normal memory access, so that it is possible to remove the influence on the task not related to the synchronous processing as described above. However, if the synchronization / communication register is unique to the system, the synchronization processing overhead that becomes apparent in an application with a large number of synchronizations cannot be improved by this technique.

[0009]

In such a conventional technique, there is a problem that the inter-task synchronization processing has a bad influence on the processing of other tasks, and a problem that the overhead of the synchronization processing itself is large. When the synchronization / communication dedicated register is provided, adverse effects on other tasks are reduced, but the overhead of the synchronization processing itself has not been shortened.

[0010]

In order to solve the above problems, the multiprocessor system of the present invention comprises a synchronization control unit for each of these processors, and an interprocessor network connecting all the synchronization control units, The synchronization control unit counts the number of processors that have reached the synchronization processing among the processors to be synchronized with the own processor (hereinafter, a synchronization counter), and a synchronization request signal to the processors to be synchronized by the own processor. A synchronization request signal transmitting means, a synchronization request signal receiving means for receiving a synchronization request signal from its own processor or another processor, and a value of the synchronization counter based on the synchronization request signal from the synchronization request signal receiving means. Control means for controlling,
After the self-processor executes the synchronization instruction, the value of the synchronization counter is monitored to confirm that the synchronization has been completed with all the synchronization target processors, and the synchronization completion signal generating means for generating the synchronization completion signal is synchronized with the self-processor. After execution of the processing, means for suppressing the subsequent instruction processing of the own processor until the synchronization completion signal is generated by the synchronization completion signal generating means.

According to the present invention, task synchronization processing can be efficiently performed without adversely affecting tasks unrelated to synchronization.

That is, since the completion of the synchronization is waited for by monitoring the above-mentioned synchronization counter independently provided in each processor, the shared memory or the only synchronization / communication register in the system is used to confirm whether the synchronization is completed. Since it does not need to be repeatedly accessed, there is little adverse effect on other tasks.

Further, it is possible to flexibly specify a processor to be synchronized.

[0014]

An embodiment of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, in the first embodiment of the present invention, each executes a barrier synchronization instruction for a task that needs to be synchronized with another task, and the own processor synchronizes with the processor to be synchronized. A plurality of processors P0-Pn that hold the state until the request signal is transmitted and the synchronization completion signal is received and the processing of the subsequent instruction is stopped, and the synchronization request signals from these processors P0-Pn are received and synchronized with their own processors. Controls the counter that counts the number of processors that have reached the synchronization processing among the target processors, monitors the value of the synchronization counter after executing the synchronization instruction by its own processor, and confirms that synchronization has been completed with all the synchronization target processors and synchronizes A plurality of synchronization control units C0- that generate completion signals
Cn, the processors P0-Pn and the synchronization control unit C0
An interprocessor kit work N configured by a crossbar kit work for connecting -Cn and a shared memory M connected to the interprocessor kit work are provided.

Referring to FIG. 2, each of the synchronization control units C0-Cn according to the second embodiment of the present invention receives the synchronization request signal 24 based on the synchronization processing request signal 20 from the processor P.
And a synchronization request signal 22 from the synchronization request signal generation unit 10.
And a synchronization request signal receiving circuit 12 for receiving a synchronization request signal 23 given from another processor via the interprocessor network N and generating a synchronization request signal 25.
, A synchronization counter 14 that indicates the number of processors that have not yet completed synchronization among the processors that should be synchronized with its own processor, a decrementer 15 that subtracts the current value 26 of this synchronization counter 14, and this current value 26 Is a constant "0", and when it is "0", the synchronization request signal 24 of the own processor from the comparator 16 and the synchronization request signal generator 10 which generates the synchronization completion signal 21 and gives it to the processor P, The sync request signal 25 from the sync request signal circuit 12 and the current value 26 from the sync counter 14
The value 29 to be set (the number of processors to be synchronized-1) 29 is output to the synchronous counter 14 at the next clock based on the following, and the value 29 to be set to the synchronous counter 14, the output 27 of the decrementer 15 and the current value of the synchronous counter 14 are output. And a synchronous counter control circuit 13 for outputting a selection instruction signal 28 for selecting and giving any one of the values 26.

Next, the operation of the first embodiment of the present invention will be described in detail.

Referring to FIG. 1, a plurality of processors P
0, P1 ... Pn are directly connected to the interprocessor network N. Further, the processors P0, P1 ... Pn are respectively connected to the synchronization control units C0, C1 ... Cn, and the respective synchronization control units C0, C1 ... Cn are respectively connected to the processor P.
A synchronous instruction processing request is received from 0, P1, ... Pn. Further, the synchronization control units C0, C1 ... Cn are also connected to the inter-processor network N, and each sends a synchronization request signal to another processor or receives a synchronization request signal from another processor.

For a task that requires synchronization with another task, a synchronization instruction is inserted in the instruction sequence as needed. Here, a barrier synchronization instruction is set as one of the instructions of each processor.

When the processing reaches the barrier synchronization instruction, the processor performs the next processing.

(1) A synchronization processing request is sent to the synchronization control unit.

(2) The hold state is maintained until the synchronization completion signal is received from the synchronization control unit, and the processing of the subsequent instruction is stopped.

When the processor P executes the barrier synchronization instruction, it transmits a synchronization processing request signal to the synchronization control unit C, and stops the processing of the subsequent instruction of the barrier synchronization instruction until it receives a synchronization completion signal from the synchronization control unit C.

When the synchronization control unit C receives a synchronization request signal from the processor P or another processor via the network, it refers to the value 26 of the synchronization counter 14, and when the value of the synchronization counter 14 is "0" (the synchronization target processor Number −
1) is selected, the output of the decrementer 15 is selected when the value of the synchronous counter 14 is not "0", and when the synchronous request signal is not received from anywhere, the synchronous counter 1 is selected.
The signal line 28 controls the selector of the synchronous counter so as to hold the value of 4.

In the synchronization control unit C, the value of the synchronization counter 14 is 0.
Then, the synchronization completion signal is generated by the comparator C06 and transmitted to the processor P.

Here, the synchronization counter 1 in the synchronization control unit C
When 4 is "0", the processor P is not in a waiting state for synchronization with another processor but in a normal instruction executing state. On the contrary, even when the processor P is in the normal operation state, the synchronization counter 14 is not always "0". That is, when another processor is waiting for the completion of synchronization of the hour processor. If the synchronization control unit C processes a synchronization request signal from another processor before the own processor, the synchronization counter 14
Is originally "0", but the value of the synchronization counter 14 is updated from "0" to another value by the synchronization request signal that first arrives regardless of the own processor / other processor.

In the first embodiment, a network between synchronization control units for synchronizing between processors is provided.
Since it is shared with the network between shared memories, the amount of hardware for synchronous control can be suppressed. Also, communication between processors for synchronization control is only a synchronization request signal that notifies the processor to be synchronized that the self processor has processed the synchronization instruction. Since the registers are not repeatedly accessed, it is possible to suppress the adverse effects of the frequent occurrence of synchronization request signals for processors and tasks that are not related to synchronization.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 3, the processor P0-Pn, the synchronization control units C0-Cn, the inter-processor network N and the shared memory M shown in the first embodiment are different from the second embodiment.
The features of this embodiment are as follows.

That is, the interprocessor network N is directly connected to the plurality of processors P0-Pn and the shared memory M. Further, the synchronization request signal is exchanged between the synchronization control units C0-Cn via the inter-synchronization control network S directly connected to the synchronization control units C0-Cn.

In the second embodiment of the present invention, by providing the inter-synchronization control unit network S separately from the inter-processor network N, as compared with the first embodiment, it is possible to deal with processors and tasks which are not related to synchronization. It is possible to further reduce the adverse effect caused by the frequent occurrence of the synchronization request signal.

Next, a third embodiment of the present invention will be described in detail with reference to the drawings.

In an actual multiprocessor system, in order to effectively use the processor resources of the system, not all tasks that can operate at the same time or all tasks that should be barrier-synchronized are allocated and executed at the same time for each processor. That is, it is necessary to realize synchronization even for tasks that are not being executed in the system at the same time.

This problem can be solved by having a plurality of synchronization counters in the synchronization control unit of the first and second embodiments.

Next, a third embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 4, the third embodiment of the present invention is a synchronization request signal generation unit 10, a synchronization request signal transmission unit 11, and a synchronization request signal reception circuit 1 in the first embodiment.
In addition to 2, the following characteristic elements are provided.

That is, the third embodiment of the present invention comprises a plurality of synchronization counters 140-14n, and these synchronization counters 14-14n.
Decrementer 150-corresponding to each of 0-14n
15n and a comparator 160-16n, a selector 18 for selecting one of the current values 260-26n from the synchronous counter 140-14n, and a comparator 1.
In addition to the selector 17 that selects one of 60-16n, the synchronization request signal generation unit 10 and the synchronization request signal reception circuit 1
2 outputs the selection instruction signal 280-28n to the input selector of the synchronization counter 140-14n according to the job number included in the synchronization request signal 24 or 25, and outputs the selection instruction signal. The present invention includes a synchronous counter control circuit 13 for inputting any of the current values 260-26n of the synchronous counters 140-14n, which is the result of selection in step 1, and outputting a signal 29 indicating the number of processors to be synchronized-1. The operation of the third embodiment will be described in detail.

Referring to FIG. 4, the job number 30 is the number of the job currently being executed by the processor itself and is managed by the OS. The job number 30 is input to the synchronization signal generator 10 and the selector 17.

When the synchronization request signal generation unit 10 receives the synchronization instruction processing request 20 from its own processor, it generates a synchronization request signal 24 and sends it to the synchronization counter control unit 13 and the synchronization request signal transmission unit 11. The synchronization request signal 24 includes the job number of the task that has issued the synchronization request.

The synchronization request signal transmission section 11 outputs the synchronization request signal 2
4 is received, and a synchronization request signal is sent from the signal line 22 to the synchronization target processor through the inter-processor network N or the synchronization control unit network S.

The synchronization request signal receiving circuit 12 receives the synchronization request signal 23 from another processor through the inter-processor network N or the inter-synchronization control unit network S and transfers the synchronization request signal 25 to the synchronization counter control unit 13.

When the synchronization counter control circuit 13 receives the synchronization request signal from the synchronization request signal generator 10 or the synchronization request signal receiving circuit 12, the synchronization counter 140 changes from the synchronization counter 140 to the synchronization counter 1 according to the job numbers included in the synchronization request signals 24 and 25.
The 4n input selector is controlled by signals 280 to 28n. That is, hold is selected except for the sync counters assigned corresponding to the job numbers indicated by the sync request signals 24 and 25, and the decrementer 15 corresponding only to the sync counter corresponding to the job numbers indicated by the sync request signals 24 and 25.
A signal 24 indicating the output of 0 to 15n or the number of synchronization target processors-1 shown in the synchronization request signal is selected.

The synchronization counter control unit 13 outputs the synchronization request signal 2
The selector 18 is controlled by the signal 31 according to the job number of 4 or 25, and the current value 26 of the one corresponding to the job number in 14n is obtained from the synchronization counter 140.

When the current value 26 is "0", the synchronization signal 24
The selector of the synchronous counter corresponding to the job number indicated by or 25 is controlled to select the signal 24, and when the signal 26 is not "0", the output of the decrementer is selected.

The outputs of the comparators 160 to 16n are selected by the selector 17 and the job number 210 as the comparator output corresponding to the task being executed by the processor, and are sent to the processor as the synchronization completion signal 21.

As described above, each processor can accept a synchronization request from another task even while executing a task other than the synchronization target. Further, the synchronization completion signal is sent to the processor only when the job to which the synchronization target task belongs is being executed, and an incorrect synchronization completion signal is not generated while a task irrelevant to a synchronization request from another processor is being executed.

In the first to third embodiments,
The method for each processor to specify the processor to be synchronized is not specified.

A method of defining a synchronization target processor in the fourth embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 5, barrier synchronization instructions to be executed by each processor are defined in the format shown. In the synchronization target processor designation field, each bit corresponds to a physical processor, and the processor corresponding to the bit of 1 is the synchronization target processor.

When each processor executes the barrier synchronization instruction, the synchronization processing request valid bit is directly connected to the synchronization target processor designation field of the barrier synchronization instruction to generate the synchronization processing request signal, and the synchronization control section corresponding to the self processor is generated. Just send it out.

In the fourth embodiment, since the synchronization target processor is designated by the synchronization target processor designation field of the barrier synchronization instruction, all the tasks which can be executed simultaneously and the processor which executes the task are supported when the barrier synchronization is not required. It is only necessary to drop the bit to be used, and flexible synchronization control is possible.

The synchronization target processor designating method according to the fourth embodiment corresponds to all of the first to third embodiments.

In the fourth embodiment, the number that can be specified as the synchronization target processor has a drawback that it depends on the instruction word length. If the number of processors is larger than the bit length of the synchronization target processor designation field, the fourth embodiment cannot handle it.

Next, as a fifth embodiment of the present invention, another method of designating a synchronization target processor will be described in detail with reference to the drawings.

Referring to FIG. 7, the synchronization control unit is assumed to include one or a plurality of synchronization target registers 19 for designating a synchronization target processor. Each bit of each synchronization target register 19 corresponds to a physical processor number and has a value “1”.
The processor corresponding to the bit is the processor to be synchronized.

The barrier synchronization instruction is defined in the format shown in FIG. The instruction type field is followed by a synchronization target register designation field. Each processor concatenates the synchronization target register designating field of the barrier synchronization instruction to the synchronization processing request valid bit as it is to generate a synchronization processing request signal and sends it to the synchronization processing unit.

In the synchronization processing unit, the output of the synchronization target register 19 is selected by the synchronization target register designation field of the synchronization request signal and input to the synchronization request signal generation unit 10.

The control of the synchronization request signal generator 10 and below is the first
This is the same as in Examples N to 3 of the above.

In the fifth embodiment, each synchronization target register 19
No matter how many processors there are, the synchronous processing can be performed between any of the processors as long as the bit lengths of all the processors are provided.

Further, the synchronization target register 19 can be shared with a general-purpose register used for calculation in each processor. In this case, an increase in the amount of hardware due to the addition of the synchronization target register 19 can be suppressed.

In the fourth embodiment, the synchronization target processor is specified in the instruction word, but it is impossible to specify on which processor each task will be executed when the software is compiled. Conversely, if you specify the processor that executes each task at compile time and decide the synchronous processor specification field of the barrier synchronization instruction, you must assign each task to the processor specified at compile time and execute it. It becomes impossible to operate.

Next, a sixth embodiment of the present invention showing a solution to this problem will be described with reference to the drawings.

In the sixth embodiment of the present invention, the synchronization target processor designation field of the barrier synchronization instruction of FIG. 5 is changed to a field which designates a logical task number which can be determined at compile time, instead of a physical processor number. To do.
That is, the task corresponding to the bit having the value “1” is the task to be synchronized.

Each processor concatenates the synchronization target task designation field of the barrier synchronization instruction to the synchronization processing request valid bit as it is to generate a synchronization processing request signal and sends it to the synchronization processing unit.

Further, as shown in FIG. 8, a mechanism for converting the synchronization target task number into the processor number to which each task is actually assigned is added to the synchronization processing section. The synchronization processing unit converts the synchronization target task number of the synchronization processing request signal into a real processor number and inputs it to the synchronization request signal generation unit 10.

The register 9 manages which processor each task is assigned to. Each bit of the register 9 corresponds to each processor, and the task corresponding to the bit of the value "1" is assigned to the processor. This register 9 has one set of bit length sentences in the task number field, and has a plurality of sets corresponding to job numbers.

This embodiment enables flexible operation of the system.

[0068]

As described above, according to the present invention, it becomes possible to flexibly and efficiently perform synchronization control between processors of a multiprocessor and between tasks.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a synchronization control unit in the first embodiment in FIG.

FIG. 3 is a diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a synchronization control unit according to a third embodiment of the present invention.

FIG. 5 is a diagram showing an example of a format of a synchronization instruction according to a fourth embodiment of the present invention.

FIG. 6 is a diagram showing an example of a format of a synchronization instruction according to a fifth embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a synchronization control unit according to a fifth embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a synchronization control unit according to a sixth embodiment of the present invention.

[Explanation of symbols]

C synchronization control unit P processor 14 synchronization counter 10 synchronization request signal generation unit 11 synchronization request signal transmission unit 12 synchronization request signal reception circuit 13 synchronization counter control circuit 15 decrementer 16 comparator 20 synchronization processing request signal 21 synchronization completion signal 22 synchronization with other processors Synchronization request signal to control unit 23 Synchronization request signal from synchronization control unit to other processor 24 Synchronization request signal 25 Synchronization request signal reception signal 26 Current value of synchronization counter 27 Output of decrementer 15 28 Input selector control signal of synchronization counter 29 (Number of synchronous processors) -1

Claims (8)

[Claims] 1. A multi-processor that takes necessary synchronization between tasks assigned to its own processor by a synchronization request signal generated according to each instruction sequence executed by each of a plurality of processors connected via a network. In the processor system, each of the processors includes a synchronization control unit and an inter-processor network connecting the synchronization control units, and the synchronization control unit is a synchronization processing unit among the processors to be synchronized with the own processor. Synchronization counting means for counting the number of processors that have reached, synchronization request signal receiving means for receiving a synchronization request signal from its own processor or another processor, and the synchronization counting means based on the synchronization request signal from the synchronization request signal receiving means. Control means for controlling the value of the Synchronization completion signal generation means for monitoring the value of the stage and confirming that synchronization has been completed with all the synchronization target processors, and a synchronization completion signal generation means for executing synchronization processing by the own processor and synchronization by this synchronization completion signal generation means A multiprocessor system comprising: a suppression unit that suppresses subsequent instruction processing of its own processor until the completion signal is generated. 2. The synchronization request signal comprises a synchronization request valid bit and at least one synchronization target processor number, and the synchronization request signal receiving means responds to the reception of the synchronization request signal by counting the number of synchronization target processors and the synchronization count. A request to update the means to the control means, and the control means responds to the update request to the synchronization counting means and the reception of the number of processors to be synchronized, and the current value of the synchronization counting means is "0". Is the number of processors to be synchronized −
1) is set, and when the current value of the synchronization counting means is not "0", the value of the synchronization counting means is changed, and the synchronization completion signal generating means sets the value of the synchronization counting means to "0". The multiprocessor system according to claim 1, wherein the synchronization completion signal is sometimes generated. 3. The processor according to claim 1, wherein each of the processors inserts the synchronization request signal generation instruction into an instruction sequence, and generates a synchronization request signal when the processor executes the synchronization request signal generation instruction. Alternatively, the multiprocessor system according to claim 2. 4. The interprocessor network connecting the synchronization control unit is an independent interprocessor network different from the shared memory-processor network. The multiprocessor system according to claim 3. 5. The synchronization control section includes a plurality of the synchronization counting means and means for associating each synchronization counting means with a job number of a job executed by each processor, and each synchronization counting means in the system. 5. The multiprocessor system according to claim 1, claim 2, claim 3, or claim 4, wherein tasks are synchronized for each job by allocating to each job that is being executed simultaneously. 6. The instruction for generating the synchronization request signal comprises:
An instruction type field and a field indicating a physical synchronization target processor number in bit units, and the synchronization control unit sends a synchronization request signal to the processor indicated by the synchronization target processor number when each processor executes the synchronization instruction. 6. The multiprocessor system according to claim 1, claim 2, claim 3, claim 4 or claim 5, which sends out. 7. The instruction for generating the synchronization request signal comprises:
An instruction type field and a field indicating a logical synchronization target task number in bit units, and the synchronization control unit includes means for converting the synchronization target task number into a physical processor number to which the task is allocated. 4. The synchronization control unit sends a synchronization request signal to the processor indicated by the physical processor number when each of the processors executes the synchronization instruction. 4. The multiprocessor system according to claim 4, and claim 5. 8. Each synchronization control unit includes at least one synchronization target register indicating a physical synchronization target processor number, and an instruction for generating the synchronization request signal includes an instruction type field and an instruction type field of the synchronization control unit. When each of the plurality of synchronization target registers is provided, the synchronization target register number and a field for designating the synchronization target register number are included, and the synchronization control unit controls the processor indicated by the synchronization target register when each of the processors executes the synchronization instruction. The multiprocessor system according to claim 1, claim 2, claim 3, claim 4, or claim 5, which transmits a synchronization request signal.