JPH05114718A - Programmable analog master - Google Patents

Abstract

PURPOSE:To obtain a programable analog master with which a developing period can be reduced remarkably. CONSTITUTION:The title programmable analog master is provided with wiring groups 2 and 3, which are arranged in matrix form by connecting to the transistor, resistor, capacitor and the like which are array-like arranged on a chip 1, switch groups 4 which are arranged on the crossing part of the above- mentioned wiring groups 2 and 3 and inserted between wirings in vertical and horizontal directions, and a control part with which the above-mentioned switch groups are ON-OFF controlled in a selective manner. The required circuit can be constituted by mutually and selectively connecting the wiring groups in vertical and horizontal directions using the control part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog master integrated circuit in which analog elements are arranged on an array, and more particularly to a programmable analog master capable of manufacturing any analog integrated circuit in a short development period.

[0002]

2. Description of the Related Art Conventionally, in the development of analog integrated circuits, after circuit design, analog characteristics have been confirmed by SPICE, and layout design has been performed manually. The layout is designed with elements such as transistors, resistors, and capacitors as units, and attention is paid to various restrictions such as matching between elements, wiring impedance, and parasitic capacitance. After that, a prototype is made and sample evaluation is performed. This development method has a problem that it takes a long design period because the layout design is performed manually, and the prototype period is long because the impurity diffusion for forming each element is performed from the first diffusion process step. In addition, since a mask is required for all the steps, the development cost will be high.

In order to solve such a problem, there is provided a so-called "analog master" in which analog devices such as NPN transistors, PNP transistors, various resistors and capacitors are arranged on the array like the gate array. In the analog master, since the devices are regularly arranged, the aluminum wiring is designed so that it can be laid on a regular lattice, and the automatic layout by CAD becomes possible, and the layout design period can be greatly shortened. Further, since the trial manufacture may be performed from the patterning of the first aluminum wiring, the trial manufacture period can be significantly shortened as compared with the conventional process including diffusion.

[0004]

However, since such an analog master has a problem peculiar to the analog circuit,
It is difficult to completely verify the characteristics by simulation, and the actually manufactured sample is mounted on a board for set evaluation.The defects found in this evaluation are re-corrected after the layout is corrected. You have to make a prototype. In particular, the user's demand for shortening the development period is becoming more and more severe, and a sample for verification is required immediately after confirmation by a simulation after circuit design. In order to meet such demands, the current analog master has a limit in shortening the delivery time because it actually makes a mask and makes a prototype. In addition, the constant may be changed to change the subtle characteristics of the analog circuit. To realize this with an analog master, it is conceivable to provide an adjustment terminal outside or a master slice method, but the former is parasitic. The characteristics may be deteriorated in terms of capacity, temperature, etc., and the latter is usually limited to a change range of about three master slices. It is an object of the present invention to provide a programmable analog master that can significantly shorten the development period.

[0005]

SUMMARY OF THE INVENTION A programmable analog master of the present invention comprises transistors arranged in an array,
A group of wirings connected to elements such as resistors and capacitors and arranged in a matrix, a group of switches arranged at intersections of these wiring groups and interposed between wirings in a vertical direction and a horizontal direction, and these switch groups And a control unit for selectively turning on and off. Further, it is preferable that a part of the circuit of at least one analog circuit block is fixedly connected by metal wiring.

[0006]

According to the present invention, the vertical and horizontal wirings can be connected by turning on an arbitrary switch, whereby an arbitrary analog circuit can be constructed only by switch control. Further, the resistance and the capacitance are reduced by fixedly connecting some of the circuits of the analog circuit block with metal wiring.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a programmable analog master of the present invention. This analog master divides the semiconductor chip 1 into seven blocks here. That is, a GND wiring block (I), a resistance block (II) composed of a large number of basic resistors, an NPN transistor block (III) formed assuming that a constant current circuit is formed, differential and bi-differential circuits. Etc., an NPN or PNP transistor block (IV), a transistor block (V) consisting of NPN or PNP transistors assuming a transistor load, etc., a resistance load, a resistance block for the purpose of determining the current ratio of the current mirror ( VI), power supply V _CC block (VI
I). In other words, it has a structure in which resistors, transistors, etc. are hierarchically stacked between the GND wiring block (I) and the power supply wiring block (VII). The transistor block (III) may be composed of only the NPN transistor or the PNP transistor alone, or the NPN transistor and the PNP transistor may be mixed.

Then, on this semiconductor chip 1, a horizontal wiring group (broken line) 2 is formed between the blocks by a first aluminum wiring, and a vertical wiring line is formed in the vertical direction which is orthogonal to the first aluminum wiring. The wiring group (one-dot chain line) 3 is formed by the second aluminum wiring. Further, a switch group 4 is arranged at the intersection of the horizontal wiring group 2 and the vertical wiring group 3 as shown by a circle in the figure, and the horizontal wiring group 2 and the vertical wiring group 3 are formed by these switch groups 4. Are arbitrarily connected or insulated. Then, a control circuit (not shown) for controlling the switch group 4 is formed on a part of the chip 1, and the switch group 4 is selectively turned on and off by this control circuit. As the control in this case, a method can be adopted in which each switch is associated with an address of the control circuit and this address data is set as desired to selectively operate the switch of the corresponding address. Since each switch is normally off, the wiring groups 2 and 3 are not connected to each other and each element is in a floating state. When the switch is turned on by the drive signal from the switch control circuit, each wiring group is connected to each other, and a desired analog circuit is formed together with the element.

FIG. 2 shows a first example of the configuration of the switch. When the Zener diodes 11 and 12 are connected in the reverse direction and turned on, the Zener diodes 11 and 1 are turned on.
The switch is turned on by destroying one of the two and causing a short circuit. Also, FIG. 3 shows a second example of the switch,
Is an oxide film, 22 is a first aluminum wiring as a horizontal wiring group, 23 is an interlayer insulating film, 24 is a second aluminum wiring as a vertical wiring group, and 25 is formed on the bottom surface of a through hole provided in the interlayer insulating film 23. It is a thin insulating film of about 100Å. In a normal use state, the first aluminum wiring 22 and the second aluminum wiring 24 are insulated by the thin insulating film 25 in the through hole portion, but thin when the high voltage pulse from the switch control portion is applied to the switch. The insulating film 25 is destroyed and the first aluminum wiring 22
Then, the second aluminum wiring 24 is short-circuited and the switch is turned on. Therefore, a bidirectional switch with extremely low on-resistance can be realized.

FIG. 4 is a plan view showing how the differential amplifiers are specifically connected as an example. Also, FIG.
Is an equivalent circuit diagram thereof. By turning on the switch 4A shown in FIG. 4 among the switch group 4 shown in FIG. 1, the horizontal wiring group 2 and the vertical wiring group 3 are connected at this intersection, and the circuit shown in FIG. 5 is configured. In addition, here, Q3 forming a constant current circuit
Has three basic transistors connected in parallel. Also, the resistance is 500 Ω and 2 KΩ by combining 1 KΩ for each line.
Is made to match the circuit constants.

The development flow of the programmable analog master according to the present invention is shown in FIG. After circuit design, SPICE
The circuit characteristics are verified, the netlist is compiled, and writing is performed by a dedicated writer so as to turn on a desired switch on the chip. Next, after evaluating the integrated circuit alone, the GA, standard cell,
This integrated circuit is mounted on a substrate on which various integrated circuits such as CCDs and drivers are mounted, and the entire board is evaluated. If no problem occurs in this integrated circuit in this evaluation, the circuit is corrected and the same procedure is repeated using a new chip again. If the board evaluation is OK, a mask pattern of a normal mass production analog master is formed and mass production is performed. By using this development flow, a chip can be made from a circuit simulation without making a mask.

[0012] Therefore, the designer himself C
The chips can be designed with the help of AD tools, which can significantly reduce the development period. Further, it is also possible to verify the analog circuit at the board level by using this programmable analog master, make some corrections, and then mass-produce it by the analog master. If you are only producing a small amount, it is more advantageous to produce the entire lot with this programmable analog master chip, but if you are producing a large amount, this chip will shorten the development period and mass production will be an analog master for mass production. Therefore, it is advantageous to lower the chip unit price.

Further, since a circuit after simulation verification is converted into a netlist and is compiled, a desired circuit can be made by turning on a necessary switch in a switch group by a writer, so that a large number of circuits can be formed on a wafer. It can be experimentally prototyped, and can be said to be most suitable for making analog circuit libraries, making small circuit changes, setting conditions, and evaluating variations. Also, since the period from simulation to chip making is very short, you can perform detailed simulation again immediately after analyzing the characteristics with this programmable analog master, and analyze it. Will be a powerful tool. Here, although the capacitance is not described in the above-mentioned embodiment, a capacitance block including a MOS capacitor may be provided on the resistance block (VI) in FIG. This capacitance is extremely important when making an analog filter circuit.

FIG. 7 is a diagram showing a modification of FIG. 4. In this embodiment, the emitters of the transistors Q1 and Q2 are connected in advance by aluminum wiring, as indicated by the thick line in the figure. The block of the three basic transistors forming the transistor Q3 has a switch 4B at each terminal. In this way, by connecting the emitters of Q1 and Q2 in advance with the aluminum wiring, the offset of the differential transistor is not deteriorated, and the wiring capacitance is small, so that the frequency characteristic is good.

That is, in the current semiconductor process technology, it is difficult to set the on resistance of the switch to about several Ω and the capacitance value to about 1 pF, and if one is made small, for example, if the on resistance is made small, the other becomes It becomes large, that is, the capacitance value becomes large. However, by forming a part of the metal wiring in advance as described above, the switch can be omitted, and the wiring resistance and capacitance caused by the switch can be reduced.

FIG. 8 shows some examples of macros in the present invention. (A) is a macro in which the common emitters of the differential transistors are connected. By connecting in advance in the metal wiring process, it is possible to reduce the number of wirings and the number of switches that connect the blocks arranged outside the block region. (B) is an example in which the macros of (a) are connected in parallel, and an equivalent circuit is constructed by connecting the base and collector by a program. The wirings connected by the program are shown by broken lines. In this case, it can be used as a differential, or can be used as a single transistor which is connected in parallel to pass current.

Further, FIG. 1C shows a macro of the current mirror, and FIG. 1D shows an example in which a part of the circuit of the differential amplifier is made into a macro. In both cases, the solid line portions are preliminarily connected by aluminum wiring. By making such standard and widely used circuits into macros, not only can the number of wires and switches be greatly reduced, but also the wire resistance and capacitance can be greatly reduced, improving the analog circuit characteristics. Can be planned.

FIG. 9 shows an example in which the operational amplifier is made into a macro. By programming the resistor A shown in FIG. 9, the gain bandwidth product and the slew rate can be set to the values desired by the circuit designer after the mold assembly. .. Also, resistors B and C
It is possible to improve the offset of the operational amplifier by making the program variable. In this example, most of the circuits are connected in the metal wiring process of the wafer process process, so that the analog circuit characteristics are good.
In addition, since the analog characteristics such as frequency characteristics, gain, offset, etc. can be adjusted after the mold is assembled, the circuit characteristics can be adjusted and changed extremely easily. Figure 1
Reference numeral 0 indicates the resistances A, B, and C of FIG. 9 in a background image, and a desired resistance value can be obtained by turning on and off switches arranged at the intersections of vertical and horizontal wirings.

As a modification of the switch shown in FIG. 3, the structure shown in FIG. 11 can be adopted. In the figure, 3
1 is a field oxide film, 32 is a first aluminum wiring,
33 is an interlayer insulating film, 34 is a second aluminum wiring, 35
Is an interlayer insulating film, 36 is a third aluminum wiring, 37 is an interlayer insulating film, 38 is a fourth aluminum wiring, and 39 is a passivation film. Then, the first aluminum wiring 3
The thickness of a part of the interlayer insulating film 33 at the intersection of the second aluminum wiring 34 and the second aluminum wiring 34 is partially thinned to about 100 Å, and this is configured as a switch 40. Also in this example, if a high voltage pulse from the switch controller is applied between the first aluminum wiring 32 and the second aluminum wiring 34, the interlayer insulating film 33 of the switch 40 is destroyed and both wirings are short-circuited, The switch is turned on.

[0020]

As described above, according to the present invention, the circuit designer can configure the analog circuit by merely turning on the switch selectively, so that the development period can be significantly shortened as compared with the conventional analog master. Moreover, there is an effect that the development cost can be reduced because the mask is unnecessary. Also, because of the characteristics of the analog circuit, wiring lines that are strongly affected by parasitic elements are formed in advance in the wiring forming process in the wafer process, so this wiring has a low resistance and a low capacitance. It is possible to prevent deterioration of characteristics. In this case, the number of switches can be reduced and the chip size can be reduced by connecting some of them with metal wiring in advance. Further, since the length of the wiring within the block is limited within the height and width of the block, the parasitic wiring capacitance can be reduced. Further, for the inter-block wiring, since a wiring layer different from the wiring layer inside the block is used, it is possible to pass through the block, and wiring can be performed in the shortest distance, which is advantageous in terms of analog characteristics.

[Brief description of drawings]

FIG. 1 is a plan view of a chip according to an embodiment of the present invention and a diagram showing a hierarchical structure of basic blocks on the chip.

FIG. 2 is a circuit diagram of a first example of a switch.

FIG. 3 is a sectional view of a second example of the switch.

FIG. 4 is a schematic plan view of a chip in which the present invention is applied to a differential amplifier.

5 is an equivalent circuit diagram of FIG.

FIG. 6 is a flowchart showing a development flow of the present invention.

FIG. 7 is a schematic plan view similar to FIG. 4 of another embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram showing various macro examples according to the present invention.

FIG. 9 is a macro diagram of an example in which the present invention is applied to an operational amplifier.

10 is a background image diagram of resistors A to C in FIG. 9;

FIG. 11 is a cross-sectional view of another example of the switch of the present invention.

[Explanation of symbols]

 1 semiconductor chip 2 horizontal wiring group 3 vertical wiring group 4 switch group I to VII basic block

Claims (2)

[Claims] 1. In an analog master in which elements such as transistors, resistors, and capacitors are arranged in an array, a wiring group connected to the elements and arranged in a matrix, and a vertical group arranged at an intersection of these wiring groups. A programmable analog master, comprising: a switch group interposed between wirings in a horizontal direction and a horizontal direction; and a control unit for selectively turning on and off the switch group. 2. A part of at least one analog circuit block is fixedly connected by metal wiring.
Programmable analog master.