JP2001007207A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the period for developing linear ASICs. SOLUTION: When an electronic circuit is constructed by automatically selecting semiconductor elements within a block sequentially using a computer such that the electronic circuit can meet various needs of users, the computer automatically combines size-adjustable semiconductor elements based on various information about, for example, the adjustable range of each size-adjustable semiconductor element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for automatically selecting and arranging each semiconductor element constituting an electronic circuit, thereby shortening the development period and designing. The degree of freedom is realized.

[0002]

2. Description of the Related Art Conventionally, an ASIC is mainly composed of a MOS, and a gate array, a master slice and the like have been realized. MOS is a circuit mainly composed of a digital circuit, and a circuit is formed by turning on and off a transistor. Transistors, resistors, and the like have almost the same characteristics such as size, current capacity, and the like. Therefore, a transistor, a resistor, and the like are repeated, and these are selected by wiring to form one circuit, and an IC is realized.

[0003] However, a linear circuit, particularly a BIP linear circuit, has a plurality of electronic circuit blocks, and elements constituting the electronic circuit blocks have various characteristics and various sizes.
Therefore, semiconductor elements such as transistors, diodes, resistors, and capacitors are repeatedly arranged like a gate array or a master slice and cannot be selected to form a circuit.

For example, Japanese Patent Application Laid-Open No. 2-3952 (FIG. 1)
1) is an example. This is a so-called building block system in which an element arrangement region is formed in a rectangular shape, and a power supply line and a ground line are provided on both sides of the block.

In other words, when configuring an AM circuit, the required number of elements is determined, and all the elements are arranged in an arrangement area of the same size.

For example, eight arrangement areas of the same size are arranged side by side and formed in two rows. Among them, the electronic circuit block of A (for example, AM circuit) in three arrangement areas, 3
The electronic circuit block of B is constituted by the two arrangement areas, the electronic circuit block of C is constituted by the two arrangement areas, the electronic circuit block of D is constituted by the five arrangement areas, and the electronic circuit block of E is constituted by the three arrangement areas. I have.

That is, the arrangement areas having the same size correspond to building blocks, and the building blocks are arranged neatly on a rectangular IC so that they are arranged neatly. For example, the electronic circuit block C
Is unnecessary, these two blocks are deleted, and the remaining blocks are rearranged, another IC chip can be realized. If an electronic circuit block F is to be added, the building block including the blocks constituting the same is included. What is necessary is just to rearrange as follows.

This design method will be described with reference to FIG. For example, in the case of an AM / FM circuit IC, after a required circuit library is selected, a rectangular pattern library is formed in order to build the selected circuit library into an IC chip by a building block method. , Are arranged in an IC chip. Then, metal wiring is performed so as to select all of the pattern libraries. This is the first generation AM / FMIC that becomes the parent.

[0009]

The AM / FM circuit allows the pattern library to be used for many years because the generation of the circuit does not change so quickly, and is particularly suitable in the field of sound and the like.

However, in the case of an IC whose generation changes rapidly, an IC that is difficult to develop as a pattern library, and an IC that ends with its model, a gate array, a master slice, and the like, which are still implemented by MOS, are employed.

However, as described above, in a linear circuit, each element is substantially different from the beginning to the end of the circuit. For example, in the case of resistors, various elements ranging from several mΩ to several MΩ are used. For the Tr, a vertical PNP transistor, a lateral PNP transistor, a vertical NPN transistor, and the like are used. In these various transistors, Trs of various sizes are incorporated depending on the current capacity condition. Was.
Although the description is omitted, the same applies to the capacitor.

Therefore, it was substantially difficult to prepare all of these various resistors, capacitors, and Trs for the master slice.

[0013] In addition, it is practically possible to prepare several types of each element and to obtain characteristics by serial / parallel connection by selecting wirings in order to realize specific characteristics (resistance value, capacitance value or current capacity). Although it is possible, wiring must be arranged like a mesh, and there is a problem that computerization is difficult.

Further, some of the wirings such as meshes extend a long distance from one end of the chip to the other in a severe case. However, in this long extension area, there are elements that emit switching noise, those that emit unnecessary radiation noise by an oscillation circuit, those that emit leak current, and those that lose pairing. In some cases, it may be necessary to re-select, or rearrange to change the extension area of the wiring.

In such a case, the automatic design by the computer is canceled, and the position of the element, the route of the wiring, and the like are manually changed. Accordingly, there has been a problem that it is difficult to realize a short delivery time by employing such a manual design in an IC scale which is increasing day by day.

Further, as described above, in order to realize a specific characteristic (resistance value, capacitance value or current capacity), it is difficult to obtain a characteristic by series / parallel connection by wiring selection. When trying to adjust the size of a value that includes a fractional value (for example, 1.02 KΩ in the case of a resistance, for example), not only is it difficult to build the circuit, but sometimes it is necessary to give up the building and change the circuit design. I even had to start over.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device for automatically synthesizing a semiconductor element whose size can be adjusted.

[0018]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made by a computer so that each of semiconductor elements prepared in a block is automatically and sequentially selected to form a desired electronic circuit. At the time of automatic assignment, a semiconductor element whose size is adjustable is automatically synthesized based on size adjustment availability information and size adjustable range information on the semiconductor element stored in the computer.

Further, the size adjustable range information includes:
At least information on the minimum value that can be adjusted for each semiconductor element is stored. When the size adjustment value of the semiconductor element to be automatically synthesized by adjusting the size is smaller than the minimum value, the computer sizes the plurality of semiconductor elements. Adjust,
The combined semiconductor elements are connected to each other.

[0020]

Embodiments of the present invention will be described below. The present invention particularly relates to a linear circuit, and will be described here with a BIP-IC, but can also be applied to a MOS linear circuit.

Here, the feature of the present invention is that a semiconductor device prepared in a block is automatically selected sequentially and automatically allocated so as to constitute a desired electronic circuit by using a computer described in detail later. In this case, a size-adjustable semiconductor element is automatically synthesized based on size adjustment availability information and size-adjustable range information on the semiconductor element stored in the computer. More specifically, the computer adjusts the size of the semiconductor element to be automatically synthesized based on the size-adjustable minimum value information for each semiconductor element stored in the size-adjustable range information. When the value is smaller than the minimum value, the size of the plurality of semiconductor elements is adjusted, and the synthesized semiconductor elements are connected to each other, so that the automatic synthesis of the size-adjustable semiconductor elements is accurately performed. Wiring for connecting semiconductor elements is realized with a minimum number of wires.

A method for manufacturing a semiconductor integrated circuit device according to the present invention, particularly a method for automatically synthesizing a semiconductor element whose size can be adjusted, will be described below with reference to FIGS.

When automatic synthesis is performed by a computer, it is necessary to previously store various information relating to size adjustment in the computer. Therefore, in the present invention, automatic synthesis is performed under the conditions shown in FIG. The computer is controlled so as to automatically synthesize electronic circuit diagram information (numerical information such as pair characteristics and resistance values) read from the circuit diagram and various information of each semiconductor element in the block shown in FIG. ing.

The model name is a name given to an actual circuit diagram, and the master cell name is a cell pattern name. The cell pattern indicates a resistance value and a capacitance value of the element as a value, and indicates whether each element can be trimmed, and, if it can be trimmed, how much the element can be trimmed as a minimum value, and a size adjustable range thereof. ing. In addition, the maximum number of combined elements is indicated as to which of the round-off, round-up, and round-off methods is used as the permissible error and the method of rounding the permissible error.

With this table, the conditions of the calculation process are determined and the design speed is increased.

For example, if a resistor is used as an element, the value of the element (resistance) defined in the circuit diagram is selected and synthesized by selecting how many elements (resistances), or the above table is added as a condition. Is processed. Here, the case of the capacitor is also realized in consideration of the similar connection.

The present invention has a feature here. First, it is determined whether an element (resistance) can be trimmed or not.
This is determined from the table shown in FIG.

If trimming is not possible, the number of selected modes in the following six modes is calculated, and the mode that minimizes the number of selected modes is selected. Series connection Series connection and surplus value are realized in parallel.Series and series are connected in parallel.Parallel and series are connected in parallel.Parallel connection Parallel and parallel are connected in series. The number of base cells to be adopted is determined by dividing by the resistance value of the base cell, and the remainder of the resistance value generated in this calculation is calculated by how many base cells can be connected in parallel.

It is needless to say that the use of a larger base cell reduces the number of composite cells.

Subsequently, when trimming is possible, calculation processing is performed in two modes.

In the present invention, at the time of the trimming process, the minimum value information of the adjustment width stored in the table of FIG. 1 has an important meaning. That is, a specific example of automatically synthesizing a resistance of 1.02 KΩ using the example of the master cell name “low resistance 1” in FIG. 1 will be described.

First, the resistor having the master cell name "low resistance 1" is a trimmable element as a matter of course, and its size adjustable range is from 500 Ω to 1 KΩ.

Here, how to make 1.02 KΩ is, for example, as shown in FIG.
1KΩ, the same as the resistance (without trimming)
The resistance of 1.02 KΩ can be theoretically automatically synthesized by trimming the resistances of the above and forming a resistance of 0.02 KΩ and connecting them in series. Note that C1, C2, C
1 'and C2' indicate contact holes.

However, it is difficult to trim a 1 KΩ resistor to produce a 0.02 KΩ resistor due to process restrictions and the like, and even if it is forcibly produced, good characteristics cannot be obtained. That is, as shown in FIG. 2A, the contact holes C1 ', C
The 2's are too close to each other, making it impossible to produce a good resistance value.

Therefore, according to the present invention, when the remainder of the resistance value to be automatically synthesized is smaller than the minimum value, a plurality of semiconductor elements (here, resistors) are trimmed. That is, the minimum value of the resistance of the master cell name “low resistance 1” is 500Ω.
Therefore, a plurality of resistors are trimmed based on this 500Ω to automatically synthesize 1.02KΩ. Therefore, the computer trims the two resistors, one trimming to 500Ω and the other trimming to 5Ω, as shown in FIG.
Trim to 20Ω. Note that C11, C12, C1
1 ′ and C12 ′ indicate contact holes. And
By connecting these resistors in series, 1.02 KΩ can be automatically synthesized.

In the specific example described above, the resistance value (1.02 KΩ) which is larger than the resistance value of the base (1 KΩ in this case).
Ω), and is realized by connecting a plurality of resistors in series as a combination of resistors.

In the following specific example, a plurality of resistors are connected in parallel as a combination of resistors, and the resistance value of the ground (here, 1 KΩ)
An example in which a smaller resistance value (80Ω) is synthesized will be introduced.

In this case, the resistance which becomes smaller than the minimum trimming value is generated with an equal value.
As shown in FIG.
By making 7 Ω resistors and connecting them in parallel, 8
A resistance of 0Ω can be automatically synthesized.

Hereinafter, a method of automatically allocating a semiconductor integrated circuit device to which the present invention is applied will be described with reference to FIGS. In the following description, the case where the size adjustment of each semiconductor element is not performed is described. However, the same applies to the case where the size adjustment is performed, and automatic allocation is performed as described above.

FIG. 4 shows an example of the arrangement of elements generated when the present invention is not employed, based on the circuit diagram of FIG.
Shows an arrangement example when the present invention is adopted.

In both figures, 22 resistances of 1 kΩ are formed as a first resistance group from above with respect to the paper surface.
(Hereinafter referred to as Tr) groups, and 12 1 kΩ resistors are arranged as a second resistor group. However, this array is merely an example, and another array may be used.

In the method not employing the present invention shown in FIG.
Are 5 kΩ. In the first resistor group, five resistors are automatically selected from the left and connected in series. Further, in the circuit of FIG. 5, four Trs Q1 to Q4 are employed, so that up to four from the left are selected in the first Tr group. Further, the resistors R5 and R6 of FIG.
Is 3 kΩ, and three are selected from the left in the second resistor group, and each is connected in series.

When the elements are automatically selected in this manner, the elements are sequentially selected from the end (left end or right end) of the column, and thereafter, the wiring is automatically arranged.

However, with this structure, the balance of the wiring length of the entire circuit is deteriorated, noise enters from a portion having a long wiring length, and the pairing of circuit elements is lost, resulting in an operational characteristic. There was a problem that it became worse.

Particularly, in the case of an analog circuit, pairing is required particularly in a differential amplifier circuit, an Amp, a comparator, a waveform shaping circuit, and the like. For example, the resistors R1 and R2, R3 and R in FIG.
4, Q1 and Q2, and Q3 and Q4.

Accordingly, in view of the above problem, in the present invention, FIG.
After arranging the elements in a state or virtually arranging the elements, the wiring length is calculated, and the element is reselected at least once so that the wiring length is shortened in consideration of the pairing property. It is characterized by: In particular, here, the transistors Q1 and Q2 and the transistors Q3 and Q4 are arranged next to each other because of the need for pairing, and are rearranged so that the wiring length is shortened in the state where the transistors are arranged next to each other.

That is, as shown in FIG. 3, the positions of the resistors R1 and R2 are fixed at Q1 and Q2 because the length of the row of the resistors R1 and R2 is long. Therefore, the positions of the first to the tenth resistors from the left in the first resistor group are fixed, and a pair of Trs (Q1 and Q2) adjacent to each other is adjusted during this period. In other words, Tr (Q1 and Q
2) is reselected.

Then, the second resistor group is selected again so that the connection wiring I to the second resistor group is at the shortest distance with respect to the fixed Q1 and Q2. That is, the third to fifth resistors from the left of the second resistor group are reselected so as to form the resistor R5.

Similarly, in Q3 and Q4, resistors R3 and R4
Are long, the positions of the resistors R3 and R4 are fixed. Accordingly, the first resistor group, the resistors between the eleventh and twentieth from the left, have their positions fixed, and
The pair of Trs (Q3 and Q4) in the adjacent state is adjusted. That is, the wirings CG and DH are taken
Tr (Q3 and Q4) are reselected so that is shortest.

Then, the second resistor group is selected again so that the connection wiring J to the second resistor group is at the shortest distance with respect to the fixed Q3 and Q4. That is, the first to third resistors from the right of the second resistor group are reselected to form the resistor R6.

The wiring length is calculated by recognizing the hatched portion in FIG. That is, an area (port) indicated by oblique lines is defined on a base (mask information etc.) indicated by a solid line,
This port is recognized by the computer, and the port is automatically selected so that the distance (fly line) connected by a straight line becomes shorter. (A), (b), (c), (d),
(E) is a block diagram of a basic circuit such as a capacitor, a resistor, a transistor, a pad, an Amp, and a logic circuit. In this block, input / output terminals and the like are arranged as ports.

Subsequently, the synthesis of the elements will be described. In FIG. 5, the resistance values are indicated by good numbers such as 5k and 3k, but actually there are fractions.

When the computer sets the allowable error strictly, the computer calculates as instructed. Therefore, in order to approach the numerical value as much as possible, the number of synthesized elements becomes enormous, and the calculation time becomes enormous. Therefore, the calculation is performed under the conditions as shown in FIG. The computer controls the rearrangement based on the electronic circuit pattern information (numerical information such as pairing and resistance values) read from the circuit diagram and the various information of each semiconductor element in the block shown in FIG. ing. Note that the calculation method under the conditions of FIG. 1 has already been described above, and will be omitted to avoid redundant description.

A series of design methods will be described with reference to FIG.

First, in "generation of base information table", base information of a master cell in an area where elements are arranged is generated in a table.

The “generation of allocation table” is to generate information such as which element to select from the X-axis or the Y-axis in consideration of pairing of a circuit to be realized.

Subsequently, in the "synthesis process", as described above,
The number of selected master cells is minimized, and a composite pattern of each element is generated. At this time, in the synthesis of the elements for which the pairing property is specified, they are configured as the same pattern.
For example, when three 1 KΩ resistors are connected in series to form 3 KΩ resistors in pairs, they are configured in the same pattern.

Subsequently, in the "transistor arrangement", the arrangement position, the orientation, and the like of the transistor are determined.

After this, the resistors are normally placed, but here, the process of “initial placement” and “placement improvement” is started. In the initial arrangement, arrangement is performed from the lower left corner of the block and the arrangement is performed along the circuit diagram. For an element generated by the synthesis processing, an optimal place suitable for the synthesis pattern is selected. After the initial arrangement, “arrangement improvement” is performed. The arrangement improvement is a process in which data processing is performed so that wiring is shortened, and the TR is reselected to a non-selected TR if necessary.

Subsequently, a resistor R is arranged. Also here, if necessary, a non-selected transistor and a resistor are replaced with a non-selected transistor and a resistor, if necessary, so that the wiring length between TR and the resistor R is shortened.

Subsequently, the capacitance is arranged, and finally, the fly line improvement of the resistance is performed.

Here, the selected master cell (resistor)
Is adjusted so that the length of the wiring is shortened by adjusting the position of the terminal in contact with the wiring.

Next, a specific example will be described with reference to FIGS.

Generally, in the semiconductor chip 20, as shown in FIG. 6, the area surrounded by the bonding pads 21 is, for example, a plurality of block rows (here, three rows BL on the left and right sides).
1, BL2, BL3), and each block row is divided into a plurality of blocks. For example, the first block row BL1 includes blocks 1 to 10, and the second block row BL2 includes blocks 11 to 20.
The third block column BL3 includes blocks 21 to 30.

Each of the blocks 1 to 30 comprises a basic unit cell UC as shown in an enlarged view (lower view in FIG. 6) indicated by an arrow. The unit cells UC are formed in groups so that the circuit diagram shown in the left diagram of FIG. 7 can be selected.

That is, a plurality of types of resistors having different values are selected, and each is arranged in a group. This is the same for the transistor Tr and the capacitor. In particular, Tr
In the figure, vertical and horizontal PNP-Tr, vertical NPN-T
The three types of r are arranged in groups. The way of arranging the block rows and the number of arrays are merely examples,
However, it is not limited to this. A diode or the like may be provided in addition to the resistors, Trs, and capacitors, which are the elements in the block.

Furthermore, each element has a different size (resistors have different resistance values, Tr has different current capacities, and capacitors have different capacities). The elements are arranged in groups.

In some cases, a protection diode or the like is formed under the bonding pad. However, it is ignored here because it is extremely small in view of the ratio of the number of elements. Power pads, bonding pads 21.
At least one ground pad is formed.

First, a plurality of electronic circuit blocks are prepared in the semiconductor chip 20 shown in FIG. 3 as shown in FIG.
A C circuit is realized. Each electronic circuit block is configured by selecting elements in the block according to the circuit diagram,
It is composed of at least one block.

FIG. 8 shows, for example, Tr in a target circuit diagram.
And a state in which the resistor is selected, and is again computer-processed so that the wiring between the Tr and the resistor is minimized. That is, the first to fourth resistors from the left are selected in series connection, and the fifth to eighth resistors are also selected in series connection from the left. Here, the connection wirings to the second Tr row and the first resistor row are arranged on the left side as a whole because the left element in each element row is selected, and the balance is broken. I understand.

FIG. 7 shows the result of computer processing by applying the present invention and reselection of Tr. The transistors are reselected from the state in which the first and second Trs from the left shown in FIG. 8 are selected to the second and fourth Trs from the left in FIG. 7, and the resistance is also changed to the left as shown in FIG. First to
Although the fourth resistor is taken in order, in FIG. 7, it is reselected in the reverse direction from the fourth to the first. Therefore, processing is performed so that the wiring length is shortened while maintaining the pairing property by being reselected.

As described above, the circuit pattern is drawn along the circuit diagram.

Generally, in order to select an element, a contact hole for wiring is opened, but a wafer in a stage before the contact hole is opened is prepared. For example, in the case of a bipolar type, there are two types: a type in which a contact hole is opened and a metal is formed in a state where all the diffusion regions are formed; and a type in which a contact hole is formed and then emitter diffusion or emitter ion implantation is performed. Divided into streets.

In any case, the wafer before the contact holes are formed is prepared, and the contact holes of the elements previously selected by the computer and the wiring pattern generated by the computer are prepared as a photomask.

Then, a contact hole is opened in the semiconductor wafer using a photomask for contact holes, and wiring is performed via the photomask for wiring.

Of course, in the type in which the impurity is introduced after the contact hole is opened, the impurity is introduced via the ion implantation mask before the wiring is formed.

As described above, since the pattern design time by the computer is shortened and elements are reselected so that the wiring pattern is shortened, a semiconductor integrated circuit having a structure in which noise is hardly penetrated is provided to the user in a short delivery time. Can supply.

There are also the following merits. Conventionally, when a circuit designer instructs a pattern designer to use, for example, 1.02 KΩ as a resistor, while the pattern designer replies that this resistance cannot be realized due to the complexity of pattern synthesis, The user has to use another resistance value in a compromised manner and redesign the circuit. However, in the present invention, since the synthesis of the elements is computerized, the inconvenience of not being able to use 1.02 KΩ is eliminated, and the circuit designer can exchange information with the pattern designer without compromising the above-mentioned conditions. This makes it possible to design a circuit with high performance in a short time.

[0079]

According to the present invention, when each semiconductor element prepared in a block is automatically selected sequentially and automatically allocated by a computer so as to form a desired electronic circuit, the semiconductor element is stored in the computer. Since the size-adjustable semiconductor elements are automatically synthesized based on the size adjustment enable / disable information and the size-adjustable range information regarding the semiconductor elements, the accuracy of the automatic synthesis can be increased.

When the size adjustment value of the semiconductor element to be automatically synthesized is smaller than the minimum value stored in the size adjustable range information, the plurality of semiconductor elements are adjusted in size and each semiconductor element is connected. By doing so, automatic synthesis can be realized with high accuracy and with the minimum number of wires.

In addition, conventionally, the size adjustment processing has been performed manually, but by applying the present invention and processing these under predetermined conditions, the images can be automatically synthesized by a computer, and the design time can be reduced. it can.

[Brief description of the drawings]

FIG. 1 is a diagram for describing conditions when performing arithmetic processing on size-adjustable information and the like.

FIG. 2 is a diagram illustrating a method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor integrated circuit to which the present invention is applied.

FIG. 4 is a diagram illustrating a conventional method for manufacturing a semiconductor integrated circuit.

FIG. 5 is a diagram illustrating an example of a circuit diagram accommodated in a block.

FIG. 6 is a diagram illustrating a configuration of a semiconductor integrated circuit.

FIG. 7 is a diagram illustrating an example of selecting elements in the block of FIG. 6;

FIG. 8 is a diagram illustrating an example of selecting elements in the block of FIG. 6;

FIG. 9 is a diagram showing a flowchart relating to automatic allocation.

FIG. 10 is a diagram illustrating ports allocated to elements in a block.

FIG. 11 is a diagram illustrating a conventional method of manufacturing a semiconductor integrated circuit.

FIG. 12 is a diagram illustrating a conventional method for manufacturing a semiconductor integrated circuit.

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit in which each semiconductor element prepared in a block is automatically selected sequentially and automatically allocated by a computer so as to form a desired electronic circuit. A method for automatically synthesizing a size-adjustable semiconductor element based on size adjustment availability information and size-adjustable range information on the semiconductor element. 2. The size-adjustable range information stores at least information on the minimum value of the size of each semiconductor element that can be adjusted, and the computer adjusts the size of the semiconductor element and automatically adjusts the size adjustment value of the semiconductor element. 2. The method according to claim 1, wherein when the value is smaller than the minimum value, the plurality of semiconductor elements are adjusted in size and the respective semiconductor elements are connected to each other. 3. The method according to claim 1, wherein the electronic circuit is a linear circuit. 4. The method according to claim 3, wherein the linear circuit is a bipolar electronic circuit.