JPH05114717A - Mos gate array - Google Patents

Abstract

PURPOSE:To provide a MOS gate array on which an EPROM can be mounted as a multifunctioning material and also a high resistance load type SRAM can be formed in high integration. CONSTITUTION:The gate electrode of transistors Q1 and Q2 are constructed in two-layer polysilicon structure, the first layer of polysilicon (1st poly) is used as floating gates 31 and 32, the second layer of polysilicon (2nd poly) is used as word lines k21 and 122, and as a result, an EPROM can be mounted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS gate array, and more particularly to a MOS gate array capable of mounting a large capacity memory.

[0002]

2. Description of the Related Art As shown in FIG.
Two transistors Q ₁ and Q sharing one diffusion layer 61
₂ are arranged in an array, and a contact hole is formed at a position marked with X in the figure, and wiring is connected to form a circuit. Recently, it is general to use a CMOS configuration for the gate array, which is an n-channel transistor and a p-channel transistor.
Rows of channel type transistors are often arranged alternately.

[0003]

However, in the conventional MOS gate array, one layer of polysilicon is used as a gate electrode of a transistor, and by connecting this with a multilayer wiring, a logic circuit, a CMOS SRAM, a mask ROM, or the like. However, since the polysilicon has only one layer, the EPROM cannot be formed, which hinders the multifunctionalization.

Therefore, according to the present invention, an EPROM can be mounted as one of multi-functionalization, and a high resistance load type SR is provided.
An object is to provide a MOS gate array capable of forming an AM with high integration.

[0005]

In order to achieve the above object, a MOS gate array according to the present invention has a gate electrode having a two-layer polysilicon structure and uses the first-layer polysilicon as a floating gate. It has a structure in which an EPROM having a structure using polysilicon of the layer as a word line is mounted. Further, the MOS gate array according to the present invention has a structure in which a SRAM having a structure in which a partial region of the second layer polysilicon is used as a high resistance region and which is used as a load is mounted.

[0006]

In the MOS gate array according to the present invention, the gate electrode of the transistor has a two-layer polysilicon structure,
An EPROM can be mounted by using the first-layer polysilicon as a floating gate and the second-layer polysilicon as a word line. Furthermore, by using a partial region of the second-layer polysilicon as a high resistance region and using this as a load, the SRAM can be mounted with high integration.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a pattern diagram showing an embodiment of the present invention, and FIG. 2 is a sectional view (A) and B- of FIG.
FIG. 9 is a sectional view (B) taken along the arrow B. In the figure, on the surface of the silicon substrate 1, the floating gate 3 ₁ , is formed by the first layer of polysilicon (1poly) through the oxide film (SiO ₂ ) 2.
3 ₂ are formed and these floating gates 3 ₁ , 3
₂ on the further control gate 5 via an interlayer insulating film 4 by a second layer of polysilicon (2poly) _1, 5 ₂
Are formed in the same pattern as the first layer of polysilicon (1poly).

[0008] surface of the silicon substrate 1, floating gate 3 _1, 3 a source region 6 consisting of N ⁺ impurity region between _2, floating gates 3 _1, 3 ₂ of the drain region made of outside N ⁺ impurity region 7 ₁ and 7 ₂ are formed respectively, and thus 2 sharing a single diffusion layer 8
Two transistors Q ₁ and Q ₂ are arranged in an array.

The drain region 7 ₂ of the diffusion layer 8 is shown in FIG.
As shown in (A), a contact hole formed in the portion marked with a circle in FIG. 1 is formed in the bit line 9 _{2 of} Bit2 formed of the first layer aluminum (hereinafter simply referred to as aluminum) wiring (1Al). Contact is made through. Similarly, the drain region 7 ₁ is in contact with the bit line 9 _{1 of} Bit2. On the other hand, the source region 6 is the aluminum wiring of the first layer.
The Vss power supply line 10 made of (1Al) is contacted through a contact hole formed in a portion marked with a circle in FIG. 1, and is grounded through the Vss power supply line 10.

As shown in FIG. 2B, the control gate 5 _{2 made} of the second layer of polysilicon (2poly) is used.
Is contacted with the Al region 11 ₂ of the first layer through a contact hole formed in the portion marked with ● in FIG.
Furthermore these Al region 11 _2, the word line 12 of Word2 through a contact hole formed in □ mark portion of FIG. 1
Contacted with ₂ . Control gate 5
₁ have also been taken word line 12 ₁ and the contact as well. As a result, the control gates 5 ₁ and 5 ₂ are connected to the word lines 12 ₁ and 12 ₂ and act as word lines. FIG. 3 shows the equivalent circuit.

As described above, the gate electrodes of the transistors Q ₁ and Q ₂ have a two-layer polysilicon structure, and the floating gates 3 ₁ and 3 are made of the first layer polysilicon (1poly).
By forming ₂ and using the second layer of polysilicon (2poly) as the word line, the EPROM can be mounted as one of the multi-functionalizations required today.

Further, as is apparent from FIG. 2 (B), 2
The structure is such that the floating gate 3 ₂ made of the first-layer polysilicon (1poly) is always present under the control gate 52 made of the _second- layer polysilicon (2poly). Since the patterns can be formed at the same time, the misalignment of the patterns of each layer can be eliminated, and the deterioration of the application range of 1Al in the 2poly contact portion can be prevented.

FIG. 4 is a pattern diagram showing another embodiment of the present invention, which is applied to the memory cell using the high resistance load type SRAM shown in FIG. In FIG. 4, 1
A layer th polysilicon (1poly) four gate electrodes of the transistors Q ₁ to Q ₄ are formed, the two transistors Q ₃ of these transistors Q ₁ to Q _4, Q
The gate electrode of _{4 has} the same pattern as the second layer of polysilicon (2poly) on the first layer of polysilicon (1poly).
Has a two-layer polysilicon structure formed by being insulated.

In the transistors Q ₃ and Q _{4 having the} two-layer polysilicon structure, a partial region (hatched region in the figure) of the second-layer polysilicon (2poly) is a high resistance region,
This high resistance region is used as the load resistances R ₁ and R ₂ in FIG. In Fig. 4, the alternate long and short dash line indicates the aluminum wiring (1
Al) and the chain double-dashed line represent the second layer aluminum wiring (2Al), respectively. The first layer aluminum wiring (1Al) is the bit lines B ₁ and B ₂ , the power source lines V _DD and V _SS, and the contact wiring between the layers, and the second layer aluminum wiring (2Al) is the word lines W and the respective layers. Used as contact wiring between layers.

In FIG. 4, the large and small □ marks are contact parts, and the small □ contact parts C _a are aluminum wiring (1Al) of the first layer and polysilicon (1) of the first and second layers. , 2po
ly) and the diffusion layer, and the contact portion C _b marked with a large □ is a contact portion for making contact between the first layer aluminum wiring (1Al) and the second layer aluminum wiring (2Al). Is.

That is, the base electrodes (1poly) of the transistors Q ₁ and Q ₂ are _{1 at} the contact portions C _a1 and C _a2 , respectively.
Contact was made with the aluminum wiring (1Al) in the first layer.
By layers th aluminum wiring (1Al) the contact is taken as the second-layer aluminum wiring in the contact portion C _b1 (2Al), is connected to the word line W (2Al). Transistors Q ₁ and Q
The source regions of the _2, contact the bit line (1Al) B _1, the B ₂ are respectively taken in the contact portion C _a3, C _a4.

The drain region of the transistor Q ₁ is contacted with the aluminum wiring (1Al) of the first layer at the contact portion C _a5 , and the aluminum wiring (1Al) of the first layer is contacted with the two-layer poly wiring at the contact portion C _a6. By making contact with each layer of the silicon structure, the base electrode (1poly) of transistor Q ₄
And a resistor R _{1 formed} of a high resistance region (2poly), respectively. Also, the first layer of aluminum wiring (1Al)
Is contacted with the second layer aluminum wiring (2Al) at the contact portion C _b2 , and the second layer aluminum wiring (2Al) is contacted with the first layer aluminum wiring (1Al) at the contact portion C _b3. Further, the aluminum wiring (1Al) of the first layer is brought into contact with the drain region of the transistor Q ₃ at the contact portion C _a7 , whereby the drain regions of the transistors Q ₁ and Q ₃ are commonly connected.

On the other hand, the drain region of the transistor Q ₂ is contacted with the first-layer aluminum wiring (1Al) at the contact portion C _a8 , and the first-layer aluminum wiring (1Al) is contacted with the contact portion C _a9 . By making contact with the first layer of the layer polysilicon structure, it is connected to the base electrode (1poly) of the transistor Q ₃ and this base electrode (1po
ly) is the contact part C _a10 and the first layer of aluminum wiring (1Al)
Is connected to one end of a resistor R ₂ composed of a high resistance region (2poly). Further, since the first-layer aluminum wiring (1Al) is in contact with the drain region of the transistor Q ₄ at the contact portion C _a11 , the transistors Q ₂ , Q _{2 are connected} .
The drain regions of ₄ are commonly connected.

The other end of the resistor R ₁ is the second layer of polysilicon.
(2poly) is the contact part C _a12 and the first layer aluminum wiring (1
It is connected to the power supply line V _DD by making contact with Al). On the other hand, at the other end of the resistor R ₂ , the second-layer polysilicon (2poly) is contacted with the first-layer aluminum wiring (1Al) at the contact portion C _a13 , and the first-layer aluminum wiring (1Al) is formed. Is the contact layer C _b4 and the second layer of aluminum wiring (2
Al) and a contact is taken, further the second layer aluminum wiring (2Al) is a contact portion C _b5 in the first layer aluminum wiring (1
It is connected to the power supply line V _DD by making contact with Al). Further, the source regions of the transistors Q ₃ and Q ₄ are contacted with the aluminum wiring (1Al) of the first layer at the contact portions C _a14 and C _a15 , so that the power supply line V _{CC is obtained.}
It is connected to the.

As is apparent from the above, in the MOS gate array, the gate electrode of the transistor is a two-layer polysilicon structure, and a partial region of the second layer polysilicon (2poly) is a high resistance region, which is used as a load resistance. By using R ₁ and R ₂ , the SRAM can be mounted with high integration.

As described above, if this cell is used, EP
Although ROM or SRAM can be formed, when these memories are not formed, the conventional cell shown in FIG. 6 can be applied without changing the cell area and wiring flexibility.

[0022]

As described above, according to the present invention,
As the gate electrode of the transistor has a two-layer polysilicon structure and the first-layer polysilicon is used as a floating gate and the second-layer polysilicon is used as a word line, an EPROM can be mounted as one of the multifunctional features. A high resistance load type SRAM can be formed with a high degree of integration by using a part of the second-layer polysilicon as a high resistance region and using it as a load.

[Brief description of drawings]

FIG. 1 is a pattern diagram of an embodiment of the present invention.

FIG. 2 is a sectional structural view of an embodiment of the present invention, (A)
1 is a cross-sectional structure taken along the line AA in FIG. 1, and (B) is BB
The cross-sectional structure taken along the arrow is shown.

FIG. 3 is an equivalent circuit diagram of an embodiment of the present invention.

FIG. 4 is a pattern diagram of another embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of another embodiment of the present invention.

FIG. 6 is a cell pattern diagram of a conventional example.

[Explanation of symbols]

1 Silicon substrate 3 ₁ , 3 ₂ Floating gate 5 ₁ , 5 ₂ Control gate 6 Source region 7 ₁ , 7 ₂ Drain region 8 Diffusion layer 9 ₁ , 9 ₂ Bit line 12 ₁ , 12 ₂ Word line

[Procedure amendment]

[Submission date] January 10, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art As shown in FIG. 6, a gate array has two transistors Q ₁ and Q ₂ sharing a source region 61.
Are arranged in an array, contact holes are formed at the positions marked with X in the figure, and wiring is connected to form a circuit. In recent years, it is general that the gate array has a CMOS structure, and columns of n-channel transistors and P-channel transistors are often arranged alternately.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a pattern diagram showing an embodiment of the present invention, and FIG. 2 is a sectional view (A) and B- of FIG.
FIG. 9 is a sectional view (B) taken along the arrow B. In the figure, a floating gate 3 ₁ 3 ₂ is formed on the surface of a silicon substrate 1 with a first layer of polysilicon (1 poly) via an oxide film (SiO ₂ ) 2 and these floating gates 3 ₁ , 3 ₂ are formed. further on, the interlayer insulating film 4 control gates 5 ₁ by second polysilicon layer over the _(2poly), 5 ₂ polysilicon in the first layer except a region and its vicinity to form a contact hole (1 pol
y) and the same pattern.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

[0008] surface of the silicon substrate 1, floating gate ₃ 1, ₃ a source region 6 consisting of ^{N +} impurity region between _2, floating gates ₃ 1, _{3 2} of the drain region made of outside ^{N +} impurity region 7 ₁ and 7 ₂ are formed respectively, so that two transistors Q ₁ and Q ₂ sharing one source region 6 are arranged in an array.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

[0009] The drain region _{7 2} of the active region 8, FIG. 2
As shown in (A), a Bit 2 formed of a first-layer aluminum (hereinafter simply referred to as aluminum) wiring (1Al)
Of the bit line 9 _2, it is taken the contact via a contact hole formed in part in FIG. 1 ○ mark. Similarly, the drain region 7 _{1 is} also in contact with the bit line 9 _{1 of} Bit1. On the other hand, the source region 6 is connected to the Vss power supply line 10 made of the first layer aluminum wiring (1Al),
A contact is made through a contact hole formed in a portion marked with a circle in FIG. 1, and is grounded through the Vss power supply line 10.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

In the transistors Q ₃ and Q _{4 having} the two-layer polysilicon structure, the second-layer polysilicon (2pol) is used.
Part of y) is a high resistance region (region with dotted points in the figure), and this high resistance region is the load resistance R _{1 of} FIG.
Used as R ₂ . In FIG. 4, the one-dot chain line represents the first-layer aluminum wiring (1Al), and the two-dot chain line represents the second-layer aluminum wiring (2Al). The first layer aluminum wiring (1Al) is used as the bit lines B ₁ and B ₂ , the power supply lines V _DD and V _SS, and the contact wiring between the layers 2
The aluminum wiring of the second layer (2Al) is used as the word line W and the contact wiring between the respective layers.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

That is, the gate electrodes (1poly) of the transistors Q ₁ and Q ₂ have contact portions C _a1 and C 2 respectively.
_a2 each first-layer aluminum wiring and (1Al) contact is taken in, by contact with the first layer aluminum wiring (1Al) is a second-layer aluminum wiring in the contact portion _{C b1} (2Al) is taken , Word line W (2Al). The source regions of the transistors Q ₁ and Q ₂ are
Bit line (1Al) at contact portions C _a3 and C _a4
Contact is made to each of B ₁ and B ₂ .

[Procedure Amendment 7]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

[Procedure Amendment 8]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

[Procedure Amendment 9]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location H01L 29/792 H01L 29/78 371

Claims (2)

[Claims] 1. An EPROM having a two-layer polysilicon structure gate electrode, wherein the first-layer polysilicon is used as a floating gate and the second-layer polysilicon is used as a word line is mounted. And a MOS gate array. 2. An SRAM having a gate electrode having a two-layer polysilicon structure, and having a structure in which a partial region of the second-layer polysilicon is used as a high resistance region and which is used as a load is mounted. MOS gate array.