JPH05110106A - Structure of mosfet chip - Google Patents
Structure of mosfet chipInfo
- Publication number
- JPH05110106A JPH05110106A JP3268021A JP26802191A JPH05110106A JP H05110106 A JPH05110106 A JP H05110106A JP 3268021 A JP3268021 A JP 3268021A JP 26802191 A JP26802191 A JP 26802191A JP H05110106 A JPH05110106 A JP H05110106A
- Authority
- JP
- Japan
- Prior art keywords
- source electrode
- oxide film
- chip
- metal layer
- case
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】パワーハイブリッドＩＣ等に使用
されるパワー用ＭＯＳ ＦＥＴ（電界効果トランジス
タ）チップの構造に関し、特に放熱に適した構造に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a power MOS FET (field effect transistor) chip used in a power hybrid IC or the like, and particularly to a structure suitable for heat dissipation.
【０００２】[0002]
【従来の技術】パワーハイブリッドＩＣ（以下パワーＨ
ＩＣと記す）等に使用される従来のＭＯＳ ＦＥＴチッ
プ１は図２Ａに示すような構造であった。即ち、ｎ型の
半導体基板２の一面の所定の領域に絶縁性の酸化膜（例
えばＳｉＯ2）３が形成され、他面にドレイン電極４が
形成される。酸化膜３中にはゲート電極５が埋込み形成
されている。半導体基板２の一面の他の領域及び酸化膜
３上にまたがってソース電極６が蒸着により形成され
る。なお図示していないが、ゲート電極５の一端は酸化
膜３より外部に露出されて、ボンディング用電極部とさ
れている（図２Ｂ参照）。2. Description of the Related Art Power hybrid ICs (hereinafter referred to as power H
The conventional MOS FET chip 1 used for IC) and the like has a structure as shown in FIG. 2A. That is, an insulating oxide film (eg, SiO 2 ) 3 is formed on a predetermined region of one surface of the n-type semiconductor substrate 2, and a drain electrode 4 is formed on the other surface. A gate electrode 5 is embedded in the oxide film 3. A source electrode 6 is formed by vapor deposition over the other region of the one surface of the semiconductor substrate 2 and the oxide film 3. Although not shown, one end of the gate electrode 5 is exposed to the outside through the oxide film 3 and serves as a bonding electrode portion (see FIG. 2B).
【０００３】半導体基板２は、ｎ型半導体ウエハの一面
側よりｐ型不純物が拡散されてＰ層２ａが半導体基板２
の上面側の一部に形成され、そのＰ層２ａの上面側より
更にｎ型不純物が拡散されて、ｎ+ 層２ｂがＰ層２ａに
囲まれて基板２の上面側に形成されている。ｎ+ 層２ｂ
の上面の半部はソース電極６と、他の半部は酸化膜３と
それぞれ対接される。半導体基板２のドレイン電極４と
対接する側にｎ+ 層２ｃ（なお＋，−の符号は不純物濃
度が大きいか小さいかを表す。）が、その内面にｎ- 層
２ｄが形成されている。このような構造のＭＯＳ ＦＥ
Ｔは２重拡散型ＭＯＳ ＦＥＴと言われ、よく知られた
ものであるので詳細な説明を省略する。In the semiconductor substrate 2, p-type impurities are diffused from one surface side of the n-type semiconductor wafer so that the P layer 2a is formed on the semiconductor substrate 2.
Is formed on a part of the upper surface side of the P layer 2a, the n type impurity is further diffused from the upper surface side of the P layer 2a, and the n + layer 2b is formed on the upper surface side of the substrate 2 surrounded by the P layer 2a. n + layer 2b
One half of the upper surface of the source electrode 6 is in contact with the source electrode 6, and the other half is in contact with the oxide film 3. An n + layer 2c (note that + and − signs indicate high or low impurity concentration) is formed on the side of the semiconductor substrate 2 that is in contact with the drain electrode 4, and an n − layer 2d is formed on the inner surface thereof. MOS FE with such a structure
T is said to be a double diffusion type MOS FET and is well known, so a detailed description thereof will be omitted.
【０００４】このように構成されたＭＯＳ ＦＥＴチッ
プ１は、そのドレイン電極４がパワーＨＩＣ７のセラミ
ック基板８上の導体パターンにボンディングされ、また
ゲート電極５及びソース電極６がボンディングワイヤ９
又は１０を介してセラミック基板８上の対応する導体パ
ターンにそれぞれボンディングされる。セラミック基板
８には一般にその他の回路素子も実装されるが図示して
いない。これら回路素子を実装したセラミック基板１２
はセラミック、プラスチック等より成るケース１１内に
収容、保持されてパワーＨＩＣ７が構成される。In the MOS FET chip 1 thus constructed, the drain electrode 4 is bonded to the conductor pattern on the ceramic substrate 8 of the power HIC 7, and the gate electrode 5 and the source electrode 6 are bonded to the bonding wire 9.
Alternatively, they are bonded to the corresponding conductor patterns on the ceramic substrate 8 via 10 respectively. Although other circuit elements are generally mounted on the ceramic substrate 8, they are not shown. Ceramic substrate 12 on which these circuit elements are mounted
Is housed and held in a case 11 made of ceramic, plastic or the like to form a power HIC 7.
【０００５】パワーＨＩＣ７に組み込まれたＭＯＳ Ｆ
ＥＴチップ１の放熱経路は、ドレイン電極４−セラミッ
ク基板８−ケース１１−外部に至る第１の経路と、ソー
ス電極６−ボンディングワイヤ１０−セラミック基板８
−ケース１１−外部に至る第２の経路と、ゲート電極５
−ボンディングワイヤ９−セラミック基板８−ケース１
１−外部に至る第３の経路とが存在する。MOS F incorporated in power HIC 7
The heat dissipation route of the ET chip 1 is the drain electrode 4-ceramic substrate 8-the case 11-the first route to the outside, the source electrode 6-the bonding wire 10-the ceramic substrate 8.
-Case 11-The second path to the outside and the gate electrode 5
-Bonding wire 9-Ceramic substrate 8-Case 1
1-the third path to the outside.
【０００６】[0006]
【発明が解決しようとする課題】従来のパワーＨＩＣで
は、ＭＯＳ ＦＥＴチップの放熱が不充分のため、同チ
ップの温度が上昇し、電気的性能が低下するのみなら
ず、パワーＨＩＣの温度も上昇し、その電気的性能や寿
命に悪影響を与える恐れがあった。この発明の目的は従
来のものより放熱量が大きく、パワーＨＩＣ用に好適な
パワーＭＯＳ ＦＥＴチップの構造を提供しようとする
ものである。In the conventional power HIC, since the heat dissipation of the MOS FET chip is insufficient, not only the temperature of the chip rises and the electrical performance deteriorates, but also the temperature of the power HIC rises. However, there is a risk that the electrical performance and the life of the product may be adversely affected. An object of the present invention is to provide a structure of a power MOS FET chip which has a larger heat radiation amount than the conventional one and is suitable for a power HIC.
【０００７】[0007]
【課題を解決するための手段】（１） 請求項１の発明
では、ソース電極の近傍に、そのソース電極と絶縁され
て放熱用金属層が形成される。 （２） 請求項２の発明は、上記（１）項の内でも特
に、半導体基板の一面の所定の領域に絶縁性の酸化膜
が、他面にドレイン電極がそれぞれ形成され、前記酸化
膜中にゲート電極が埋込み形成され、前記半導体基板の
前記一面の他の領域及び前記酸化膜上にまたがってソー
ス電極が形成されて成るＭＯＳ ＦＥＴチップの構造に
関するものであって、前記酸化膜上に放熱用金属層が、
前記ソース電極と絶縁されて形成される。Means for Solving the Problems (1) In the invention of claim 1, a heat dissipation metal layer is formed in the vicinity of the source electrode and insulated from the source electrode. (2) The invention according to claim 2 is, in particular within the above (1), in which an insulating oxide film is formed on a predetermined region of one surface of the semiconductor substrate and a drain electrode is formed on the other surface of the semiconductor substrate. The present invention relates to a structure of a MOS FET chip in which a gate electrode is buried and formed, and a source electrode is formed over the other region of the one surface of the semiconductor substrate and the oxide film. The metal layer for
It is formed to be insulated from the source electrode.
【０００８】[0008]
【実施例】この発明では、図１Ａに示すように、酸化膜
３上にソース電極６を蒸着する際、一部をマスキングす
ることによって、ソース電極６とは絶縁された放熱用金
属層１４が形成される。放熱用金属層１４とソース電極
６との間にはマスキングによって空隙１５が形成され、
この空隙により互いに絶縁される。EXAMPLE In the present invention, as shown in FIG. 1A, when the source electrode 6 is vapor-deposited on the oxide film 3, by masking a part of the source electrode 6, a heat-radiating metal layer 14 insulated from the source electrode 6 is formed. It is formed. A space 15 is formed between the heat dissipation metal layer 14 and the source electrode 6 by masking,
The voids insulate one another.
【０００９】この発明のＭＯＳ ＦＥＴチップを実装し
たセラミック基板８をパワーＨＩＣ７のケース１１内に
収容する場合には、図１Ｂに示すように、放熱用金属層
１４とケース１１の内面とがアルミ等の太線ワイヤ１５
でボンディングされる。これにより従来の技術で述べた
第１乃至第３の放熱経路に加えて、放熱用金属層１４−
太線ワイヤ１５−ケース１１−外部に至る第４の放熱経
路が形成され、放熱容量の大幅な増加が図られる。When the ceramic substrate 8 on which the MOS FET chip of the present invention is mounted is housed in the case 11 of the power HIC 7, as shown in FIG. 1B, the heat dissipation metal layer 14 and the inner surface of the case 11 are made of aluminum or the like. Thick wire 15
Bonded with. As a result, in addition to the first to third heat dissipation paths described in the related art, the heat dissipation metal layer 14-
A fourth heat dissipation path extending from the thick wire 15 to the case 11 to the outside is formed, and the heat dissipation capacity is significantly increased.
【００１０】[0010]
【発明の効果】この発明によれば、ＭＯＳ ＦＥＴチッ
プ１の近傍にそのソース電極６とは絶縁されて放熱用金
属層１４が形成されている。同チップ１を実装したセラ
ミック基板８をパワーＨＩＣのケース１１内に収容する
場合、この放熱用金属層１４とケース１１の内面とを太
線ワイヤ１５でボンディングすることによって新たな放
熱経路を形成できる。これにより放熱容量の大幅な増加
が図られる。According to the present invention, the heat radiation metal layer 14 is formed in the vicinity of the MOS FET chip 1 so as to be insulated from the source electrode 6. When the ceramic substrate 8 on which the chip 1 is mounted is housed in the case 11 of the power HIC, a new heat dissipation path can be formed by bonding the heat dissipation metal layer 14 and the inner surface of the case 11 with the thick wire 15. As a result, the heat dissipation capacity can be significantly increased.
【００１１】従ってこの発明によれば、従来のものより
ＭＯＳ ＦＥＴチップ自身の温度上昇を低く押えて、Ｆ
ＥＴの電気的性能の低下を防止できると共に、ＨＩＣの
温度上昇も従来より小さくなるので、その電気的性能の
温度による劣化や寿命の低下を同時に改善できる。Therefore, according to the present invention, the temperature rise of the MOS FET chip itself can be suppressed lower than that of the conventional one, and F
The deterioration of the electrical performance of the ET can be prevented, and the temperature rise of the HIC is smaller than before, so that the deterioration of the electrical performance due to the temperature and the reduction of the life can be simultaneously improved.
【図１】Ａはこの発明の実施例を示す断面図、ＢはＡの
ＭＯＳ ＦＥＴチップを実装したパワーＨＩＣの断面
図。1A is a sectional view showing an embodiment of the present invention, and FIG. 1B is a sectional view of a power HIC on which a MOS FET chip of A is mounted.
【図２】Ａは従来のパワー用ＭＯＳ ＦＥＴチップの断
面図、ＢはＡのＭＯＳ ＦＥＴチップを実装したパワー
ＨＩＣの断面図。FIG. 2A is a sectional view of a conventional power MOS FET chip, and B is a sectional view of a power HIC on which the MOS FET chip of A is mounted.
Claims (2)
縁されて放熱用金属層が形成されているＭＯＳ ＦＥＴ
チップの構造。1. A MOS FET in which a metal layer for heat dissipation is formed near a source electrode and insulated from the source electrode.
Chip structure.
の酸化膜が、他面にドレイン電極がそれぞれ形成され、 前記酸化膜中にゲート電極が埋込み形成され、 前記半導体基板の前記一面の他の領域及び前記酸化膜上
にまたがってソース電極が形成されて成るＭＯＳ ＦＥ
Ｔチップの構造において、 前記酸化膜上に放熱用金属層が、形成されていることを
特徴とする請求項１記載のＭＯＳ ＦＥＴチップの構
造。2. An insulating oxide film is formed on a predetermined region of one surface of the semiconductor substrate, and a drain electrode is formed on the other surface of the semiconductor substrate, and a gate electrode is embedded in the oxide film. A MOS FE having a source electrode formed over the other region and the oxide film
The structure of a MOS FET chip according to claim 1, wherein in the structure of the T chip, a heat dissipation metal layer is formed on the oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3268021A JPH05110106A (en) | 1991-10-17 | 1991-10-17 | Structure of mosfet chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3268021A JPH05110106A (en) | 1991-10-17 | 1991-10-17 | Structure of mosfet chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05110106A true JPH05110106A (en) | 1993-04-30 |
Family
ID=17452795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3268021A Withdrawn JPH05110106A (en) | 1991-10-17 | 1991-10-17 | Structure of mosfet chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05110106A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010199206A (en) * | 2009-02-24 | 2010-09-09 | Nissan Motor Co Ltd | Semiconductor device |
-
1991
- 1991-10-17 JP JP3268021A patent/JPH05110106A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010199206A (en) * | 2009-02-24 | 2010-09-09 | Nissan Motor Co Ltd | Semiconductor device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990107 |