JP2003008006A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that is high in withstand voltage and to provide a method of manufacturing the device. SOLUTION: In the surface area of an N-type drain drift region 20, an N<+> - type drain region 17 and a P-type well region 18 surrounding an N<+> -type source region are formed. Near the well region 18, in addition, a polysilicon film 25 is provided as a gate electrode. Between the drain region 17 and well region 18, a first trench 21 filled up with a silicon oxide film 28 is arranged. In the trench 21, a plurality of second field plates 27 is arranged with the silicon oxide film 28 in between.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a high breakdown voltage and its manufacturing method.

[0002]

2. Description of the Related Art A lateral MOSFET (Metal Oxide) is used as a power device used in an industrial power switch or the like.
Semiconductor Field Effect Transistor), horizontal IG
BT (Insulated Gate Bipolar Transistor) and the like are used. Of these, the lateral MOSFET is formed from the front surface side of the semiconductor substrate using a planar diffusion technique,
It has a main current path in the horizontal (horizontal) direction of the main surface of the substrate.

Power transistors are used under high voltage and are required to have high withstand voltage characteristics. Furthermore, the power transistor for the power switch has high switching characteristics,
That is, low on-resistance is required.

In order to increase the breakdown voltage, a lateral MOSFET having a resurf structure has been developed. The RESURF structure is a structure in which a depletion layer extends laterally in a drift layer between a source and a drain to ensure a breakdown voltage when a reverse bias is applied to the source and the drain. When the RESURF structure is used, the breakdown voltage can be increased in a relatively small area as compared with a general semiconductor device having a planar structure.

Further, Japanese Patent Publication No. 63-50871 and Japanese Patent Laid-Open No. 5-190693 disclose a lateral MOSFET having a floating field plate (capacitively coupled field plate) structure in addition to the RESURF structure. In these lateral MOSFETs, in order to reduce the influence of the electric field balance in the RESURF portion (depletion layer forming portion) due to foreign ions or electric field generated by sealing resin or the like, a plurality of insulating MOSFETs are provided above the RESURF structure. Are provided, and these conductor layers are capacitively coupled to each other. Each conductor layer can be fixed to a voltage according to the capacitance ratio, the electric field concentration in the specific region of the resurf portion can be relaxed, and the breakdown voltage can be improved.

As described above, if the element structure in which the floating plate and the RESURF structure are combined is adopted,
The impurity concentration can be increased without lowering the withstand voltage characteristic of the drift layer. That is, it is possible to reduce the on-resistance while maintaining a high breakdown voltage.

[0007]

However, even if the above element structure is adopted, it is difficult to significantly improve the characteristics because the potential fixing by the floating plate is limited to only the surface of the element. That is, in the conventional device structure having the floating gate only on the device surface, it is not possible to sufficiently fix the potential to the deep portion of the drift region, and it is difficult to sufficiently improve the breakdown voltage while maintaining the low on-resistance. Met.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor device having a high breakdown voltage and a manufacturing method thereof. Another object of the present invention is to provide a semiconductor device having both low on-resistance and high breakdown voltage and a method for manufacturing the same.

[0009]

In order to achieve the above object, a semiconductor device according to a first aspect of the present invention is provided with a first semiconductor region set to a first potential and a space from the first semiconductor region. And the second potential that is set to the second potential
A third region that surrounds the semiconductor region, the first semiconductor region, and the second semiconductor region so that their surfaces are exposed to form a current path between the first semiconductor region and the second semiconductor region. A semiconductor layer, a third semiconductor region, a dielectric layer provided in a trench formed between the first semiconductor region and the second semiconductor region, and a predetermined dielectric layer provided inside the dielectric layer. And an internal field plate set to a potential of 1.

According to the above configuration, the first semiconductor region and the second semiconductor region
An internal field plate is provided inside the third semiconductor region that forms a current path with the semiconductor region. As a result, variations and concentration of the electric field in the current path are alleviated. As a result, a high breakdown voltage can be obtained while keeping the current path and the on-resistance of the semiconductor device low.

In order to achieve the above object, a semiconductor device according to a second aspect of the present invention is provided with a first conductivity type drift region formed on a semiconductor substrate, and island-shaped provided in the drift region. A first conductivity type drain region having an impurity concentration higher than that of the drift region and the drift region,
A second conductive type well region provided in an island shape apart from the drain region, a first conductive type source region provided in an island shape in the well region, the source region and the A gate electrode provided via an insulating film on at least a part of the well region sandwiched between a drift region and a trench formed between the drain region and the source region in the drift region. It is characterized by comprising a dielectric layer provided and an internal field plate provided inside the dielectric layer and set to a predetermined potential.

According to the above structure, in the insulated gate type FET, the internal field plate embedded in the dielectric film is provided in the drift region which is the current path between the source and the drain. As a result, variations and concentration of the electric field in the drift region are alleviated, and a high breakdown voltage of the semiconductor device can be obtained. Further, since such a high breakdown voltage is obtained, the conductivity of the drift region can be increased and the resistance value can be reduced. Therefore, it is possible to achieve both low on-resistance and high breakdown voltage.

The semiconductor device may further include a second conductivity type diffusion region which is provided along the inner wall of the trench so as to surround the dielectric layer and forms a PN junction with the drift region. .

According to the above structure, the PN is provided in the drift region.
A so-called RESURF structure is formed in which a diffusion region that forms a junction is provided. In this structure, when a reverse bias is applied, the depletion layer formed from the PN junction spreads in the drift region. As a result, compared to the case where there is no PN junction, a high breakdown voltage can be maintained even when the drift region has a higher impurity concentration. The diffusion region is also arranged in the deep portion of the drift region along the inner wall of the trench, and the depletion layer is uniformly formed in the entire drift region. Thereby, a higher breakdown voltage can be obtained.

In the above structure, it is preferable that a plurality of the internal field plates are provided and are capacitively coupled to each other. As a result, each of the plurality of internal field plates is fixed to a potential corresponding to the capacitance ratio, and a high breakdown voltage is obtained by alleviating variations and concentration of the electric field.

In the above structure, for example, the trench is provided so as to extend in a substantially straight line connecting the drain region and the source region, and the internal field plate is
The dielectric layers are arranged at substantially equal intervals in the extending direction.

In the above structure, for example, a plurality of the dielectric layers enclosing the internal field plate are provided between the drain region and the source region at predetermined intervals. According to the above configuration, a sufficient current path is ensured between the dielectrics, the ON resistance during operation is kept low, and a high breakdown voltage during reverse bias is obtained.

According to the above configuration, for example, the internal field plate on the drain region side is set to the same potential as the drain region, and the internal field plate on the source region side is set to the same potential as the source region. To be done. That is, the potential of the internal field plate can be fixed by using the drain electrode and the source electrode connected to the drain region and the source region, respectively.

In the semiconductor device, further, on the drift region between the drain region and the source region,
A surface field plate provided via an insulating film may be provided. This prevents variation and concentration of the electric field not only inside the drain region but also near the surface.
Furthermore, the influence of an external electric field due to foreign ions, electrode wiring, etc. can be prevented. From these things, a more stable and high breakdown voltage can be obtained.

For example, the surface field plate is
A plurality of them are provided at a predetermined interval from each other. further,
The surface field plate is, for example, arranged substantially perpendicular to the dielectric layer containing the inner field plate.

In the above structure, the surface field plate may be substantially integrated with the inner field plate. As a result, the inner field plate and the surface field plate can be fixed in potential by a common electrode, and can be formed in the same process.

In the above structure, the internal and surface field plates are made of, for example, polysilicon. The insulating film is made of, for example, a silicon oxide film.

In order to achieve the above object, in a method for manufacturing a semiconductor device according to a third aspect of the present invention, a drift region of a first conductivity type formed on a semiconductor substrate and island-shaped provisions in the drift region are provided. A drain region having an impurity concentration higher than that of the drift region, a second conductivity type well region provided in the drift region in an island shape apart from the drain region, and an island in the well region. A source region of the first conductivity type provided in the shape of a stripe, and a gate electrode provided via an insulating film on at least a part of a well region sandwiched between the source region and the drift region. A method of manufacturing a semiconductor device, the method comprising: forming a plurality of grooves adjacent to each other in the drift region between the drain region and the source region; oxidizing an inner wall of the groove to form an oxide film. A step of forming, embedded a conductive film in the groove, characterized by comprising a step of forming an inner field plate.

According to the above structure, the insulated gate FE in which the internal field plate embedded in the dielectric film is provided in the drift region which is the current path between the source and the drain.
T can be manufactured. As a result, a semiconductor device having a high breakdown voltage, in which variations and concentration of electric field in the drift region are alleviated, is manufactured.

The manufacturing method may further include a step of performing impurity diffusion on the wall surface of the groove to form a diffusion layer on which the oxide film is laminated, before the step of oxidizing the inner wall of the groove. .

According to the method of the above structure, an insulated gate FET having a so-called RESURF structure in which a diffusion region forming a PN junction is provided in the drift region is manufactured. In the insulated gate FET having this structure, when a reverse bias is applied, the depletion layer formed from the PN junction spreads in the drift region and improves the breakdown voltage. The diffusion region is also arranged in the deep portion of the drift region along the inner wall of the trench, and the depletion layer is uniformly formed in the entire drift region. Thereby, a high breakdown voltage can be obtained.

The manufacturing method may further include a step of forming a surface field plate made of a conductor layer on the surface of the drift region. This prevents variation and concentration of the electric field not only inside the drain region but also in the vicinity of the surface, and a more stable and high breakdown voltage can be obtained.

In the method of the above structure, it is preferable that the step of forming the surface field plate is performed at the same time as the step of forming the inner field plate.

[0029]

DETAILED DESCRIPTION OF THE INVENTION A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. The semiconductor device of the present embodiment is a lateral MOSFET (Metal Oxid
e Semiconductor Field Effect Transistor) and a plurality of semiconductor elements (not shown) having a power capacity smaller than that of the lateral MOSFET, and function as a power switch as a whole.

FIG. 1 shows a top view of a semiconductor device 11 according to this embodiment. As shown in FIG. 1, the semiconductor device 1
1 includes a band-shaped drain electrode 12, a source electrode 13 provided in a ring shape so as to surround the drain electrode 12, and a gate electrode 14 adjacent to the outer peripheral side of the source electrode 13. As will be described later, the semiconductor device 11 includes a drain region, a source region, and a gate insulating film provided below each electrode. Drain electrode 12,
BPS is provided between the source electrode 13 and the gate electrode 14.
An insulating film 15 such as G is provided.

FIG. 2 shows an enlarged view of the one-dot chain line in FIG. In order to facilitate understanding, the drain electrode 12 and the source electrode 1 covered with the insulating film 15 in FIG.
3 and the gate electrode 14 are also shown by solid lines.

As shown in FIG. 2, the drain electrode 12 and
A plurality of strip-shaped first field plates 16 are provided between the source electrode 13 and the source electrode 13. The first field plate 16 is provided in an annular shape along the source electrode 13 so as to surround the drain electrode 12. The first field plate 16 is composed of a conductor film such as polysilicon.

The insulating film 15 is interposed between the adjacent first field plates 16. The innermost first field plate 16 is electrically connected to the drain electrode 12, while the outermost first field plate 16 is electrically connected to the source electrode 13. When a voltage is applied between the source electrode 13 and the drain electrode 12, the adjacent first field plate 16
Are capacitively coupled to the other adjacent first field plates 16 via the silicon oxide film.

FIG. 3 is a top view of the surface of the semiconductor device 11 from which the drain electrode 12, the source electrode 13, the gate electrode 14, the first field plate 16 and the insulating film 15 are removed.

As shown in FIG. 3, a drain region 17 and a source region 19 provided in a well region 18 facing the drain region 17 are provided in the surface region of the semiconductor device 11. The source region 19 is formed along the well region 18
The strips are provided at predetermined intervals.

A drain drift region 20 and a first trench 21 are provided in a region between the drain region 17 and the well region 18. Drain drift region 20
The first trenches 21 are alternately arranged at substantially equal intervals so as to be orthogonal to the drain regions 17 and the well regions 18. A second trench 22 is provided outside the well region 18 (on the opposite side of the drain region 17) via the drain drift region 20.

FIG. 4 is a sectional view taken along the line AA 'of FIG. 2 (and FIG. 3). That is, FIG. 4 shows that the drain drift region 2 is formed in the region between the drain region 17 and the well region 18.
0 indicates a state of being mainly arranged.

As shown in FIG. 4, the semiconductor device 11 has P
Formed on a substrate 23 of a rectangular shape, and an N-type drain drift region 20 formed by a well-known epitaxial growth method is formed on one surface thereof. The P-type substrate 23 and the N-type drain drift region 20 are shared by a plurality of semiconductor elements (not shown) having a power capacity smaller than that of the MOSFET.

The surface region of the drain drift region 20 is provided with an N ⁺ type drain region 17 formed by diffusion of N type impurities and having a higher impurity concentration than the drain drift region 20. The drain electrode 12 is provided on the drain region 17.

Further, in the surface region of the drain drift region 20, a P-type well region 18 formed by P-type impurity diffusion is provided. In the well region 18, N
⁺ Type source region 1 formed by diffusing a p-type impurity
9 are provided in an island shape. A source electrode 13 is provided on the P-type well region 18 and the source region 19 in contact with them.

Outside the well region 18 (drain region 17
The second trench 22 is provided on the opposite side). An insulating film 24 such as a silicon oxide film is thinly formed on the inner wall of the second trench 22, and a polysilicon film 25 is buried inside the insulating film 24. The polysilicon film 25 is exposed upward, and the exposed surface is in contact with the gate electrode 14 made of aluminum or the like. The polysilicon film 25 is
Impurities are introduced to impart predetermined conductivity. The insulating film 24 functions as a gate insulating film, and the gate electrode 1
By applying a gate voltage to the polysilicon film 25 by 4, the channel is formed in the P-type well region 18. As a result, current flows between the source region 19 and the drain region 17 with the drain drift region 20 as the main current path.

A plurality of first field plates 16 each having a rectangular cross section are provided near the surface of the semiconductor device 11. The first field plate 16 is arranged above the drain drift region 20 via the insulating film 15.

FIG. 5 shows a cross section taken along the line BB ′ of FIGS. 2 and 3. That is, in FIG. 5, the first trench 21 is mainly formed in the region between the drain region 17 and the well region 18.
Shows the state in which is arranged.

As shown in FIG. 5, the first trench 21 is formed.
Is formed in the deep portion of the drain drift region 20 by the P-type substrate 23.
It is formed so as to reach the vicinity of. A P-type diffusion region 26 is thinly formed around the first trench 21. As will be described later, the P-type diffusion region 26 forms a PN junction at the interface with the N-type drain drift region 20, and forms a depletion layer during reverse bias to improve the breakdown voltage.

The inside of the first trench 21 is filled with a silicon oxide film 28. In addition, the silicon oxide film 28
A second field plate 27 is embedded in the inside of the. The second field plate 27 extends substantially in a straight line perpendicular to the main surface of the semiconductor device 11 in the depth direction from the surface side so as to reach near the bottom of the first trench 21. A plurality of second field plates 27 are provided inside the first trench 21 (silicon oxide film 28) at substantially equal intervals.

Referring to FIG. 3, a plurality of rectangular second field plates 27 are provided in parallel with each other inside the first trench 21 extending in a strip shape at substantially equal intervals from the drain region 17 to the source region 19. Has been. 2 and 3
The second field plate 27 is arranged immediately below the first field plate 16 (not shown).

Returning to FIG. 5, the second field plate 2
7 are respectively connected to the first field plates 16 directly above them, and are substantially integrally formed. Therefore,
The innermost second field plate 27 is electrically connected to the drain electrode 12 via the first field plate 16. The outermost second field plate 27 is electrically connected to the source electrode 13 via the first field plate 16. A silicon oxide film 28 is interposed between the second field plates 27. When a voltage is applied between the source electrode 13 and the drain electrode 12, the second field plates 27 adjacent to each other are capacitively coupled.

In FIG. 5, when a reverse bias is applied between the source electrode 13 and the drain electrode 12, the first
Diffusion region 26 forming the inner wall of trench 21 of
Functions as a so-called resurf structure. That is,
A depletion layer is formed from the PN junction at the interface between the N type drain drift region 20 and the P type diffusion region 26, and the P type substrate 23 is formed.
And the drain drift region 20 are integrated with a depletion layer formed from a PN junction.

As shown in FIG. 3, the first trench 21
Are formed in the drain drift region 20 at predetermined intervals. Therefore, the current path at the time of forward bias is sufficiently secured, and at the time of reverse bias, the drain drift region 20 sandwiched between the adjacent first trenches 21 is formed of the P-type diffusion region 26 and the like facing each other. Filled with depletion layer. As described above, the P-type diffusion region 26 forms a sufficient depletion layer in the drain drift region 20, so that high breakdown voltage characteristics are obtained.

Here, further, the first field plate 16 and the second field plate 27 are MOS
It functions as a so-called floating field plate in the FET and further improves the breakdown voltage characteristics.

That is, as shown in FIGS. 2 and 4, the plurality of first field plates 16 are arranged on the region between the drain region 17 and the source region 19 at a predetermined interval. As described above, the first field plate 16 includes the drain electrode 12 and the source electrode 1.
3 is electrically connected. Thus, when biased, the first field plate 16 whose potential is fixed by the capacitance ratio exists on the surface of the drain drift region 20, and the concentration of electrolysis at a specific point near the surface of the drain drift region 20 is mitigated. It

Further, the second field plate 27 is
It extends to the deep portion of the drain drift region 20 and contributes to fixing the potential in the depth direction. That is, the second field plate 27 is connected to the first field plate 16, and the potential is fixed according to the capacitance ratio when biased. Thereby, the drain drift region 20
The concentration of the electric field is relieved even in the deep part of.

First field plate 16 on the device surface
By using the second field plate 27 extending to the deep portion of the element, and adjusting the size and interval, the conditions of the silicon oxide films 15 and 28 surrounding these, and the like,
The drain drift region 20 at the time of reverse bias can be controlled to a desired potential with high precision. Therefore, even if the impurity concentration of the drain drift region 20 is set high, it is possible to prevent the breakdown voltage from decreasing and obtain a desired breakdown voltage. As a result, it is possible to achieve both a high breakdown voltage and a high on-resistance that are in a trade-off relationship.

For example, by appropriately changing the distance between the second field plates 27, the capacitance ratio between the second field plates 27 can be changed and the potential distribution can be changed as desired. Further, the interval between the first trenches 21 can be changed to freely change the pattern of the drain drift region 20 between them. At the same time, by giving the drain drift region 20 a distribution of the amount of impurities in consideration of the electric field induced when a high voltage is applied, it is possible to suppress the generation of a parasitic current when passing a current.

Furthermore, as shown in FIG. 3, the first trench 21 including the second field plate 27 and the RESURF structure has a drain drift between the drain region 17 and the source region 19 (well region 18). In area 20,
It is provided at a predetermined interval so as to be orthogonal to the drain region 17. In this way, the first trenches 21 are formed at intervals.
By providing, it is possible to secure a sufficient main current path. Therefore, a high breakdown voltage can be obtained without increasing the on-resistance.

Hereinafter, the semiconductor device 1 according to the present embodiment
The manufacturing method of No. 1 will be described with reference to the drawings.

First, the relatively high concentration N type epitaxial layer 20 (about 0.1Ω to 2Ω) is formed on the low concentration P type substrate 23. Subsequently, as shown in FIG. 6A, a plurality of first trenches 30 are formed by a photolithography technique and an etching technique.

Next, a low concentration P-type impurity is added to the first groove 3
By selectively doping the inside of 0, a P-type impurity region 31 is formed on the inner wall of the first groove 30 as shown in FIG. 6B. Then, the inside of the first groove 30 is thermally oxidized to form a silicon oxide film 28 laminated on the P-type diffusion region 26 as shown in FIG. 6C. Here, the intervals between the first grooves 30 are formed to be narrow, and the silicon layer between the first grooves 30 is almost changed to the silicon oxide film 28.

Subsequently, the second groove 32 is formed by the photolithography technique and the etching technique. afterwards,
Thermal oxidation is performed, and as shown in FIG.
And a silicon oxide film 33 is formed on the surface of the substrate.

Then, as shown in FIG. 7E, the CVD (Chemical) is performed inside the first groove 30 and the second groove 32.
Vapor Deposition) fills the polysilicon film and forms a film having a predetermined thickness on the entire surface. At this time, a polysilicon film doped with impurities is formed, or the formed polysilicon film is doped with impurities by a diffusion method.

Subsequently, the polysilicon film on the surface is patterned into a predetermined shape by using a photolithography technique and an etching technique, as shown in FIG. As a result, the first field plate 16, the second field plate 27 integrated with the first field plate 16, and the polysilicon film 25 functioning as a gate electrode are formed.

Further, a P-type impurity is selectively doped and is diffused to a predetermined depth by heat treatment. As a result, the P-type well region 18 is formed. After that, N-type impurities are selectively doped and heat-treated to diffuse to a predetermined depth. As a result, the drain region 17 and the source region 19 are formed as shown in FIG. Here, the well region 18 and the source region 19
Are formed by the DSA (Diffusin Self-Align) method.

Subsequently, the insulating film 15 is formed on the surface and heat treatment is performed. After that, a contact window is formed by photolithography technology and etching technology, and C
An electrode made of aluminum or the like is formed by VD or the like.
As a result, the semiconductor device 11 shown in FIG. 8H is formed, and the manufacturing process is completed.

As described above, the present invention can be applied to the MOSFE
The semiconductor device 11 applied to T has a first semiconductor device in the vicinity of the surface of the drain drift region 20, which serves as the main current path of the MOSFET.
The field plate 16 of FIG. Further, in the first trench 21 provided in the drain drift region 20, the second field plate 27 is embedded in the insulating film 28. Thereby, the drain drift region 20
The field plate effect is obtained not only in the vicinity of the surface but also in the deep portion, and a high breakdown voltage is obtained.

A plurality of first trenches 21 are provided between the drain region 17 and the well region 18 (source region 19) at a predetermined interval. As a result, a sufficient current path can be secured, so that low on-resistance and high breakdown voltage can be achieved at a high level.

The present invention is not limited to the above embodiment, but various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

In the above embodiment, the insulating film between the first field plates 16 and the second field plates 27 is made of a silicon oxide film. However, the first field plate 16 and the second field plate 2 are not limited to the silicon oxide film.
Any material such as a silicon nitride film may be used as long as 7 is a dielectric film that electrically couples with a desired capacitance ratio.

In the above embodiment, the second trench 21 is used.
A P-type diffusion region 26 that forms a PN junction with the N-type drain drift region 20 is provided around the structure. However, a configuration without the P-type diffusion region 26 is also possible. However, it goes without saying that a higher breakdown voltage can be obtained by providing the P-type diffusion region 26 and forming the PN junction.

In the above embodiment, the well region 18 and
The source electrode 19 and the same electrode (source electrode 13)
Shall be connected to. However, with the well region 18,
The source region 19 and the source region 19 may be connected to different electrodes (power sources).

In the above embodiment, the N-channel MO is used.
The SFET has been described as an example. However, it is of course possible to apply it to a P-channel type MOSFET. Also,
The invention is not limited to MOSFETs, and may be applied to other insulated gate FETs.

In addition, the substrate 23 and the drain drift region 2
A so-called SOI (Silicon On Insulator) structure may be provided by providing an insulating film such as a silicon oxide film between 0 and 0. In this case, the present invention is applied to a lateral IGBT (Insulated Gate Bipol).
ar Transistor) etc.

Further, the present invention can be used as a high breakdown voltage resistor or a high breakdown voltage isolation.

[0073]

As described above, according to the present invention,
Provided are a semiconductor device having a high breakdown voltage and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a top view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a top view of the semiconductor device according to the exemplary embodiment of the present invention.

FIG. 3 is a top view of the semiconductor device according to the exemplary embodiment of the present invention.

FIG. 4 is an A- of a semiconductor device according to an embodiment of the present invention.
It is a sectional view taken along the line A '.

FIG. 5 is a semiconductor device B- according to an embodiment of the present invention.
It is a sectional view taken along line B '.

FIG. 6 is a diagram showing a manufacturing process of the semiconductor device according to the embodiment of the invention.

FIG. 7 is a diagram showing a manufacturing process of the semiconductor device according to the embodiment of the invention.

FIG. 8 is a diagram showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

[Explanation of symbols]

11 Semiconductor device 12 drain electrode 13 Source electrode 14 Gate electrode 15 Insulating film 16 First field plate 17 Drain region 18 well area 19 Source area 20 Drain drift region 21 first trench 22 Second trench 23 board 24 Silicon oxide film 25 Polysilicon film 26 P-type diffusion region 27 Second field plate 28 Silicon oxide film

Claims (17)

[Claims] 1. A first semiconductor region set to a first potential, a second semiconductor region spaced apart from the first semiconductor region and set to a second potential, the first semiconductor region. A third semiconductor region that surrounds the first semiconductor region and the second semiconductor region so that the surface thereof is exposed, and forms a current path between the first semiconductor region and the second semiconductor region; And the first semiconductor region and the second semiconductor region
A semiconductor device comprising: a dielectric layer provided in a trench formed between a semiconductor region and an internal field plate provided inside the dielectric layer and set to a predetermined potential. . 2. A drift region of a first conductivity type formed on a semiconductor substrate, a drain region of a first conductivity type provided in the drift region in an island shape and having an impurity concentration higher than that of the drift region, A second conductivity type well region provided in the drift region in an island shape apart from the drain region; and a first conductivity type source region provided in an island shape in the well region; A gate electrode provided on at least a part of the well region sandwiched between the source region and the drift region via an insulating film, and between the drain region and the source region in the drift region. A semiconductor device comprising: a dielectric layer provided in the formed trench; and an internal field plate provided inside the dielectric layer and set to a predetermined potential. 3. A diffusion region of a second conductivity type is provided along the inner wall of the trench so as to surround the dielectric layer and forms a PN junction with the drift region.
The semiconductor device according to claim 2, wherein: 4. The plurality of inner field plates are provided and are capacitively coupled to each other.
Alternatively, the semiconductor device according to item 3. 5. The trench is provided so as to extend in a substantially linear shape connecting the drain region and the source region, and the internal field plates are arranged at substantially equal intervals in the extending direction of the dielectric layer. The semiconductor device according to any one of claims 2 to 4, wherein: 6. A plurality of the dielectric layers enclosing the internal field plate are provided between the drain region and the source region at a predetermined interval from each other. 6. The semiconductor device according to any one of items 5 to 5. 7. The internal field plate on the drain region side is set to the same potential as the drain region, and the internal field plate on the source region side is set to the same potential as the source region. The semiconductor device according to any one of claims 2 to 6. 8. A surface field plate provided via an insulating film on the drift region between the drain region and the source region, further comprising a surface field plate. The semiconductor device according to claim 1. 9. The semiconductor device according to claim 8, wherein a plurality of the surface field plates are provided at a predetermined interval from each other. 10. The semiconductor device according to claim 8, wherein the surface field plate is arranged substantially perpendicular to the dielectric layer that encloses the internal field plate. 11. The semiconductor device according to claim 8, wherein the surface field plate is formed substantially integrally with the inner field plate. 12. The semiconductor device according to claim 2, wherein the inner and surface field plates are made of polysilicon. 13. The semiconductor device according to claim 2, wherein the insulating film is composed of a silicon oxide film. 14. A drift region of a first conductivity type formed on a semiconductor substrate, and an island shape provided in the drift region,
A drain region having an impurity concentration higher than that of the drift region, a second conductivity type well region provided in the drift region in an island shape apart from the drain region, and in an island shape in the well region. A semiconductor device including a provided first-conductivity-type source region and a gate electrode provided via an insulating film on at least a portion of a well region sandwiched between the source region and the drift region. And a step of forming a plurality of trenches adjacent to each other in the drift region between the drain region and the source region, and oxidizing an inner wall of the trench to form an oxide film. A method of manufacturing a semiconductor device, comprising: a step of burying a conductor film in the groove to form an internal field plate. 15. The method further comprises the step of performing impurity diffusion on the wall surface of the groove to form a diffusion layer on which the oxide film is laminated, before the step of oxidizing the inner wall of the groove. The method for manufacturing a semiconductor device according to claim 14. 16. Further, on the surface of the drift region,
16. The method of manufacturing a semiconductor device according to claim 14, further comprising a step of forming a surface field plate made of a conductor layer. 17. The method of manufacturing a semiconductor device according to claim 16, wherein the step of forming the front surface field plate is performed simultaneously with the step of forming the inner field plate.