JPH05110078A - Field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To form a field effect transistor which enables a P-N junction to be lessened in area restraining it from increasing in contact resistance by a method wherein a second conductivity type region is continuously extended from one side of a ridge to the other side to be provided onto the ridge. CONSTITUTION:A first conductivity type base 30, an insulating film 36 provided with a window 34 which exposes the element forming regions 32 of the base 30, a gate oxide film 38 and a gate electrode 40 located nearly at the center of the regions 32, a drain region 42 provided to the adjacent element forming region 32, and a source region 44 provided to the other element forming region 32 are provided. The drain region 42 and the source region 44 are set to be of second conductivity type regions, ridges 46 and troughs 48 are alternately provided in parallel to both the element forming regions 32 or either of them, and a second conductivity type region is continuously provided extending from the side of the ridge 46 to the other side of it in constitution. Therefore, a P-N junction is lessened in area so as to be decreased in junction capacitance, so that a field effect transistor of this design can be improved in operation speed.

Description

Detailed Description of the Invention

[0001]

This invention relates to the structure of field effect transistors.

[0002]

2. Description of the Related Art Currently, VLSI (Very Large)
As a basic element that constitutes the Scale Integration, a field effect transistor (Metal Oxide Semiconductor) having a MOS structure is used.
r Field Ef-fect Transisto
r: referred to as MOSFET) is widely used. Hereinafter, a structure of a conventional MOSFET will be schematically described with reference to the drawings. For details of the MOSFET manufacturing method and the element structure, see, for example, Document 1: Ultra-high-speed MOS device, Baifukan, February 10, 1986, p117-1.
See 25.

11A and 11B show a conventional MOSF.
11A and 11B are a cross-sectional view and a plan view schematically showing the configuration of a main part of the ET, and FIG. 11A shows a cross section taken along line AA of FIG. 11B. In the figure, the MOS included in the VLSI
Focusing on the FET1 element, the configuration of the main part thereof is shown.

As shown in FIGS. 11A and 11B, F
The ET 10 includes a substrate 12, a gate oxide film 16, a gate electrode 18, a source region 20 and a drain region 22. A field oxide film 24 is provided on the substrate 12 for electrically separating the FET 10 included in the VLSI and the other elements, and a window 26 exposing the element formation region 14 of the substrate 12 is formed in the field oxide film 24. Set up. And window 2
A gate oxide film 16 and a gate electrode 18 are sequentially provided on the element forming region 14 exposed through the gate electrode 6. Further, the source region 20 and the drain region 22 are provided in the element formation region 14 so as to be adjacent to one and the other side portions of the gate electrode 18. In the figure, the source region 20 and the drain region 22 are indicated by dots. Although not shown, the gate electrode 18 and the source region 20
The source region 20 is provided on the drain region 22 and the drain region 22, respectively.
And an intermediate insulating film having a contact hole exposing the drain region 22 is provided. A wiring electrode connected to the source region 20 and the drain region 22 through a contact hole is provided on this insulating film.

When the FET 10 is an n-channel MOSFET, a p-type substrate is used as the substrate 12 and an n ⁺ layer formed by adding an n-type impurity to the substrate 12 is used as the source region 20.
And the drain region 22. When the FET 12 is a p-channel MOSFET, an n-type substrate is used as the substrate 12 and a p-type impurity is added to the substrate 12 to form a p-type MOSFET.
^{The +} layer is the source region 20 and the drain region 22. The junction capacitance due to the pn junction between the substrate 12 and the source region 20 and the drain region 22 is a factor that delays the operating speed of the FET 10, and therefore the FET 10
The junction capacitance of the source region 20 and / or the drain region 22 may be reduced in order not to delay the operation speed of the above.

The value of the junction capacitance of the source region 20 or the drain region 22 is a value obtained by multiplying the capacitance value per unit area of the pn junction in the source region 20 or the drain region 22 by X · Y. Here, as shown in FIG. 11B, X
Is the length of the source region 20 or the drain region 22 in the width direction of the gate electrode 18 in a plan view, and Y
Represents the length of the source region 20 or the drain region 22 in the length direction of the gate electrode 18 when viewed in a plan view.

[0007]

However, the conventional F
In ET, the junction capacitance per unit area in the source and drain regions is determined by the amount of extension of the depletion layer extending from the source and drain regions into the underlying substrate, so there is a limit to reducing the junction capacitance per unit area. is there.
Further, in the conventional FET, the area of the pn junction can be reduced by reducing the length X and / or Y. However, by reducing the length X and / or Y, the connection between the source / drain region and the corresponding wiring electrode can be achieved. The area is reduced, resulting in an increase in contact resistance between these regions and the electrodes.

Therefore, the conventional FET has a limit in reducing the delay of the operating speed.

An object of the present invention is to solve the above-mentioned conventional problems, and to provide a field effect transistor having a structure capable of reducing the area of a pn junction while suppressing an increase in contact resistance, and a manufacturing method thereof. It is in.

[0010]

In order to achieve this object, the field effect transistor of the first invention of this application exposes a first conductivity type underlayer and an element formation region of the underlayer provided on the underlayer. An insulating film having a window, a gate oxide film and a gate electrode sequentially provided in substantially the center of the element formation region, and a drain region provided in one element formation region adjacent to one side of the gate electrode, A source region provided in the other element formation region adjacent to the other side of the gate electrode, and the drain region and the source region are regions of the second conductivity type opposite to the first conductivity type; A plurality of peaks and a plurality of troughs are provided in parallel by alternately disposing peaks and troughs on both or either of the element forming regions of
It is characterized in that the second conductivity type region is continuously provided from one side portion of the mountain portion to the other side portion of the mountain portion.

Further, a method of manufacturing a field effect transistor according to the second invention is a method for manufacturing a field effect transistor in which the valley portion of the field effect transistor of the first invention is an underlayer of the first conductivity type. In this case, a peak and a valley are formed by etching one or the other of the element forming regions or one of the bases, and then an insulating film is formed on the valley so that the peak is exposed, Next, a second conductivity type impurity having a conductivity type opposite to the first conductivity type is implanted into the insulating film by an ion implantation method at a depth that does not reach the valley portion from the upper surface portion of the insulating film, and a plurality of impurities are added to the mountain portion. Is injected from different incident directions.

[0012]

According to the first aspect of the present invention, the second conductivity type region to be the drain region or the source region is continuously provided from one side portion to the other side portion of the mountain portion in the mountain portion. , The pn junction is only formed between the second conductivity type region and the first conductivity type base on the bottom side of the mountain portion. Therefore, if the surface area of the second conductivity type region is the same and compared with the conventional case, the area of the pn junction can be reduced. Moreover, the area of the pn junction can be reduced as the area of the second conductivity type region provided in the mountain portion is increased.

Further, according to the second invention, the insulating film is formed in the valley so as to expose the peak, and the second conductivity type impurity is then formed at a depth not reaching the valley from the upper surface of the insulating film. While being injected into the insulating film, it is injected into the mountain portion from a plurality of different incident directions. Therefore, the second conductivity type region can be formed continuously from one side of the peak to the other side while preventing the second conductivity type impurities from being injected into the valley by the insulating film.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the drawings are merely schematic representations so that the invention can be understood, and therefore the present invention is not limited to the illustrated examples.

1 and 2 are a plan view and a cross-sectional view schematically showing the structure of a main part of an embodiment of the present invention, and FIG.
A cross section taken along line II-II of FIG. F in this example
The ET 28 is a MOSFET mounted on an LSI, and the configuration of the main part is shown in these figures.

In the FET 28 of this embodiment, an underlayer 30, an insulating film 36 provided on the underlayer 30 and having a window 34 for exposing an element forming region 32 of the underlayer 30, and a FET 28 are located substantially in the center of the element forming region 32. The gate oxide film 38 and the gate electrode 40 sequentially provided on the element forming region 32, the drain region 42 provided in one element forming region p adjacent to one side of the gate electrode 40, and the gate electrode 40 A source region 44 provided in the other element forming region q adjacent to the other side portion, and a peak portion 46 and a valley portion 48 provided in both the one and the other element forming regions p and q are provided.
1 and 2, the drain region 42 and the source region 44 are indicated by dots, and the drain region 42
And pn formed between the source region 44 and the base 30
The joint portion is shown by a dotted line.

The base 30 is a base made of a semiconductor material of the first conductivity type, for example, a p-type Si substrate, and an insulating film 36 is provided on the base 30. The insulating film 36 is, for example, a field oxide film, and is used to separate the FET 28 mounted on the LSI from other electric circuit elements. The element forming region 32 of the base 30 is exposed through the window 34 of the insulating film 36. Then, the gate insulating film 38 and the gate electrode 40 are provided in substantially the center of the element forming region 32, and one and the other element forming regions p and q are arranged adjacent to the gate electrode 40 so as to sandwich the gate electrode 40.

Further, one and the other element forming regions p and q
The plurality of peaks 46 and the plurality of valleys 48 are alternately arranged and the plurality of peaks 46 and the plurality of valleys 48 are arranged in parallel. The peak portion 46 and the valley portion 48 are formed, for example, in the gate electrode 40.
Are provided so as to extend parallel to the lengthwise direction of the gate electrode 40 and be spaced apart from the gate electrode 40.

The drain region 42 and the source region 44 are second conductivity type regions of opposite conductivity type to the first conductivity type, for example, n ⁺ regions, and the second conductivity type regions are formed from one side of the peak portion 46 to the other. It is provided in the mountain part 46 continuously to the side part of the
8 is a first conductivity type base 30. Therefore, since the drain region 42 and the source region 44 each include the peak portion 46, the drain region 42 is reduced as the element size of the FET is reduced.
Even if the planar area of the source region 44 is reduced, by increasing the number and depth (or height) of the ridges 46, these regions 42 and 44 are made to correspond to the wiring electrodes. It is possible to increase the contact area between these regions 42 and 44 and the wiring electrode when they are connected to each other, and as a result, it is possible to suppress an increase in contact resistance between these regions and electrodes. Further, since the second conductivity type region is continuously provided from one side portion to the other side portion of the mountain portion 46, the mountain portion 4
6, the second conductivity type region and the first conductivity type base 30
The pn junction formed between and is present only in the lower portion of the peak portion 46, and there is no pn junction in the other portions of the peak portion 46. Therefore, when the surface area of the second conductivity type region is made the same and compared with the conventional FET, the area of the pn junction is reduced and therefore the junction capacitance due to the pn junction is reduced. Moreover, Yamabe 4
By increasing the number of 6 and the depth,
The surface area of the second-conductivity-type region provided in is increased, and the area of the pn junction is reduced with this increase. When the total surface area of the second conductivity type region as the drain region 42 or the source region 44 is kept constant, the surface area of the second conductivity type region provided in the peak portion 46 is increased and the drain region 42 or the drain region 42 or The area of the source region 44 in plan view is reduced, so that the device scale of the FET can be further reduced.

Further, in this embodiment, a second conductivity type region is provided in the peak portion 46 of one element forming region p and a region p1 between the peak portion 46 and the gate electrode 40, and these second conductivity type regions are drain regions. 42, and the remaining region p2 of the one element formation region p is used as the first conductivity type base 30. In carrying out the present invention, the valley portion 4 of one element forming region p is
8 and the second conductivity type region may be formed in a portion of the region p2 other than the valley portion 48, but in order to more effectively reduce the area of the pn junction, the valley portion 48, and further the region. It is more advantageous to use the portion of p2 other than the valley portion 48 as the first conductivity type base 30. Similarly, in order to reduce the area of the pn junction more effectively, the peak portion 4 of the other element forming region q is formed.
6 and a region q1 between the mountain portion 46 and the gate electrode 40
Second conductivity type regions are provided as the source regions 44, and the remaining region q2 of the other element forming region q is provided.
Is the first conductivity type base 30.

Further, in this embodiment, as will be described later, impurities are added to the base 30 by the ion implantation method to form the second conductivity type region.
Because it is added to the mountain portion 46 while not adding to
Further, since the valley portion 48 is the first conductivity type base 30, the valley portion 4
An insulating film 50 is provided on the valley portion 48 for the purpose of not electrically contacting the wiring metal of the drain region 42 and the source region 44 with each other. When forming the second conductivity type region in the valley portion 48, the insulating film 50 may not be provided.

Next, an example of the second invention will be described. This embodiment is an example of the method of manufacturing the FET 28 described above. 3 to 10 are explanatory views of the manufacturing process of the embodiment of the second invention. 3, 5 and 6 (A) and FIG. 10 are plan views of a main part schematically showing a state of an element formation region and a region corresponding to the vicinity thereof in the course of manufacturing the FET, and FIG. 5 and 6 (B) and FIGS. 4 and 7 to 9 (A) to (B), respectively.
3 is a cross-sectional view schematically showing a state of a region corresponding to a drain region in the process of manufacturing an FET, in a cross section corresponding to a cross section taken along line III-III in FIG.
It is along the line III-III in (A). Moreover, FIG. 3 (B)
5A shows the same step as FIG. 3A, FIG. 5B shows the same step as FIG. 5A, and FIG. 6B shows the same step as FIG. 6A.

In manufacturing the FET 28 of this embodiment, a base of the first conductivity type such as a p-type Si substrate is prepared as the base 30. Next, as shown in FIGS. 3A and 3B, a pad oxide film 52 is formed on the base 30. The pad oxide film 52 is, for example, SiO formed by a thermal oxidation method.
_Two films, which are formed for the purpose of stress relaxation at the time of forming the field oxide film 36. Then, on the pad oxide film 52,
The mask forming film 54 is laminated. The mask forming film 54 is made of a material that is not easily oxidized, and is formed by, for example, CVD (Chem).
This is a Si ₃ N ₄ film formed by the ICP method. Then, a resist pattern 56 used for patterning the mask forming film 54 is formed on the mask forming film 54.

Next, as shown in FIG. 4A, the mask forming film 54 is patterned using the resist pattern 56 as a mask to obtain a mask 58 made of the patterned mask forming film 54. At this time, only the mask forming film 54 is selectively patterned without patterning the pad oxide film 52. Then, impurities for channel stopper, for example, B ions are selectively added to the base 30 around the element forming region 32. In the figure, the region to which this ion is added is schematically indicated by a cross mark.

Next, as shown in FIG. 4B, the resist pattern 56 is removed, and then the underlayer 30 is selectively oxidized by using a mask 58 to form an insulating film 36 on the underlayer 30. Since the mask 58 is not easily oxidized, the insulating film 36 is selectively formed on the region of the base 30 which is not covered with the mask 58.

Next, as shown in FIGS. 5 (A) and 5 (B),
The mask 58 and the pad oxide film 52 are removed to remove the insulating film 36.
A window 34 is formed in the. The base 30 in the element formation region 32 is exposed through the window 34.

Next, peaks 46 and valleys 48 are formed in both the element formation regions p and q by etching. Therefore, as shown in FIGS. 6A and 6B, a mask 60 for forming the peaks 46 and the valleys 48 is formed on the element forming region 32 exposed through the window 34. The mask 60 has a stripe-shaped window 62 extending in the gate length direction. A plurality of windows 62 are arranged in a region to be one element forming region p and a region to be the other element forming region q, respectively, and a portion of the element forming region 32 where the valley portion 48 is to be formed is exposed through the window 62. Then, the remaining portion is covered with the mask 60. Thereafter, for example, by a conventionally known dry etching method, a portion where the valley portion 48 of the element forming region 32 is to be formed is selectively removed by etching to form a groove 64 in this portion. The portion 46 and the valley portion 48 are formed. Yamabe 4
After forming 6 and the valley portion 48, the mask 60 is removed.

Next, an insulating film 50 is formed on the valley 48 so as to expose the peak 46 by, for example, an etch back method in order to prevent the valley 48 from being doped with impurities. Therefore, as shown in FIG. 7A, an oxide film 66 for forming the insulating film 50 is deposited in the trench 64 by, for example, the CVD method,
After that, a resist 68 is embedded in a recess formed in a portion of the oxide film 66 corresponding to the groove 64, and the recess is flattened. Preferably, the oxide film 66 and the resist 68 are made of a material having an etching rate substantially equal to each other, and the oxide film 66 is made of a material having an etching rate faster than the etching rates of the base 30 and the insulating film 36.
Next, as shown in FIG. 7B, the oxide film 66 having a predetermined film thickness is left on the valley portion 48 by, for example, reactive ion etching, and the remaining oxide film 66 and the resist 68 are removed by etching. The film 66 and the resist 68 are etched to obtain an insulating film 50 made of the oxide film 66 left on the valley 48.

Next, as shown in FIG. 8A, an oxide film 70 for forming a gate oxide film is formed on the element forming region 32. The oxide film 70 is formed, for example, in the element formation region 32 at 900 ° C.
Film thickness of 3 to 3
It is a SiO ₂ film of about 20 nm. Then, although not shown,
Impurities for controlling the threshold voltage are added to the element forming region 32.

Next, as shown in FIG. 8B, the oxide film 7
0 for forming a gate electrode, for example, a polysilicon film 72
And then a resist mask 74 is formed on the polysilicon film 72. The mask 74 covers the gate electrode formation portion of the polysilicon film 72 and exposes the remaining portion.

Next, as also shown in FIG. 9, the gate electrode forming portion of the polysilicon film 72 is left and the remaining portion is removed by etching to obtain the gate electrode 40 made of the remaining polysilicon film 72 and the insulating film. Expose 36.
Next, the portion of the oxide film 70 immediately below the gate electrode is left and the remaining portion is removed by etching to obtain the gate oxide film 38 of the remaining oxide film 70 and the element formation region 3
2. The peaks 46 and the valleys 48 are exposed.

Next, a second conductivity type impurity having a conductivity type opposite to the first conductivity type is implanted into the insulating film 50 by an ion implantation method from the upper surface portion of the insulating film 50 to a depth not reaching the valley portion 48. However, the peak portion 46 is injected from a plurality of different incident directions. Therefore, as shown in FIG.
4 and then resist mask 7 with window 76
8 is a device forming region 32, a gate electrode 40 and an insulating film 36.
Form on top. The mask 78 is used for forming a portion of the element formation region 32 where the drain region 42 is to be formed and a source region 44.
And the portion of the gate electrode 40 between these portions is exposed through the window 76, and the remaining portion is covered. Then
A second conductivity type impurity such as P ions or As ions is added to the element forming region 32 exposed through the window 76 to complete the basic structure of the FET 28 as shown in FIGS.
When the second conductivity type impurity is added, the impurity is added by an ion implantation method using, for example, part of the gate electrode 40 and the mask 78 as a mask. Moreover, the second conductivity type region is continuously formed from one side portion of the mountain portion 46 to the other side portion thereof, and the mountain portion 4 is formed.
6, so that the main surface of the base 30 (in this example, S
It is preferable that the second-conductivity-type impurity be incident on the side wall portion of the crest portion 46 not only from the direction perpendicular to the substrate surface of the i substrate but also from a plurality of directions oblique to the main plane. Note that, for example, as shown in FIG. 2, the second conductivity type impurity is introduced so that the second conductivity type impurity is introduced into a region between the upper surface of the peak portion 46 and the depth h that does not reach the valley portion 48. Adjust the depth.

Next, although not shown in the drawing, according to a conventionally known method,
Gate electrode 40, drain region 42, and source region 44
An intermediate insulating film is laminated on top, and then contact holes exposing the drain region 42 and the source region 44 are formed in the intermediate insulating film. The contact holes of the drain region 42 and the source region 44 are defined by p of the drain region 42 and the source region 44.
Except for the n-junction portion, these regions 42 and 4 are exposed.
The pn junction portion of No. 4 and the underlying portion of the first conductivity type are not exposed. Next, a wiring electrode connected to the drain region 42 and the source region 44 through the contact hole is formed on the intermediate insulating film, and the wiring of the FET 28 is completed.

In the example described above, an n-channel FET is manufactured as the FET 28. However, in place of this, the second conductivity type impurity for forming the drain region 42 and the source region 44 using the base 30 as an n-type substrate. For example B
Alternatively, BF ₂ may be used and a p-channel FET may be manufactured as FET 28.

The present invention is not limited to the above-mentioned embodiment, and therefore, the shape of each component, the arrangement position,
The forming material, the forming method, the numerical conditions, the extending direction, the numerical conditions and the like can be arbitrarily changed. For example, in the embodiments of the first and second inventions, the peaks and valleys are provided or formed only in one of the element forming regions of the one side and the other side adjacent to the one side and the other side of the gate electrode. May be. In order to reduce the junction capacitance due to the pn junction and improve the operating speed of the field effect transistor, at least one element formation region in which a drain region should be formed or should be formed should have a peak and a valley. It is better to Further, in the above-mentioned example, the ridges and valleys are formed by forming the grooves in the first-conductivity-type base, but the method of forming the ridges and valleys is not limited to this. Alternatively, for example, a peak portion and a valley portion may be formed by stacking a layer of the second conductivity type on the lower surface of the first conductivity type and etching the layer of the second conductivity type.

[0036]

As is apparent from the above description, according to the first invention, the second conductivity type region to be the drain region or the source region is continuously formed from one side portion of the mountain portion to the other side portion. Since it is provided in the mountain part, in the mountain part, pn
The junction is only formed between the second conductivity type region and the first conductivity type base on the bottom side of the peak. Therefore, if the surface area of the second conductivity type region is the same and compared with the conventional case, by increasing the second conductivity type region provided in the mountain portion, the area of the pn junction is reduced while suppressing an increase in contact resistance, and the pn junction is reduced. It is possible to reduce the junction capacitance due to, thereby improving the operating speed of the field effect transistor.

Further, according to the second invention, the insulating film is formed in the valley so as to expose the peak, and the second conductivity type impurity is then formed at a depth not reaching the valley from the upper surface of the insulating film. While being injected into the insulating film, it is injected into the mountain portion from a plurality of different incident directions. Therefore, the second conductivity type region can be continuously formed from one side portion of the crest portion to the other side portion while preventing the second conductivity type impurity from being injected into the valley portion by the insulating film.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a main part of a basic structure according to an embodiment of the first invention.

FIG. 2 is a sectional view schematically showing a main part of a basic structure of an embodiment of the first invention.

FIGS. 3A and 3B are explanatory views of an embodiment of the second invention, and are a plan view and a cross-sectional view of a main part schematically showing a state in the process of manufacturing in the same process step.

4 (A) and 4 (B) are explanatory views of an embodiment of the second invention, which is a cross-sectional view of an essential part schematically showing a state in the course of manufacturing in different process steps.

5 (A) and 5 (B) are explanatory views of an embodiment of the second invention, and are a main part plan view and a main part cross-sectional view schematically showing a state in the course of manufacturing in the same process step.

6 (A) and 6 (B) are explanatory views of an embodiment of the second invention, and are a plan view and a cross-sectional view of a main part schematically showing a state in the process of manufacturing in the same process step.

7 (A) and 7 (B) are explanatory views of an embodiment of the second invention, which is a cross-sectional view of relevant parts schematically showing a state in the process of being manufactured in different process steps.

8A and 8B are explanatory views of an embodiment of the second invention and are cross-sectional views of a main part schematically showing a manufacturing process in different process steps.

FIG. 9 is an explanatory view of the embodiment of the second invention, and is a cross-sectional view of a main part schematically showing a state in the course of manufacturing.

FIG. 10 is an explanatory view of the embodiment of the second invention, and is a main part plan view schematically showing a state in the course of manufacturing.

11 (A) and 11 (B) are a main-portion cross-sectional view and a main-portion plan view schematically showing the configuration of a conventional MOSFET.

[Explanation of symbols]

 28: FET 30: Base 32: Element forming region 34: Window 36, 50: Insulating film 38: Gate insulating film 40: Gate electrode 42: Drain region 44: Source region 46: Mountain part 48: Valley part

Claims (5)

[Claims] 1. A first-conductivity-type underlayer, an insulating film provided on the underlayer and having a window exposing the element formation region of the underlayer, and a gate sequentially provided in substantially the center of the element formation region. An oxide film and a gate electrode, a drain region provided in one element formation region adjacent to one side of the gate electrode, and a source provided in another device formation region adjacent to the other side of the gate electrode. And a drain region and a source region as a second conductivity type region of a conductivity type opposite to the first conductivity type, in one or both of the one and the other element formation region. A plurality of peaks and a plurality of valleys are provided in parallel by alternately arranging peaks and valleys, and the second conductivity type region is continuously formed from one side of the peaks to the other side. What was provided in the mountain Field-effect transistor which is characterized. 2. The field effect transistor according to claim 1, wherein the valley portion is an underlayer of the first conductivity type. 3. A second conductivity type region is provided in the peak portion and a region between the peak portion and the gate electrode in both or one of the one and the other element forming regions, and the remaining region is a first region. 2. A base of one conductivity type is used.
A field effect transistor described in 1. 4. The peak portion and the valley portion are provided so as to extend in the length direction of the gate electrode.
A field effect transistor described in 1. 5. In manufacturing the field effect transistor according to claim 2, a peak and a valley are formed by etching on a base of both or one of the one and the other element forming regions, and An insulating film is formed on the valley so as to expose the peak, and then a second conductivity type impurity having a conductivity type opposite to the first conductivity type is formed,
An electric field characterized by performing ion implantation from a plurality of different incident directions to the peak portion while implanting into the insulating film from the upper surface portion of the insulating film to a depth that does not reach the valley portion. Effect transistor manufacturing method.