JPH05109906A - Production of semiconductor device - Google Patents

Abstract

PURPOSE:To remove conductor on a fine step difference part on an interlayer insulating film and prevent short-circuit of second wiring by plasma etching the conduction using the mixed gas of CxF2x+2 gas and inactive gas at a process of etching an insulating film at a constant speed. CONSTITUTION:An insulating film 12 is formed on a silicon substrate 11 and Al alloy is formed by sputtering, etc., as a first wiring 13 layer. An interlayer insulating film 14 is deposited on first wiring by plasma TEO and a hole is formed by photolithography. W17 is deposited as conductive material. The deposited W17 and the interlayer insulating film are etched at an almost constant speed. As for the etching gas, reacting gas and inactive gas are mixed. The combinations of the reacting gas and the inactive gas are: C2F6 gas and Ar gas, CF4 gas and He gas, C3F8 gas and Xe gas. Thus, the reliable multilayer interconnection without a step difference is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to an etchback method for forming a wiring.

[0002]

2. Description of the Related Art FIG. 5 is a sectional view showing main steps of a conventional method for manufacturing a semiconductor device.

In the conventional wiring process, as shown in FIG. 5, a first wiring 13 is formed by a sputtering process and then by a photolithography process, and then an interlayer insulating film 14 is formed by CVD (Chemi).
Cal Vapor Deposition).

Further, the contact hole 15 is formed in the interlayer insulating film by the photolithography process so as to reach the first wiring, and the second wiring 16 is further formed by the photolithography process after being formed by the sputtering process.

In general, it is difficult to form a metal by a sputtering process because a metal around a hole is poorly attached to the metal. Therefore, recently, as shown in FIG. 6, after forming the contact hole 15, the conductor 17 is formed by CVD,
Etch back so that the conductor remains only in the hole,
Further, the second wiring 16 is formed by the sputtering process.

However, in the step of etching back so that the conductor remains only in the hole, the conductor remains in a fine step on the interlayer insulating film, which causes a short circuit of the second wiring. Therefore, it is difficult to say that the wiring is perfect.

[0007]

However, in the above-described method for manufacturing a semiconductor device, in the step of etching back so that the conductor remains only in the holes, the conductor remains in the fine steps on the interlayer insulating film. However, the second wiring may be short-circuited, and it is difficult to say that this is a complete wiring process. Further, if the etch back is increased so as not to cause a short circuit of the second wiring, the conductor cannot be left in the important hole, which is no different from the conventional wiring process. Therefore, this technique is only applied to small prototypes.

Therefore, the present invention solves such a problem. The conductor can be left in the hole, and the conductor remains in a fine step on the interlayer insulating film, so that the second wiring is short-circuited. It is an object of the present invention to provide an etch-back method for realizing wiring formation that does not lead to the above.

[0009]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming an insulating film on a first wiring, and a step of forming a contact hole reaching the first wiring in the insulating film. In the step of forming a conductive material and the step of etching back the conductor and the insulating film at a constant rate, the step of simultaneously etching back the conductor and the insulating film is C _X F
It is characterized by performing plasma etching with a mixed gas of _{2X + 2} gas and an inert gas.

The inert gas is Ar gas.

The inert gas is He gas.

The inert gas is Xe gas.

[0013]

[Function] By conducting plasma etching with a mixed gas of C _X F _{2X + 2} gas and an inert gas, the conductor and the interlayer insulating film can be etched back at a constant speed at the same time, and the conductor at the step portion of the interlayer film can be removed. Since it can be removed at the same time as the interlayer film, it is possible to planarize and leave the conductor in the hole.

[0014]

EXAMPLE This example will be described in detail below. 1 to 3 show the structure of the etching apparatus used in this embodiment. 1
Is a reaction chamber, 2 is an electrode, 3 is a wafer, 4 is an exhaust hole, 5 is a gas supply hole, 6 is a high frequency power supply, 7 is a microwave power supply, and 8
Indicates a magnetic field coil. Further, FIG. 4 is a sectional view showing the main steps of the present invention. 11 is a silicon substrate, 12 is an insulating film, 13
Is a first wiring, 14 is an interlayer insulating film, 15 is a contact hole, 16 is a second wiring, 17 is a conductor, and 18 is a photoresist.

The embodiments will be described in detail below.

First, an insulating film 12 is formed on a silicon substrate 11, and an AL alloy is formed as a first wiring 13 layer by sputtering to have a thickness of 500 nm, for example. At this time, various devices and wirings may be formed under the insulating film 12, but they are not described here. Next, the material of the first wiring 13 is processed into a wiring by a photolithography process. Further, as shown in FIG. 4B, a SiO ₂ film is formed on the first wiring as an interlayer insulating film 14 by CVD using plasma TEOS.
The hole 15 is deposited by 0 nm and further processed by a photolithography process to form a hole 15 with a diameter of 0.5 μm, for example. Figure 4
(C) After that, W is deposited as a conductor 17 material by CVD on the hole formed. At this time, the deposition film thickness is preferably about 0.7 times the diameter of the hole or more so that no step is formed on the hole. Since the hole diameter is 0.5 μm, the deposition is performed with a thickness of 800 nm. FIG. 4D shows that the deposited W17 has a thickness of 800 nm, the interlayer insulating film 15 has a thickness of 500 nm, which is the sum of 500 nm, and 1.3 μm. Etch back in. The etching conditions at this time will be described in more detail after the description of the process flow. FIG. 4 (e) Finally, an AL alloy is formed as a second wiring 16 layer on the etched back W17 and the interlayer insulating film 15 by sputtering to have a thickness of, for example, 500 nm, and the material of the second wiring 16 is processed by a photolithography process. Wiring. 4 (f) By repeating this process, a highly reliable multilayer wiring is formed. FIG. 4 (g) The wiring processed in this manner is an extremely flat article having no step especially in the second wiring.

Next, the etching back step, which is an etching back step, will be described in more detail with respect to the conditions under which the W and the interlayer film are etched back at substantially the same speed. It shows the configuration of the device called. C ₂ F ₆ gas and Ar gas were used as reaction gases in this apparatus, respectively.
SCCM, 40SCCM flow, vacuum degree 180mTorr
While keeping at r, a high frequency (13.56 MHz) was applied to the 6-inch wafer at 900 Watts to etch back W as the conductor 17 and SiO ₂ as the interlayer insulating film.

As shown in Table 1, the W etching rate is 635 nm / min, the in-plane uniformity of the wafer is 3.5%, and the SiO ₂ etching rate is 613.
nm / min and a wafer in-plane uniformity of 2.3% could be obtained.

Table 1 Gas C ₂ F ₆ 100 SCCM Ar 40 SCCM Trueness 180 mTorr RF power 900 Watts W Etch rate 635 nm / min Uniformity 3.5% Interlayer film etch rate 613 nm / min Uniformity 2 .3% Next, an example of the second etchback will be described. The etching apparatus shown in FIG. 2 shows the structure of an apparatus generally called an electroton cyclotron resonance etching (hereinafter referred to as ECR). CF ₄ was used as a reaction gas in this device.
Gas and He gas are 120SCCM and 60S, respectively
Flow CCM, maintain vacuum at 10 mTorr, and high frequency (13.56 MHz) 150 Wa for 6 inch wafer.
Apply tts and apply microwave (2.45 GHz) to 200
Watts was applied to etch back W as the conductor 17 and SiO ₂ as the interlayer insulating film.

As shown in Table 2, the etching rate of W is 776 nm / min, the in-plane uniformity of the wafer is 2.5%, and the etching rate of SiO ₂ is 769.
It was possible to obtain nm / min and a wafer in-plane uniformity of 2.2%.

Table 2 Gas CF ₄ 120 SCCM He 60 SCCM Trueness 10 mTorr RF Power 150 Watts μ Wave Power 200 Watts W Etching Rate 776 nm / min Uniformity 2.5% Interlayer Film Etching Rate 769 nm / min Average Uniformity 2.2% Next, an example of the third etchback will be described. The etching apparatus of FIG. 3 shows the configuration of an apparatus generally called magnetron enhancement reactive ion etching (hereinafter referred to as MERIE). C3F8 gas and Xe gas were used as reaction gases in this device at 150 SC each.
CM, 80 SCCM flow, vacuum degree kept at 100 mTorr, high frequency (13.56 MHz) applied at 350 Watts on 6 inch wafer, magnetic field applied at 125 Gauss, W as conductor 17 and S as interlayer insulating film
The iO ₂ was etched back.

Table 3 Gas C ₃ F ₈ 150 SCCM Xe 80 SCCM Trueness 100 mTorr RF power 250 Watts Magnetic field 125 Gauss W Etch rate 753 nm / min Uniformity 3.8% Interlayer film etch rate 734 nm / min Uniformity 3.4% The result shows that as shown in Table 3, the etching rate of W is 7%.
53 nm / min, wafer in-plane uniformity of 3.8
%, SiO ₂ etching rate is 734 nm / mi
n, it was possible to obtain 3.4% as the in-plane uniformity of the wafer.

As described above, in various etching mechanism devices, W is used as the conductor 17 and SiO ₂ is used as the interlayer insulating film in the C _X F _{2X + 2} gas and the inert gas He,
It was found that the etch back process can be performed with Ar and Xe. Further, it has been found that the etch back treatment can be performed by the combination of these C _X F _{2 X + 2} gas and the inert gas He, Ar, and Xe.

[0024]

As described above, according to the present invention, C _X
Etchback treatment is possible with a combination of F _{2 X + 2} gas and an inert gas of He, Ar, and Xe. Further, the wiring processed in this way is an extremely flat article having no step especially in the second wiring, and it becomes possible to form a highly reliable multilayer wiring.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a structure of an etching apparatus used in an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a structure of an etching apparatus used in an embodiment of the present invention.

FIG. 3 is a configuration diagram showing a structure of an etching apparatus used in an example of the present invention.

FIG. 4 is a sectional view of a main process showing an embodiment of the present invention.

FIG. 5 is a cross-sectional view of main steps showing a conventional example.

FIG. 6 is a sectional view showing main steps of a conventional example.

[Explanation of symbols]

 1 ... Reaction chamber 2 ... Electrode 3 ... Wafer 4 ... Exhaust hole 5 ... Gas supply hole 6 ... High frequency power supply 7 ... Microwave power supply 8 ... Magnetic field coil 11 ...・ ・ Silicon substrate 12 ・ ・ ・ Insulating film 13 ・ ・ ・ First wiring 14 ・ ・ ・ Interlayer insulating film 15 ・ ・ ・ Contact hole 16 ・ ・ ・ Second wiring 17 ・ ・ ・ Conductor 18 ・ ・ ・ Photo Resist

Claims (4)

[Claims] 1. A step of forming an insulating film on a first wiring, a step of forming a contact hole reaching the first wiring in the insulating film, a step of forming a conductive material, the conductor and the In the step of etching back the insulating film at a constant speed, the step of simultaneously etching back the conductor and the insulating film is
A method of manufacturing a semiconductor device, which comprises performing plasma etching with a mixed gas of C _X F _{2X + 2} gas and an inert gas. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the inert gas is Ar gas. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the inert gas is He gas. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the inert gas is Xe gas.