JPH05108305A - Elastic memory circuit - Google Patents

Abstract

PURPOSE:To perform a correct clock switching operation even if the writing timing and the reading timing are overlapping with each other. CONSTITUTION:A write signal generating circuit 22 produces the multiphase pulses WC1-WCn based on a write clock WCLK. The write date WDTA are stored in a storage part in a serial/parallel converter circuit 23 and then outputted with use of the pulses WC1-WCn. Meanwhile a read signal generating circuit 25 produces the multiphase pulses RC1-RCn based on a read clock RCLK and then latches the serial/parallel conversion output into a flip-flop 26 with use of the pulses RC1-RCn. Then a parallel/serial converter circuit 28 reads successively the data WDTA synchronously with the clocks of the receiver side and inputs them to a multiplexing device 13 of the receiver side in a bit serial way. Under such conditions, a phase comparator 27 compares the 1st and 2nd pulses WC1 and RC1 with each other and shifts the phase of the pulse RC1 when both purses are overlapping with each other. So that the pulses WC1 and RC1 are never overlapping with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an elastic memory circuit, and more particularly to an elastic memory circuit which reads transmission data on a sending side with a clock on a receiving side and changes the clock.

[0002]

2. Description of the Related Art As shown in FIG. 7, a conventional elastic memory circuit for switching clocks between transmission devices or the like sequentially generates a write address signal every time a write clock WCLK is input after a write timing pulse WTMP is generated. A write address generating circuit 1 for generating AD1, AD2, ... ADn, a DRAM 2 for writing write data WDTA bit by bit in a storage area indicated by the write address, and a read timing pulse RTMP
In synchronization with the read address signals AD1 ', AD2', ... A each time the read clock RCLK is input.
Dn 'is generated, and D indicated by the read address signal is generated.
The read address generating circuit 3 reads data from the storage area of the RAM 2.

Reference numeral 4 is a sending side multiplex converter, which receives the transmission data and is synchronized with the sending side clock output from the clock generator 5 to write timing pulse WTM.
P, write clock WCLK, write data WDT
Output A. Reference numeral 6 denotes a receiving side multiplex / conversion device that sends out transmission data in synchronization with the receiving side clock.
Data is read from the DRAM 2 by generating a read timing pulse RTMP and a read clock RCLK in synchronization with the receiving side clock output from.

According to the elastic memory circuit of FIG. 7, the transmission data WDTA is transferred to the DRAM 2 at the sending side clock.
To the DRAM 2 and write the transmission data to the DRAM 2 at the receiving side clock.
Read from and change the clock.

[0005]

Therefore, as shown on the left side of the time chart of FIG. 8, the data read timing pulse RTMP from the DRAM 2 is delayed by one clock from the data write timing pulse WTMP to the DRAM 2. In this case (one clock or more), the written data can be correctly read bit by bit and the clock can be changed.

However, if the read clock RCLK is disturbed and the number of read clocks RCLK is increased by one as shown in the PDA of FIG. 8 for some reason, the phase of the next read timing pulse RTMP and the write timing pulse WTMP are increased. The phases match. In such a case, since data writing and reading are performed at the same time, the read data may be data before writing or data after writing (hatched portion in the figure).
It is impossible to correctly read the written data bit by bit and change the clock. That is, conventionally, when the write timing and the read timing match, there is a problem that the data cannot be accurately read and the clock cannot be changed correctly.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an elastic memory circuit capable of correctly changing clocks even when the write timing and the read timing overlap.

[0008]

FIG. 1 illustrates the principle of the present invention. Reference numeral 10 is an elastic memory circuit for reading the transmission data on the sending side with the clock on the receiving side to change the clock, 11 is a sending side multiplex converter, 13 is a receiving side multiplex converter, and 22 is a write timing pulse WT.
A write signal generation circuit for generating first multi-phase pulses (write signals) WC1 to WCn based on MP and the write clock WCLK, and 23 is write data WDTA.
Is a serial-parallel conversion circuit that performs serial-parallel conversion using first multi-phase pulses WC1 to WCn, and 25 is a read signal that generates second multi-phase pulses (read signals) RC1 to RCn based on the read clock RCLK. A generator circuit, 26 is a second multiphase pulse RC1-RCn
A flip-flop 27 for latching data from the serial-to-parallel conversion circuit by means of 27 compares the phases of the first multiphase pulse RC1 and the second multiphase pulse WC1, and these first and second multiphase pulses are mutually compared. A phase comparison circuit 28 is controlled so as not to overlap, and a para-serial conversion circuit 28 performs parallel-serial conversion of the data latched in the flip-flop by the read timing pulse RTMP output from the receiving side multiplex conversion device 13.

FIG. 2 is a diagram for explaining the second principle of the present invention.
10 is an elastic memory circuit that reads the transmission data on the sending side with the clock on the receiving side and changes the clock, 11 is a sending side multiplex converter, 13 is a receiving side multiplex converter, and 32 is a sending side multiplex converter. Two frames (for example, 16 frames) are output using the output write clock WCLK.
Write address signal WADR (AD1 to AD1)
ADn, AD1 'to ADn'), a write address generating circuit, 33 is a write address signal WA for the write data WDTA output from the sending side multiplex / conversion device.
A DRAM, which is stored in a storage area designated by DR and holds for two frame periods, is a read address signal RADR for two frames (for example, 16 bits) using a read clock RCLK output from the receiving side multiplex conversion device 13.
A read address generation circuit for generating (AD1 to ADn, AD1 'to ADn') and reading data from the storage area of the DRAM 33 designated by the read address signal, 36
Is a phase comparison circuit that monitors the phases (timings) of the write address signal WADR and the read address signal RADR and controls so that these phases do not match.

[0010]

In the first invention, the write signal generating circuit 2
2 generates first multi-phase pulses WC1 to WCn based on a write clock WCLK (same as the sending clock) and a write timing pulse WTMP, and the multi-phase pulses WC1 to WCn convert write data WDTA to serial-parallel conversion. The data is stored / outputted in the storage unit built in the circuit 23 and serial / parallel converted. On the other hand, the read signal generation circuit 25 uses the read clock RCLK (which is the same as the receiving clock) to generate the second multiphase pulses RC1 to RCn.
Is generated and the multiphase pulses RC1 to RCn
The parallel conversion output data is latched in the flip-flop 26, and the parallel-serial conversion circuit 28 outputs the data from the read timing pulse RT output from the receiving side multiplex conversion device 13.
Sequential reading is performed based on MP, parallel-serial conversion is performed, and bit-serial is input to the receiving-side multiplexer in synchronization with the receiving-side clock. In this case, the phase comparison circuit 27 has the first
The phases of the multi-phase pulse WC1 and the second multi-phase pulse RC1 are compared, and when the first and second multi-phase pulses overlap, the phases of the second multi-phase pulse are shifted so that they do not overlap each other. Control.

As described above, according to the first aspect of the present invention, the timing of writing to the serial-parallel conversion circuit and the timing of latching and reading by the flip-flop are shifted, and the data is read bit-serially from the flip-flop to the receiving side multiplex converter. Since the timings of writing and reading do not coincide with the input, the clock can be changed accurately.

In the second aspect of the invention, the write address generation circuit 32 uses the write clock WCLK (same as the send clock) output from the send side multiplex / conversion device 11 to write address signals WADR (ADR for two frames.
D1 to ADn, AD1 'to ADn') are generated and the write data WDTA output from the sending side multiplexer / converter is stored bit by bit in the storage area of the DRAM 33 designated by the write address signal WADR and held for 2 frame periods. .. On the other hand, the read address generation circuit 35 outputs the read clock RCLK output from the receiving side multiplex converter 13.
(Same as the receiving clock), read address signals RADR (AD1 to ADn, AD1 'to 2 frames) for two frames are used.
ADn ') is generated, data is read bit by bit from the storage area of the DRAM 33 designated by the read address signal, and the data is serially input to the receiving side multiplex conversion device 13. In this case, the phase comparison circuit 36 monitors the phases of the write address signal WADR and the read address signal RADR, and when these phases match, the read address signal is delayed by one frame and the data is read from the DRAM 23.

As described above, in the second invention, DR
The timing of writing data to the AM and the timing of reading data from the DRAM are shifted, the data is read bit serially from the DRAM and input to the receiving side multiplex conversion device, and the read timing is set to 1 when the write and read timings match. DR with a frame delay
Since the data is read from the AM, the clock can be changed accurately.

[0014]

【Example】

(a) Overall configuration of the first embodiment of the present invention FIG. 3 is a configuration diagram of the first embodiment of the present invention, and FIG. 4 is a time chart for explaining the operation, wherein one frame has 8 bits. In FIG. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals, 10 is an elastic memory circuit for reading the transmission data of the sending side with the clock of the receiving side and changing the clock, and 11 is receiving the transmission data. Then, 12 is a clock generator for generating a clock on the sending side, and 12 is a clock generator for generating the clock on the sending side, which is the sending side multiplex converter for outputting the write data (transmission data) WDTA, the write timing pulse WTMP, and the write clock WCLK. Is the same as.

13 is a read timing pulse RTMP
And output the read clock RCLK and data R
The receiving side multiplex / conversion device that takes in and sends out DTA, and 14 is a clock generator that generates a receiving side clock, and the read clock RCLK and the receiving side clock are the same.

Reference numeral 15 denotes a counting circuit which is reset by the read timing pulse RTMP, counts the read clocks RCLK generated thereafter, and is reset to 0 by the read timing pulse RTMP after counting eight. 16 is a decoder,
The count value of the counting circuit 15 is decoded and the read signals RS _{1 to} RS ₈ which become “1” are sequentially output to the _eight signal lines.

Elastic Memory Circuit In the elastic memory circuit 10, 22 is a write signal generating circuit, which is a counting circuit 22a and a decoder 22.
b. The counting circuit 22a uses the write timing pulse WTM output from the sending side multiplex converter 11.
It is reset by P, and the number of write clocks WCLK generated thereafter is counted, and is reset to 0 by the write timing pulse WTMP every time eight clocks are counted.
The decoder 22b is a count value of the counting circuit 22a (3 bits)
Is decoded and multiphase pulses (write signals) WC _{1 to} WC ₈ are sequentially generated on the _eight signal lines.

Reference numeral 23 is a first multiphase pulse WC for the write data WDTA output from the sending side multiplex converter 11.
_{1 to} WC ₈ for serial / parallel conversion
It is a para conversion circuit. The serial-para conversion circuit 23 is composed of a demultiplexer 23a having a built-in flip-flop,
The write data WDTA input bit-serially is sequentially stored in the flip-flops corresponding to the multiphase pulses WC _{1 to} WC ₈ , and each one frame is stored and output.

Reference numeral 25 is a read signal generating circuit, which has a counting circuit 25a and a decoder 25b. Counting circuit 2
Reference numeral 5a denotes a capacitor 8 which counts the read clock RCLK output from the receiving-side multiplex converter 13 and counts from 0 again every eight counts. The decoder 25b sequentially generates a counting circuit 25a of the count value (3 bits) to the eight signal lines to decode the multi-phase pulse (read signal) RC ₁ to RC _8.

Reference numeral 26 designates _eight flip-flops for sequentially latching the 8-bit data output from the serial-parallel conversion circuit 23 by the second multiphase pulses RC _{1 to} RC ₈ .
27 compares the phases of the first multi-phase pulse WC ₁ and the second multi-phase pulse RC ₁ , and when the phases overlap, the counting circuit 2
5a is a phase comparison circuit that resets the count value of 5a to a predetermined value and controls so that the first and second multiphase pulses do not overlap each other.

Reference numeral 28 denotes a para-serial conversion circuit, which sequentially latches the data latched in the flip-flop 26 based on the read signals RS _{1 to} RS ₈ output from the decoder 16.
Multiplexer 2 that outputs bit-by-bit serially
8a.

Overall Operation (1) When the Phases of the First and Second Multi-Phase Pulses Do Not Match The write signal generation circuit 22 writes the write clock WCL.
Based on K (same as the clock on the sending side) and the write timing pulse WTMP, the first multi-phase pulses WC _{1 to} W
C ₈ is generated, and the write data WDTA is stored in a flip-flop (not shown) built in the serial-parallel conversion circuit 23 by the multiphase pulses WC _{1 to} WC _{8 and} output in parallel (serial-parallel conversion in FIG. 4). See output).

On the other hand, the read signal generating circuit 25 reads
Based on the clock RCLK (same as the receiving clock)
Second multiphase pulse RC₁~ RC₈Generate the polyphase
Pulse RC₁~ RC₈Siri-Para conversion output data by
Latch in the flip-flop 26, and the parallel-serial conversion circuit
28 is a read signal RS output from the decoder 16 ₁
~ RS₈Stored in the flip-flop 26 based on
Data is read sequentially and converted to parallel / serial
The receiver multiplexer 13 in synchronization with the receiver clock.
Input to serial.

(2) When the phases of the first and second multi-phase pulses match, during the above operation, the read clock RCLK is disturbed as shown by the PDA (see the dotted line frame) in FIG. 4 for some reason. When the number of read clocks RCLK is increased by one, the phases of the first multi-phase pulse WC ₁ and the second multi-phase pulse RC ₁ will overlap. In such a case, the serial-para conversion circuit 2
The change of the output of 3 and the latching of the data to the flip-flop 26 are performed almost at the same time. Therefore, the latched data cannot be correctly latched because the data before the change of the serial-parallel conversion output or the data after the change cannot be latched correctly, and the transfer of the clock of the transmission data cannot be performed correctly.

For this reason, the phase comparison circuit 27 is always set to the first
The phase of the multi-phase pulse WC ₁ and the phase of the second multi-phase pulse RC ₁ are compared, and if the first and second multi-phase pulses overlap, the count value of the counting circuit 25a of the read signal generating circuit 25 is Reset to the specified value and set the phase of the second multi-phase pulse to Ps
By a minute (see dotted lines in each of the multiphase pulses RC _{1 to} RC ₈ in FIG. 8). As a result, the phases of the first and second multi-phase pulses WC _{1 to} WC ₈ and RC _{1 to} RC ₈ do not overlap, and the data after the change in the serial-parallel conversion output can be reliably latched in the flip-flop 26 and received. The data can be read out bit-serially in synchronization with the clock on the side, and the clock of the transmission data can be changed correctly.

The structure when the transmission speeds of the sending side and the receiving side are taken into consideration.
In the configuration shown in FIG. 3, the transmission speeds of the sending side and the receiving side are not taken into consideration. However, in the case where both the sending side and the receiving side are low-order group multiplex converters, both the sending side and the receiving side are high-order group multiplex converters. The elastic memory circuit of the present invention can be applied as it is. The elastic memory circuit shown in FIG. 3 is also provided for each low-order group multiplex conversion device, and the data from each elastic memory circuit can be multiplexed and sent out by the high-order group multiplex conversion device.

(B) Overall configuration of the second embodiment of the present invention FIG. 5 is a configuration diagram of the second embodiment of the present invention, and FIG. 6 is a time chart for explaining the operation, wherein one frame has 8 bits. .. 5, the same parts as those in FIG. 2 are denoted by the same reference numerals, 10 is an elastic memory circuit for reading the transmission data of the sending side with the clock of the receiving side and changing the clock, 11 is the receiving of the transmission data Then, 12 is a clock generator for generating a clock on the sending side, and 12 is a clock generator for generating the clock on the sending side, which is the sending side multiplex converter for outputting the write data (transmission data) WDTA, the write timing pulse WTMP, and the write clock WCLK. Is the same as.

13 is a read timing pulse RTMP
And output the read clock RCLK and data R
The receiving side multiplex / conversion device that takes in and sends out DTA, and 14 is a clock generator that generates a receiving side clock, and the read clock RCLK and the receiving side clock are the same.

Elastic Memory Circuit In the elastic memory circuit 10, 31 is a 1/2 frequency divider circuit which doubles the write timing pulse WTMP output from the sending side multiplex converter 11 and outputs a pulse WTMP ', 32 Is a write address generation circuit that generates a 4-bit write address signal WADR, and the output pulse WTMP ′ of the 1/2 frequency divider circuit 31.
Is reset by the write clock WCL
Count K and write address signal WADR of 4 bits
It has a counting circuit for outputting. Since the write address signal WADR is 4 bits, the addresses AD1 to AD8, AD1 'for 2 frames (16 bits) are included.
~ AD8 'can be generated.

Numeral 33 is a write address signal WAD for the write data WDTA output from the sending side multiplexer.
A DRAM which stores in the storage area designated by R and holds it for two frame periods is a 1/2 frequency dividing circuit which doubles the read timing pulse RTMP output from the receiving side multiplex converter 13 and outputs a pulse RTMP '. Is.

Reference numeral 35 indicates a read address signal RADR (AD1 to AD) for 2 frames of 4 bits which is obtained by dividing the read clock RCLK output from the receiving side multiplex / conversion device 13.
Dn, AD1 'to ADn'), which is a read address generating circuit for reading data from the memory area of the DRAM designated by the read address signal, and is reset by the output pulse RTMP 'of the 1/2 frequency dividing circuit 34. At the same time, it has a counting circuit that counts the read clock RCLK and outputs a 4-bit read address signal RADR. Since the read address signal RADR has 4 bits, the addresses AD1 to AD8 and AD1 'to AD8' for 2 frames (16 bits) can be generated.

Reference numeral 36 monitors the phase (timing) of the write address signal WADR and the read address signal RADR, and, for example, the write and read pulse WTMP ', of the double cycle output from the 1/2 frequency divider circuits 31, 34.
When the phases of RTMP 'are compared with each other, and when the phases match or overlap, the count value of the 1/2 frequency dividing circuit 34 is decreased by 1, the phase of the read pulse RTMP' is delayed by one frame period, and the phases match. It is a phase comparison circuit that prevents overlapping.

Overall Operation (1) When the Phases of the Pulses WTMP 'and RTMP' Do Not Match The write address generation circuit 32 is a 1/2 frequency divider circuit 31.
Write cycle pulse W of double cycle output from
After the TMP 'is generated, every time a write clock WCLK (same as the feed clock) is output from the sending side multiplexer / conversion device 11, a 4-bit write address signal WADR is sequentially output.
(AD1 to ADn, AD1 'to ADn') are generated and write data W output from the sending side multiplex conversion device 11 is generated.
DTA is stored bit by bit in the storage area of the DRAM 33 designated by the write address signal WADR and held for two frame periods.

On the other hand, the read address generation circuit 35
After generation of the read timing pulse RTMP ′ having a double cycle output from the ½ frequency dividing circuit 34, 4 bits are sequentially output every time the read clock RCLK (which is the same as the receive clock) is output from the receive multiplex converter 13. Read address signal RADR (AD1 to ADn, AD1 'to AD
n ') is generated and D indicated by the read address signal is generated.
Data is read from the storage area of the RAM 33 bit by bit and serially input to the receiving side multiplex conversion device 13.

(2) When the phases of the pulses WTMP 'and RTMP' coincide or overlap, during some of the above operations, the read clock RCLK is disturbed as shown by the PDA (see the dotted line frame) in FIG. 6 for some reason. When the number of the read clocks RCLK is increased by one, the write and read timing pulse WTMP ′ of the double cycle,
The phases of RTMP 'overlap. In such cases,
Since data writing to the DRAM 33 and data reading from the DRAM 33 are performed at the same time, the read data becomes the data before writing or the data after writing (hatched portion), and the written data is bit by bit. It becomes impossible to read correctly and change the clock.

For this reason, the phase comparison circuit 36 always keeps the write and read timing pulse WTM of a double cycle.
The phases of P'and RTMP 'are compared, and if they match or overlap, the count value of the 1/2 frequency dividing circuit 34 is decreased by 1,
The phase of the read pulse RTMP 'is delayed by one frame period as shown in FIG. As a result, the phases of the write and read timing pulses WTMP 'and RTMP' do not coincide or overlap, and the data writing to the DRAM 33 and the data reading from the DRAM 33 can be performed at different timings and synchronized with the receiving side clock. Data can be read out in bit serial,
It is possible to correctly change the clock of transmission data.

The present invention has been described above with reference to the embodiments.
The present invention can be variously modified according to the gist of the present invention described in the claims, and the present invention does not exclude these modifications.

[0038]

As described above, according to the present invention, the data is expanded from the serial-parallel conversion circuit, and the timing of writing in the storage section of the serial-parallel conversion circuit and the timing of latching and reading the data in the flip-flop are shifted from each other. Since the data is read bit serially and input to the receiving side multiplex converter, the phases of writing and reading (timing) are compared, and the phases are not matched, it is possible to accurately change the clock. ..

Further, according to the present invention, the timing of writing data to the DRAM and the timing of reading data from the DRAM are shifted, the data is read bit serially from the DRAM and input to the receiving side multiplex conversion device, and the writing and reading are performed. When the timings match, the read timing is delayed by one frame to read the data from the DRAM, so that the clocks can be changed accurately.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a first principle of the present invention.

FIG. 2 is a diagram illustrating a second principle of the present invention.

FIG. 3 is a configuration diagram of a first embodiment of the present invention.

FIG. 4 is a time chart of the first embodiment.

FIG. 5 is a configuration diagram of a second embodiment of the present invention.

FIG. 6 is a time chart of the second embodiment.

FIG. 7 is a block diagram of a conventional elastic memory circuit.

FIG. 8 is a time chart of a conventional elastic memory circuit.

[Explanation of symbols]

 10 ... Elastic memory circuit 11 ... Send side multiplex converter 13 ... Receiving side multiplex converter 22 ... Write signal generation circuit 23 ... Serial parallel conversion circuit 25 ... Read signal generation circuit 26 ... Flip-flop 27 ... Phase comparison circuit 28. Para-serial conversion circuit 32 .. Write address generation circuit 33 .. DRAM 35 .. Read address generation circuit 36 .. Phase comparison circuit

Claims (2)

[Claims] 1. A write timing pulse (WTMP) output from a transmission side multiplex conversion device (11) in an elastic memory circuit (10) for reading transmission data on the transmission side with a clock on the reception side and changing clocks. ) And a write clock (WCLK) to generate _first multi-phase pulses (WC _{1 to} WCn), and a write data output from the sending side multiplexer / converter.
(WDTA) by the first multiphase pulse (WC _{1 to} WCn)
Serial-parallel conversion circuit for serial / parallel conversion (23)
And the read clock output from the receiving side multiplex converter (13)
A read signal generating circuit (25) for generating a second multi-phase pulse (RC _{1 to} RCn) based on (RCLK); and a second multi-phase pulse from the serial-para conversion circuit (23). Flip-flop that latches data (26)
And a phase comparison circuit (27) that compares the phases of the first multiphase pulse and the second multiphase pulse and controls so that these first and second multiphase pulses do not overlap each other, and a flip-flop ( The data latched in (26) is read timing pulse (R
Para-serial conversion circuit for parallel / serial conversion with TMP)
An elastic memory circuit comprising (28), wherein the data is read at the clock of the receiving side multiplex converter. 2. A write timing pulse (WTMP) output from a transmission side multiplex conversion device (11) in an elastic memory circuit (10) which reads transmission data on the transmission side with a clock on the reception side and changes the clock. 2) and write clock (WCLK)
The write address generation circuit (32) that generates the write address signal (WADR) for the frame and the write data (WDT) output from the sending side multiplex converter.
DRAM (33) that stores (A) in the storage area indicated by the write address signal (WADR) and holds it for two frame periods, read timing pulse (RTMP) and read clock output from the receiving side multiplex converter (13) (RCLK) is used to generate a read address signal (RADR) for two frames, and a read address generation circuit (35) for reading data from the storage area of the DRAM (33) designated by the read address signal, and a write address signal And an address memory which is equipped with a phase comparison circuit (36) that monitors the phase of the read address signal and controls so that these phases do not match, and the data is read by the clock of the receiving side multiplex converter (13). circuit.