JPH05102479A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a MOS FET structure with high driving capability and performance. CONSTITUTION:The channel region is provided with a first conductive region 2 whose conductivity type is opposite to that of the substrate; the source 8 and drain 7 regions are provided with a second conductive regions 6 deeper than the level of their pn junction. These conductive regions have a well region asymmetric with respect to the source 8 and the drain 7. This gives an MOS FET which has a high driving capability, a less substrate bias effect of threshold and a high punch-through breakdown voltage between the drain and the substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device structure.

[0002]

2. Description of the Related Art A conventional n-channel transistor will be described with reference to FIG. In FIG. 4, there is a gate electrode (12) on a p-type silicon substrate (10) via a gate oxide film (11), and n ^{+ in the} source / drain regions. A region (13) is formed.

[0003]

In the conventional MOSFET shown in FIG. 4, when a gate bias is applied, a depletion layer is formed in the channel. The depletion layer charge in this depletion layer strengthens the effective gate electric field and reduces carrier mobility. In addition, the gate electric field applied to the inversion layer is reduced, and the carrier concentration is reduced, which causes a reduction in driving ability.
Further, there is a problem that the threshold value increases when a substrate bias is applied (back gate bias effect).

[0004]

[Means for Solving the Problems] The depth of the well is changed between the channel portion and the source / drain diffusion layer portion so that it is shallow in the channel portion and deep in the source / drain diffusion layer portion. At this time, the depth of at least the source side region of the channel portion is made shallower than the sum of the gate depletion layer width and the well-substrate depletion layer width. The drain side region of the channel is
To prevent punch-through, make the channel deeper than the source side to make the channel part asymmetric. Further, the concentration of at least the source side region of the channel portion is made lower than the concentration of the diffusion portion.
As a result, the charge amount of the depletion layer of the MOSFET can be suppressed.

[0005]

According to the semiconductor device of the present invention, a MOSFET having a high carrier mobility and a high driving capability can be obtained. Further, it is possible to suppress the effect of increasing the threshold value when the substrate bias is applied. Further, by making the source and drain regions asymmetrical, a high punch-through breakdown voltage between the drain and the substrate can be obtained, and a large voltage can be applied to the drain electrode.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIGS.
A channel MOSFET will be described as an example. B ^{+ on} N-type silicon substrate (1) Is ion-implanted to form a first P well (2) having a depth of 0.1 μm, and then a 15 nm gate oxide film (3), a gate electrode (4) and a resist film (5) are formed. FIG. 1 is a schematic diagram of the result. The first p
The well (2) may be formed by epitaxial growth.

After that, As⁺ Drain by performing ion implantation
A diffusion layer (7) and a source diffusion layer (8) are formed. Furthermore
Using the gate electrode (4) and the resist film (5) as a mask
B⁺ Ion implantation is performed to make the second deeper than the first p-well.
Form a p-well. The schematic diagram up to this point is shown in Fig. 2.
It was In this case, the concentration of the second p-well (6) is
Make it darker than the p-well concentration. Further gate electrode
Drain diffusion using (4) and resist film (5) as a mask
B diagonal from membrane (7) side⁺ Ion implantation is performed and the first p
Of the p-layer in the intermediate region between the well (2) and the second p-well (6).
Increase the width (9). Then etch the resist film
It The schematic diagram up to this point is shown in FIG. This diagonal B
⁺ From the source side to the center of the channel during ion implantation
B in all channel regions⁺ Stoppy so that it does not enter
Choose a resist with high power, or B⁺ Io
The first p
Do not use any means such as setting the concentration of the well (2).
It shouldn't be.

The width yD on the drain side of the p well in the region where the first p well (2) and the second p well (6) intersect is determined by the gate depletion layer width W _g1 and the depletion layer by the silicon substrate (1). Choose to be greater than the sum of width W _s1 . That is, yD> W _g1 + W _{s10 and} the diagonal B ⁺ for creating a region corresponding to (9) in FIG. Ion implantation creates a second well B
⁺ It may be performed before the ion implantation.

In addition, the depth of the well is set to the channel portion and the source.
The drain diffusion layer is changed, and the channel is made shallow, and the source / drain diffusion layer is made deep. At this time, the depth of at least the source side region of the channel portion is made shallower than the sum of the gate depletion layer width and the well-substrate depletion layer width.

[0010]

As shown in FIGS. 1 to 3 of the embodiment of the present invention, the width yD of the first p-well of the channel portion on the drain side is yD.
Since yD> W _g1 + W _s1 is satisfied, the punch-through breakdown voltage between the drain and the substrate is improved. Further, since the width of at least the p-well of the channel portion on the source side is shallower than the sum of the gate depletion layer and the depletion layer width between the well and the substrate, the channel depletion layer charge of the MOSFET is Si substrate (1). Of the voltage Vsub
By increasing the value, the charge of the channel depletion layer can be reduced. As a result, it can be expected that the high driving ability and the S factor are improved, and the substrate bias effect of the threshold value is reduced. Further, since the well region of the drain portion is widened, the punch-through breakdown voltage between the drain and the substrate is improved and a large drain voltage can be applied.

[Brief description of drawings]

FIG. 1 is a process sectional view illustrating the present invention.

2A to 2C are process cross-sectional views illustrating the present invention.

3A to 3C are process cross-sectional views illustrating the present invention.

FIG. 4 is a sectional view of a conventional n-channel MOSFET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... 1st p well 3 ... Gate insulating film 4 ... Gate electrode 5 ... Resist film 6 ... 2nd p well 7 ... Drain diffusion region 8 ... Source diffusion region 9 ... It is made for asymmetry. Well region 10 ... Silicon substrate 11 ... Gate insulating film 12 ... Gate electrode 13
… Source / drain diffusion regions

Claims (5)

[Claims] 1. A channel region of a MOSFET has a first conduction region opposite to a substrate, and a diffusion region of a source / drain has a second conduction region deeper than the depth of its pn junction. The depth of the conduction region is changed in the channel part and the source / drain diffusion layer part, and it is made shallow in the channel part and deep in the source / drain diffusion layer part, and the depth of the source side region is at least the channel part. A semiconductor device which is shallower than the sum of the width of the gate depletion layer and the width of the depletion layer between the well and the substrate, and these conductive layers have an asymmetric structure with respect to the source / drain. 2. The drain-side width yD of the conductive region in the region where the first conductive region and the second conductive region intersect with each other,
2. The semiconductor device according to claim 1, wherein there is a relationship of yS <yD between the source-side width yS of the conductive region in the region where the conductive region of 1) and the second conductive region intersect. 3. The channel depletion layer width W _{g1 depending on the} gate voltage
2. The semiconductor device according to claim 1, wherein there is a relation of yD> W _g1 + W _s1 with the depletion layer width W _s1 in the first conduction region depending on the semiconductor substrate voltage. 4. A first conduction region is formed by ion implantation or epitaxy growth, then a second conduction region is formed by ion implantation, and the first conduction region is made asymmetric by an oblique ion implantation method. The method for manufacturing a semiconductor device according to claim 1, wherein 5. A first conduction region is formed by ion implantation or epitaxy growth, and then the first conduction region is made asymmetric by an oblique ion implantation method, and further, a second conduction region is formed by ion implantation. The method for manufacturing a semiconductor device according to claim 1, wherein