JPH05102207A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH05102207A JPH05102207A JP3263580A JP26358091A JPH05102207A JP H05102207 A JPH05102207 A JP H05102207A JP 3263580 A JP3263580 A JP 3263580A JP 26358091 A JP26358091 A JP 26358091A JP H05102207 A JPH05102207 A JP H05102207A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- hole
- paste
- die pad
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、例えば半導体装置等の
電子制御装置の組立用部材であるリードフレームに関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame which is an assembly member for an electronic control device such as a semiconductor device.
【０００２】[0002]
【従来の技術】近年、半導体素子の大型化やハイブリッ
ドＩＣ技術の拡大などの影響で、半導体パッケージの構
成部材として用いられるリードフレームのダイパッドが
大型化していく傾向にある。また一方では、近年、半導
体素子を高密度に実装することが求められており、この
実装の高密度化を図るため、半導体パッケージの小型化
及び薄形化がますます強く進められている。2. Description of the Related Art In recent years, the size of semiconductor elements and the expansion of hybrid IC technology have led to an increase in the size of die pads of lead frames used as constituent members of semiconductor packages. On the other hand, in recent years, there has been a demand for high-density mounting of semiconductor elements, and miniaturization and thinning of a semiconductor package are being strongly promoted in order to increase the packing density.
【０００３】ところで、このようなダイパッドの大型化
やパッケージの薄形化は、リードフレーム及び半導体素
子が樹脂封止される際、リードフレームとモールド樹脂
との密着性を低下させる原因となっている。この密着性
が低下すると、「パッケージクラック」と呼ばれるモー
ルド樹脂の割れが発生してしまうことがある。このパッ
ケージクラックの対策として、従来、ＱＦＰ（Quad Fla
t Package）やＴＳＯＰ（Thin Small OutlinePackage）
に使われるリードフレームのダイパッドには、モールド
樹脂との密着性を向上させるために、貫通孔を設けると
いった対策を講じている。By the way, such an increase in the size of the die pad and a reduction in the thickness of the package cause a decrease in adhesion between the lead frame and the molding resin when the lead frame and the semiconductor element are resin-sealed. .. If this adhesiveness is lowered, cracking of the mold resin called "package crack" may occur. As a countermeasure against this package crack, QFP (Quad Fla
t Package) and TSOP (Thin Small Outline Package)
For the die pad of the lead frame used for, the through hole is provided to improve the adhesion with the mold resin.
【０００４】[0004]
【発明を解決しようとする課題】しかしながら、リード
フレームのダイパッドに貫通孔を設けた場合には、その
リードフレームに半導体素子を搭載するためのダイボン
ディング工程を行う際、接着剤として広く用いられてい
るペーストの一部がこの貫通孔に流れ込むという現象が
生じる。すなわち、図１２（ａ）に示すようにリードフ
レーム１のダイパッド２には貫通孔３が形成されてお
り、このダイパッド２上に半導体素子５をダイボンディ
ングするためのペースト６を塗布し、その上に半導体素
子５を搭載する。このとき、ペースト６の余剰分がダイ
ボンディング時の押圧荷重により貫通孔３内にはみ出さ
れるようになり、ひいてはダイパッド２の裏面までまわ
り込んでしまう場合もある。However, when a through hole is provided in the die pad of the lead frame, it is widely used as an adhesive agent when performing a die bonding process for mounting a semiconductor element on the lead frame. The phenomenon that a part of the existing paste flows into this through hole occurs. That is, as shown in FIG. 12A, a through hole 3 is formed in the die pad 2 of the lead frame 1, and a paste 6 for die bonding the semiconductor element 5 is applied onto the die pad 2 and then the die pad 2 is coated therewith. The semiconductor element 5 is mounted on. At this time, the surplus portion of the paste 6 comes to be extruded into the through hole 3 due to the pressing load at the time of die bonding, and may even reach the back surface of the die pad 2.
【０００５】このようなペースト６の余剰分のはみ出し
により、ダイパッド２の裏面の平坦性が損なわれ、この
ため次の工程であるワイヤーボンディング工程において
ヒートコマとウインドクランパーとによるリードフレー
ム１の固定が不十分となる。リードフレーム１が十分に
固定されないと、ボンディング不良が生じてしまうおそ
れがある。The surplus portion of the paste 6 impairs the flatness of the back surface of the die pad 2, and thus the lead frame 1 is not fixed by the heat coma and the wind clamper in the next wire bonding step. Will be enough. If the lead frame 1 is not sufficiently fixed, there is a risk of defective bonding.
【０００６】また、貫通孔３内に流れ出たペーストによ
り、リードフレーム１とモールド樹脂との密着性が低減
してしまい、密着性を向上させるために設けられた貫通
孔３の本来の機能が十分に発揮することができなくなっ
てしまう場合がある。この結果、せっかく貫通孔を設け
てパッケージクラックの対策を講じても、パッケージク
ラックの発生頻度を効果的に低減させることができなく
なってしまう。Further, the paste flowing out into the through hole 3 reduces the adhesion between the lead frame 1 and the molding resin, and the original function of the through hole 3 provided for improving the adhesion is sufficient. In some cases, it may not be possible to exert it. As a result, even if a through hole is provided to take measures against package cracks, the frequency of occurrence of package cracks cannot be effectively reduced.
【０００７】本発明は、このような問題に鑑みてなされ
たものであって、その目的は、半導体素子等の電子制御
部品をダイパッドへダイボンディングする際、ダイボン
ディング用ペースト等の接着剤が貫通孔へ流入するのを
回避することのできるリードフレームを提供することで
ある。The present invention has been made in view of the above problems, and an object thereof is to penetrate an adhesive such as a die bonding paste when die bonding an electronic control component such as a semiconductor element to a die pad. The purpose of the present invention is to provide a lead frame that can avoid flowing into the holes.
【０００８】[0008]
【課題を解決するための手段】前述の課題を解決するた
めに、本発明は、半導体素子等の電子制御部品を搭載す
るためのダイパッドを有するリードフレームにおいて、
前記ダイパッドに貫通孔が形成されているとともに、こ
の貫通孔の回りに溝が形成されていることを特徴として
いる。In order to solve the above-mentioned problems, the present invention provides a lead frame having a die pad for mounting an electronic control component such as a semiconductor element,
A through hole is formed in the die pad, and a groove is formed around the through hole.
【０００９】[0009]
【作用】このような構成をした本発明のリードフレーム
においては、貫通孔の回りに溝が形成されているので、
半導体素子等の電子制御部品をダイパッドにダイボンデ
ィングするとき、ダイボンディング用ペースト等の接着
剤の一部が貫通孔の方へ流出しようとしても、その接着
剤は貫通孔の回りの前記溝へ流入するようになる。その
結果、接着剤は貫通孔へは流入しなくなる。In the lead frame of the present invention having such a structure, since the groove is formed around the through hole,
When die-bonding an electronically controlled component such as a semiconductor element to a die pad, even if part of the adhesive such as die bonding paste tries to flow out to the through hole, the adhesive flows into the groove around the through hole. Come to do. As a result, the adhesive does not flow into the through hole.
【００１０】これにより、接着剤が貫通孔を通ってリー
ドフレームの裏面へ回り込むようなことはなくなり、リ
ードフレームの裏面の平坦性が確保されるようになる。
したがって、半導体装置等の電子制御装置の組立におけ
るワイヤーボンディング工程時に、ボンディング不良が
低減する。As a result, the adhesive does not wrap around the back surface of the lead frame through the through hole, and the flatness of the back surface of the lead frame is secured.
Therefore, defective bonding is reduced during the wire bonding process in the assembly of an electronic control device such as a semiconductor device.
【００１１】また本発明のリードフレームにおいては、
接着剤が貫通孔に流入しないことにより、パッケージン
グする際、モールド樹脂が貫通孔に完全に流入すること
ができる。これにより、リードフレームのダイパッドと
モールド樹脂との密着性が高められ、貫通孔の固有の機
能が損なわれることなく、十分に発揮されるようにな
る。Further, in the lead frame of the present invention,
Since the adhesive does not flow into the through hole, the molding resin can completely flow into the through hole during packaging. As a result, the adhesiveness between the die pad of the lead frame and the mold resin is enhanced, and the peculiar function of the through hole is not impaired, and it can be sufficiently exerted.
【００１２】[0012]
【実施例】以下、図面を用いて本発明の実施例について
説明する。図１は本発明のリードフレームの一実施例を
示し、（ａ）はこの実施例におけるリードフレームのダ
イパッド部分の部分拡大平面図、（ｂ）は（ａ）におけ
るIBーIB線に沿う断面図である。なお、このダイパッド
部分以外のインナーリードやアウターリード等の構成
は、例えばＱＦＰやＴＳＯＰ等のパッケージに使用され
ている従来のリードフレームの構成と同じであるので、
その詳細な説明は省略する。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a lead frame of the present invention, (a) is a partially enlarged plan view of a die pad portion of the lead frame in this embodiment, and (b) is a sectional view taken along line IB-IB in (a). Is. The structure of the inner leads and the outer leads other than the die pad portion is the same as the structure of the conventional lead frame used in packages such as QFP and TSOP.
Detailed description thereof will be omitted.
【００１３】図１（ａ）に示すように、この実施例にお
けるリードフレーム１のダイパッド２には、その中央部
に位置して、モールド樹脂との密着性を高めるための十
字形の貫通孔３ａが穿設されていると共に、その四隅近
傍に位置して、モールド樹脂との密着性を高めるための
矩形の貫通孔３ｂが形成されている。更に、ダイパッド
２の外周部にも同様の貫通孔３ｃが多数穿設されてい
る。As shown in FIG. 1 (a), the die pad 2 of the lead frame 1 in this embodiment is located at the central portion thereof and has a cross-shaped through hole 3a for enhancing the adhesion with the molding resin. Is formed, and rectangular through holes 3b are formed in the vicinity of the four corners thereof in order to enhance the adhesiveness with the mold resin. Further, a large number of similar through holes 3c are also formed in the outer peripheral portion of the die pad 2.
【００１４】貫通孔３ａの周囲には、その貫通孔３ａの
縁に沿い、かつ貫通孔３ａを取り囲むようにしてペース
ト収納用の溝４ａが設けられている。また、ダイパッド
２の外周部近傍には、同様の溝４ｂがその外周縁に沿っ
て設けられている。更に、四隅近傍に設けられた貫通孔
３ｂの周囲にも、同様の溝４ｃがその貫通孔３ｂの縁に
沿い、かつ貫通孔３ｂを取り囲むようにして設けられて
いる。同図（ｂ）に示すように、溝４ａ，４ｂ，４ｃの
断面形状はほぼU字形状に形成されている。A groove 4a for containing the paste is provided around the through hole 3a along the edge of the through hole 3a and so as to surround the through hole 3a. A similar groove 4b is provided near the outer peripheral portion of the die pad 2 along the outer peripheral edge thereof. Further, similar grooves 4c are also provided around the through holes 3b provided near the four corners so as to surround the through holes 3b along the edges of the through holes 3b. As shown in FIG. 3B, the grooves 4a, 4b, 4c are formed in a substantially U-shaped cross section.
【００１５】次に、図２ないし図１０を用いてこの実施
例のリードフレーム１を製造する工程について説明す
る。まず、図２に示すように所定厚さの金属板７を用意
する。本実施例の場合、この金属板７は４２％Ｎｉ−Ｆ
ｅ合金で形成されている。しかし、本発明のリードフレ
ーム１を形成するためには、この４２％Ｎｉ−Ｆｅ合金
に限定されなく、銅合金等の他の金属を用いることも可
能である。Next, a process of manufacturing the lead frame 1 of this embodiment will be described with reference to FIGS. First, as shown in FIG. 2, a metal plate 7 having a predetermined thickness is prepared. In the case of this embodiment, the metal plate 7 is made of 42% Ni-F.
It is made of an e-alloy. However, in order to form the lead frame 1 of the present invention, it is not limited to this 42% Ni—Fe alloy, and it is also possible to use another metal such as a copper alloy.
【００１６】次に、図３ないし図５に示すように金属板
７の両面に製版を施す工程を行う。この製版フォトリソ
グラフィーの技術を用いて行われる。すなわち、図３に
示すよう金属板７の両面にレジスト８をコーティングす
る。レジスト８として、本実施例の場合ポジ型レジスト
を用いる。その後、図４に示すようにレジスト８のコー
ティング膜に所定パターンが形成された露光用マスク９
を当てがい、そのマスク９を介して透過する光源１０の
光によりレジスト８のコーティング膜を露光し、次いで
図５に示すように所定の現象液により現像を行う。この
現像により、ペースト保持用の溝４ａ，４ｂを形成する
所定位置α，βで、ボンディング側の面（図５において
上面）においては金属板７の表面が露出し、またその裏
側の面（図５において下面）においては金属板７の表面
がレジスト８により保護されて露出しない状態、すなわ
ちマスキングされた状態となっている。これにより、金
属板７はエッチングの際に片面、すなわち上面よりエッ
チングされるようになる。次に、このように製版された
リードフレーム用金属板７を図６に示すように塩化鉄に
よってエッチングし、金属板７の不要な部分を除去す
る。このエッチングにより、本発明の特徴部分であるペ
ースト保持用の溝４ａ，４ｂ及び貫通孔３ａ，３ｃが形
成される。なお、図６には示されていないが、このエッ
チングにより他の溝４ｃ、貫通孔３ｂ及びダイパッド２
とインナーリード１１との間の間隙孔１２も、それぞれ
形成されるようになる。Next, as shown in FIGS. 3 to 5, a step of performing plate making on both surfaces of the metal plate 7 is performed. This plate-making photolithography technique is used. That is, as shown in FIG. 3, both surfaces of the metal plate 7 are coated with the resist 8. As the resist 8, a positive type resist is used in this embodiment. Thereafter, as shown in FIG. 4, an exposure mask 9 having a predetermined pattern formed on the coating film of the resist 8
The coating film of the resist 8 is exposed by the light of the light source 10 which is transmitted through the mask 9 and then developed by a predetermined phenomenon liquid as shown in FIG. By this development, the surface of the metal plate 7 is exposed on the bonding side surface (upper surface in FIG. 5) at the predetermined positions α and β forming the paste holding grooves 4a and 4b, and the back surface (FIG. 5). 5, the surface of the metal plate 7 is protected by the resist 8 and is not exposed, that is, the surface is masked. As a result, the metal plate 7 is etched from one side, that is, the upper surface during etching. Next, as shown in FIG. 6, the lead frame metal plate 7 thus prepared is etched with iron chloride to remove unnecessary portions of the metal plate 7. By this etching, the paste holding grooves 4a and 4b and the through holes 3a and 3c, which are the features of the present invention, are formed. Although not shown in FIG. 6, other grooves 4c, through holes 3b and die pad 2 are formed by this etching.
The gap hole 12 between the inner lead 11 and the inner lead 11 is also formed.
【００１７】次いで、図７に示すようにこのようにエッ
チングされた金属板７からレジスト８を専用剥離液によ
り除去した後、図８に示すようにダイパッド２部分をイ
ンナーリード１１部分よりも低くなるようにディプレス
する。その後、図９に示すようにインナーリード１１の
先端にワイヤボンディングを良好にするための銀めっき
Ａを施し、最後に図１０に示すようにインナーリード１
１をテープによるテーピングすることにより固定して、
本実施例のリードフレーム１が製造される。Next, after removing the resist 8 from the metal plate 7 thus etched as shown in FIG. 7 with a dedicated stripping solution, the die pad 2 portion becomes lower than the inner lead 11 portion as shown in FIG. To depress. Thereafter, as shown in FIG. 9, silver plating A is applied to the tips of the inner leads 11 to improve wire bonding, and finally, as shown in FIG.
1 is fixed by taping with tape,
The lead frame 1 of this embodiment is manufactured.
【００１８】次に、このように構成された本実施例のリ
ードフレーム１に半導体素子５をダイボンディングする
場合について説明する。図１１（ａ）に示すように、ダ
イボンディング用のペースト６を貫通孔３ａを囲む溝４
ａの外側のダイパッド２の上面に所定量塗布する。な
お、図１１（ａ）には示されていないが、このペースト
６は貫通孔３ｂを囲む溝４ｃの外側でかつ外周部近傍の
溝４ｂの内側に塗布される。そして、同図（ｂ）に示す
ように半導体素子５をダイパッド２上のペースト６上に
搭載し、所定の押圧荷重でダイパッド２の方へ押圧す
る。このとき、ペースト６の一部が、貫通孔３ａ（その
他、貫通孔３ｂ，３ｃ）の方へ流出しようとするが、そ
の流出しようとするペースト６は、溝４ａ（その他、溝
４ｂ，４ｃ）内へ流入して、貫通孔３ａ（３ｂ，３ｃ）
の方へは流れていかない。これにより、ペースト６が貫
通孔３ａ（３ｂ，３ｃ）内へ流入することが防止され
る。Next, the case where the semiconductor element 5 is die-bonded to the lead frame 1 of this embodiment having the above structure will be described. As shown in FIG. 11A, a die bonding paste 6 is formed in a groove 4 surrounding the through hole 3a.
A predetermined amount is applied to the upper surface of the die pad 2 outside a. Although not shown in FIG. 11A, the paste 6 is applied outside the groove 4c surrounding the through hole 3b and inside the groove 4b near the outer peripheral portion. Then, as shown in FIG. 2B, the semiconductor element 5 is mounted on the paste 6 on the die pad 2 and pressed toward the die pad 2 with a predetermined pressing load. At this time, part of the paste 6 tries to flow out toward the through-hole 3a (other than the through-holes 3b and 3c), but the paste 6 that is about to flow out is the groove 4a (other than the grooves 4b and 4c). Inflow into the through hole 3a (3b, 3c)
It doesn't flow to. This prevents the paste 6 from flowing into the through holes 3a (3b, 3c).
【００１９】したがって、ペースト６のリードフレーム
１の裏面へのまわり込みが回避され、リードフレーム１
の裏面の平坦性が確保されるようになる。このように平
坦性が確保されることにより、ワイヤーボンディング工
程において、ボンディング不良が低減する。また、本実
施例のリードフレーム１においては、ペースト６が貫通
孔３ａ，３ｂ，３ｃ内に流入しないことから、モールド
樹脂が貫通孔３ａ，３ｂ，３ｃ内に完全に流入すること
ができようになる。これにより、リードフレーム１のダ
イパッド２とモールド樹脂との密着性を高めるという貫
通孔３の固有の機能が損なわれずに十分に発揮されるよ
うになる。Therefore, the spread of the paste 6 on the back surface of the lead frame 1 is avoided, and the lead frame 1
The flatness of the back surface of the will be secured. By ensuring the flatness in this way, defective bonding is reduced in the wire bonding process. Further, in the lead frame 1 of this embodiment, since the paste 6 does not flow into the through holes 3a, 3b, 3c, the mold resin can be completely flowed into the through holes 3a, 3b, 3c. Become. As a result, the unique function of the through hole 3 for enhancing the adhesion between the die pad 2 of the lead frame 1 and the molding resin can be sufficiently exerted without being impaired.
【００２０】[0020]
【発明の効果】以上の説明から明らかなように、本発明
のリードフレームによれば、ダイボンディング用ペース
ト等の接着剤の一部を貫通孔の回りの溝へ流入させて、
接着剤が貫通孔へ流入するのを防止しているので、接着
剤が貫通孔を通ってリードフレームの裏面へ回り込むこ
とが確実に防止でき、リードフレームの裏面の平坦性を
確保することができる。したがって、半導体装置等の電
子制御装置の組立におけるワイヤーボンディング工程時
に、ボンディング不良を低減することができる。また、
本発明のリードフレームによれば、接着剤が貫通孔に流
入しないことにより、パッケージングする際、モールド
樹脂を貫通孔に完全に流入させることができる。これに
より、リードフレームのダイパッドとモールド樹脂との
密着性を高めることができ、貫通孔の固有の機能を損な
うことなく十分に発揮させることができるようになる。
したがって、本発明のリードフレームにより、信頼性の
高いパッケージを実現することができる。As is apparent from the above description, according to the lead frame of the present invention, a part of the adhesive such as the die bonding paste is caused to flow into the groove around the through hole,
Since the adhesive is prevented from flowing into the through hole, it is possible to reliably prevent the adhesive from passing through the through hole and wrapping around to the back surface of the lead frame, and it is possible to secure the flatness of the back surface of the lead frame. .. Therefore, defective bonding can be reduced during the wire bonding process in the assembly of the electronic control device such as the semiconductor device. Also,
According to the lead frame of the present invention, since the adhesive does not flow into the through hole, the molding resin can be completely flowed into the through hole during packaging. As a result, the adhesiveness between the die pad of the lead frame and the mold resin can be enhanced, and the unique function of the through hole can be sufficiently exerted without impairing the function.
Therefore, the lead frame of the present invention can realize a highly reliable package.
【図１】 本発明のリードフレームの一実施例を示し、
（ａ）はこの実施例におけるリードフレームのダイパッ
ド部分の部分拡大平面図、（ｂ）は（ａ）におけるIBー
IB線に沿う断面図である。FIG. 1 shows an embodiment of a lead frame of the present invention,
(A) is a partially enlarged plan view of the die pad portion of the lead frame in this embodiment, and (b) is IB in (a).
It is sectional drawing which follows the IB line.
【図２】 本実施例のリードフレームの製造工程を説明
する図である。FIG. 2 is a diagram illustrating a manufacturing process of the lead frame of the present embodiment.
【図３】 本実施例のリードフレームの製造工程を説明
する図である。FIG. 3 is a diagram illustrating a manufacturing process of the lead frame of the present embodiment.
【図４】 本実施例のリードフレームの製造工程を説明
する図である。FIG. 4 is a diagram illustrating a manufacturing process of the lead frame of the present embodiment.
【図５】 本実施例のリードフレームの製造工程を説明
する図である。FIG. 5 is a diagram illustrating a manufacturing process of the lead frame of the present embodiment.
【図６】 本実施例のリードフレームの製造工程を説明
する図である。FIG. 6 is a diagram illustrating a manufacturing process of the lead frame of the present embodiment.
【図７】 本実施例のリードフレームの製造工程を説明
する図である。FIG. 7 is a diagram illustrating a manufacturing process of the lead frame of the present embodiment.
【図８】 本実施例のリードフレームの製造工程を説明
する図である。FIG. 8 is a diagram illustrating a manufacturing process of the lead frame of the present embodiment.
【図９】 本実施例のリードフレームの製造工程を説明
する図である。FIG. 9 is a diagram illustrating a manufacturing process of the lead frame of the present embodiment.
【図１０】 本実施例のリードフレームの製造工程を説
明する図である。FIG. 10 is a diagram illustrating a manufacturing process of the lead frame of the present embodiment.
【図１１】 本実施例のリードフレームに半導体素子を
搭載する場合について説明し、（ａ）は半導体素子の搭
載前の状態を示す図、（ｂ）は半導体素子の搭載後の状
態を示す図である。FIG. 11 illustrates a case where a semiconductor element is mounted on the lead frame of the present embodiment, (a) shows a state before mounting the semiconductor element, and (b) shows a state after mounting the semiconductor element. Is.
【図１２】 従来のリードフレームに半導体素子を搭載
する場合について説明し、（ａ）は半導体素子の搭載前
の状態を示す図、（ｂ）は半導体素子の搭載後の状態を
示す図である。FIG. 12 illustrates a case where a semiconductor element is mounted on a conventional lead frame. FIG. 12A is a diagram showing a state before mounting the semiconductor element, and FIG. 12B is a diagram showing a state after mounting the semiconductor element. ..
１…リードフレーム、２…ダイパッド、３ａ，３ｂ，３
ｃ…貫通孔、４ａ，４ｂ，４ｃ…溝、５…半導体素子、
６…ペースト、７…金属板、８…レジスト、９…露光用
マスク、１０…光源、１１…インナーリード、１２…間
隙孔、１３…テーピング用テープ、Ａ…銀めっき1 ... Lead frame, 2 ... Die pad, 3a, 3b, 3
c ... through hole, 4a, 4b, 4c ... groove, 5 ... semiconductor element,
6 ... Paste, 7 ... Metal plate, 8 ... Resist, 9 ... Exposure mask, 10 ... Light source, 11 ... Inner lead, 12 ... Gap hole, 13 ... Taping tape, A ... Silver plating
Claims (1)
ためのダイパッドを有するリードフレームにおいて、 前記ダイパッドに貫通孔が形成されているとともに、こ
の貫通孔の回りに溝が形成されていることを特徴とする
リードフレーム。1. A lead frame having a die pad for mounting an electronic control component such as a semiconductor element, wherein a through hole is formed in the die pad and a groove is formed around the through hole. Characteristic lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3263580A JPH05102207A (en) | 1991-10-11 | 1991-10-11 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3263580A JPH05102207A (en) | 1991-10-11 | 1991-10-11 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05102207A true JPH05102207A (en) | 1993-04-23 |
Family
ID=17391529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3263580A Pending JPH05102207A (en) | 1991-10-11 | 1991-10-11 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05102207A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0655782A3 (en) * | 1993-11-29 | 1995-10-18 | Toshiba Kk | Resin-sealed semiconductor device and method of fabricating same. |
| US6399182B1 (en) * | 2000-04-12 | 2002-06-04 | Cmc Wireless Components, Inc. | Die attachment utilizing grooved surfaces |
-
1991
- 1991-10-11 JP JP3263580A patent/JPH05102207A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0655782A3 (en) * | 1993-11-29 | 1995-10-18 | Toshiba Kk | Resin-sealed semiconductor device and method of fabricating same. |
| US6399182B1 (en) * | 2000-04-12 | 2002-06-04 | Cmc Wireless Components, Inc. | Die attachment utilizing grooved surfaces |
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