JPH05175267A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05175267A
JPH05175267A JP15647392A JP15647392A JPH05175267A JP H05175267 A JPH05175267 A JP H05175267A JP 15647392 A JP15647392 A JP 15647392A JP 15647392 A JP15647392 A JP 15647392A JP H05175267 A JPH05175267 A JP H05175267A
Authority
JP
Japan
Prior art keywords
semiconductor chip
substrate
wire
relay substrate
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15647392A
Other languages
Japanese (ja)
Inventor
Yukihiro Okuhara
幸弘 奥原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP15647392A priority Critical patent/JPH05175267A/en
Publication of JPH05175267A publication Critical patent/JPH05175267A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To make thin a package after resin-sealing, to make small the area of the package, to lessen a short circuit of wiring and moreover, to stabilize a semiconductor chip mounting position by a method wherein a recess is provided in the semiconductor chip mounting part of a joint substrate. CONSTITUTION:In a semiconductor device which is inputted/outputted from or to the outside via a joint substrate 1, on which one or more pieces of a semiconductor chip 2 are mounted and a wiring consisting of a conductor is provided in a pattern, a recess is provided in a semiconductor chip mounting part of the substrate 1. For example, a joint substrate 1 is mounted on an island part 4 of a lead frame 3 via a bonding agent 5, a semiconductor chip 2 is sealed on a recess in the substrate 1 with a bonding agent 5 and electrodes on the chip 2 are wire-bonded to the end parts on one side of the end parts of metallic wiring parts on the substrate 1 by conductive wires 6. Moreover, the other end parts of the metallic wiring parts on the substrate 1 are wire- bonded to inner lead parts 7 of the frame 3 by conductive wires 6 and the device is resin-sealed by a resin sealing material 8.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、１個以上の半導体チッ
プを搭載し、導電体でパターン配線された中継基板を介
し外部に入出力する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device on which one or more semiconductor chips are mounted and which inputs / outputs to / from the outside through a relay substrate patterned by a conductor.

【０００２】[0002]

【従来の技術】従来は図４に示すように、半導体チップ
２を搭載する中継基板１は、平面形状であった。2. Description of the Related Art Conventionally, as shown in FIG. 4, a relay substrate 1 on which a semiconductor chip 2 is mounted has a planar shape.

【０００３】[0003]

【発明が解決しようとする課題】しかし、リードフレー
ム３のアイランド部４の上に接着剤５を介し中継基板１
を搭載し、さらに中継基板１の上に接着剤５を介し半導
体チップ２を搭載し、ワイヤーボンディングしたため樹
脂封止後のパッケージ厚が非常に厚くなるという課題を
有していた。However, the relay board 1 is formed on the island portion 4 of the lead frame 3 with the adhesive 5 interposed therebetween.
Since the semiconductor chip 2 is mounted on the relay substrate 1 via the adhesive 5 and wire bonding is performed, the package thickness after resin sealing becomes very thick.

【０００４】また、半導体チップ２の表面と中継基板１
の表面は高さの差が大きいため、中継基板１側へのワイ
ヤーボンディングは、半導体チップ２に近くワイヤーボ
ンディングすることが難しく、ワイヤー長さが長くなり
パッケージ面積の大型化や樹脂封止時のワイヤー流れに
よるワイヤーショートが生じやすいという課題を有して
いた。さらに半導体チップ２の搭載位置がばらつきやす
いという課題も有していた。Further, the surface of the semiconductor chip 2 and the relay substrate 1
Since there is a large difference in height between the surfaces of, the wire bonding to the relay substrate 1 side is difficult to wire close to the semiconductor chip 2, and the wire length becomes long, resulting in a large package area and resin encapsulation. There was a problem that a wire short circuit due to the wire flow is likely to occur. Further, there is a problem that the mounting position of the semiconductor chip 2 tends to vary.

【０００５】そこで本発明は、従来のこのような課題を
解決するために、中継基板の半導体チップ搭載部に凹み
を設けることで樹脂封止後のパッケージ厚を薄くし、パ
ッケージ面積を小さくし、ワイヤーショートを少なく
し、さらに半導体チップの搭載位置安定化をする事を目
的としている。Therefore, in order to solve such a conventional problem, the present invention reduces the package thickness after resin encapsulation by providing a recess in the semiconductor chip mounting portion of the relay substrate, thereby reducing the package area, The purpose is to reduce wire shorts and stabilize the mounting position of semiconductor chips.

【０００６】[0006]

【課題を解決するための手段】前述の課題を解決するた
め、本発明の半導体装置は、 （１） １個以上の半導体チップを搭載し、導電体でパ
ターン配線された中継基板を介し外部に入出力する半導
体装置に於て、前記中継基板の半導体チップ搭載部に凹
みを設けた事を特徴とする。In order to solve the above-mentioned problems, the semiconductor device of the present invention comprises: (1) One or more semiconductor chips are mounted to the outside via a relay substrate patterned by conductors. In the input / output semiconductor device, a recess is provided in the semiconductor chip mounting portion of the relay substrate.

【０００７】（２） 前記中継基板の半導体チップ搭載
部に貫通穴を設けた事を特徴とする。(2) A through hole is provided in the semiconductor chip mounting portion of the relay board.

【０００８】[0008]

【実施例】（実施例１）以下に本発明の実施例を図面に
もとずいて説明する。Embodiments Embodiment 1 of the present invention will be described below with reference to the drawings.

【０００９】図１に於て、リードフレーム３のアイラン
ド部４の上に接着剤５を介し中継基板１が搭載されてい
る。さらに中継基板１の上に半導体チップ２が接着剤５
によって固着される。In FIG. 1, the relay board 1 is mounted on the island portion 4 of the lead frame 3 with an adhesive 5 interposed therebetween. Further, the semiconductor chip 2 has the adhesive 5 on the relay substrate 1.
Fixed by.

【００１０】半導体チップ２の電極と中継基板１の金属
配線部に導電性ワイヤー６でワイヤーボンディングされ
る。The electrodes of the semiconductor chip 2 and the metal wiring portions of the relay substrate 1 are wire-bonded with the conductive wires 6.

【００１１】中継基板１の金属配線のもう一方の端部と
リードフレーム３のインナーリード部７へさらに導電性
ワイヤー６でワイヤーボンディングされる。そして樹脂
封止材８で樹脂封止されている。The other end of the metal wiring of the relay board 1 and the inner lead portion 7 of the lead frame 3 are further wire-bonded with a conductive wire 6. Then, it is resin-sealed with the resin sealing material 8.

【００１２】ここで、中継基板１の半導体チップ２の搭
載部は、凹みがつけられている。Here, the mounting portion of the semiconductor chip 2 on the relay substrate 1 is provided with a recess.

【００１３】この凹みがあるため、中継基板１の表面か
ら半導体チップ２の表面までの高さは、図４の中継基板
１の凹みが無いときに比較して中継基板１の凹み分だけ
低く抑えることができる。Due to this recess, the height from the surface of the relay substrate 1 to the surface of the semiconductor chip 2 is suppressed to be lower than that of the relay substrate 1 shown in FIG. be able to.

【００１４】これによって、最終的に樹脂封止材８で樹
脂封止された後のパッケージ厚が薄く抑えられる。As a result, the package thickness after resin sealing with the resin sealing material 8 is finally suppressed.

【００１５】さらに、中継基板１の表面から半導体チッ
プ２の表面までの距離が短くできるため、従来の図４に
比較して中継基板１側のワイヤーボンディングが半導体
チップ２に近くワイヤーボンディングできワイヤー長さ
を短く抑えられる。Further, since the distance from the surface of the relay substrate 1 to the surface of the semiconductor chip 2 can be shortened, the wire bonding on the side of the relay substrate 1 is closer to the semiconductor chip 2 than in the conventional case of FIG. Can be kept short.

【００１６】このため、ボンディング品質の向上が実現
できるとともに、中継基板１の小型化ができ樹脂封止材
８で樹脂封止後のパッケージ面積の小型化も可能とな
る。As a result, the bonding quality can be improved, the relay substrate 1 can be downsized, and the package area after resin sealing with the resin sealing material 8 can be reduced.

【００１７】そして、ワイヤー長さが短くできるのと同
時に、導電性ワイヤー６と半導体チップ２の角のエッジ
ショートも起こりにくく、ワイヤー高さも低くでき樹脂
封止後のパッケージ厚を薄くするのにさらに貢献でき
る。At the same time that the wire length can be shortened, edge shorts at the corners of the conductive wire 6 and the semiconductor chip 2 are unlikely to occur, and the wire height can be lowered, further reducing the package thickness after resin sealing. I can contribute.

【００１８】また、ワイヤー長さが短くできることによ
って、樹脂封止材８で樹脂封止時にワイヤー流れが少な
く、ワイヤーショートが発生しにくくなるというメリッ
トも持っている。Further, since the wire length can be shortened, there is also an advantage that the wire flow during resin encapsulation with the resin encapsulant 8 is small and a wire short circuit is less likely to occur.

【００１９】（実施例２）図２は別の実施例で、中継基
板１の凹みの段差部９を斜めに角度をつけている。こう
することによって、半導体チップ２を搭載する際の位置
決め機能が増し、中継基板１に半導体チップ２搭載時の
位置ずれを減少でき安定した実装が可能となる。もとも
とアイランド部４の上に中継基板１を搭載時に位置がば
らつき、さらに半導体チップ２を搭載時に位置がばらつ
くため２重のばらつきが相乗する課題にたいして有効な
対策である。(Embodiment 2) FIG. 2 shows another embodiment in which the stepped portion 9 of the recess of the relay board 1 is obliquely angled. By doing so, the positioning function at the time of mounting the semiconductor chip 2 is increased, the positional deviation when mounting the semiconductor chip 2 on the relay board 1 can be reduced, and stable mounting can be performed. This is an effective measure against the problem that double variations are synergistic since the position of the relay substrate 1 originally varies on the island part 4 when it is mounted and the position of the semiconductor chip 2 also varies when it is mounted.

【００２０】（実施例３）図３にさらに別の実施例を示
す。中継基板１に貫通穴を設け、半導体チップ２を搭載
する構造になっている。実施例１及び実施例２に於いて
は、リードフレーム３のアイランド部４の上に接着剤５
を塗布する事、接着剤５の上に中継基板１を搭載する
事、接着剤５を硬化させる事、中継基板１の上に接着剤
５を塗布する事、接着剤５の上に半導体チップ２を搭載
する事、接着剤５を硬化する事、これでようやく導電性
ワイヤー６でワイヤーボンディングする準備ができる。(Embodiment 3) FIG. 3 shows still another embodiment. A through hole is provided in the relay board 1 to mount the semiconductor chip 2. In the first and second embodiments, the adhesive 5 is applied on the island portion 4 of the lead frame 3.
Coating, mounting the relay substrate 1 on the adhesive 5, curing the adhesive 5, coating the adhesive 5 on the relay substrate 1, and mounting the semiconductor chip 2 on the adhesive 5. Then, the adhesive 5 is hardened, and finally, the conductive wire 6 is ready for wire bonding.

【００２１】実施例３に於いては、リードフレーム３の
アイランド部４の上に接着剤５を塗布する事、接着剤５
の上に中継基板１を搭載する事、さらに中継基板１の貫
通穴に半導体チップ２を搭載する事、接着剤５を硬化す
る事、以上で導電性ワイヤー６でワイヤーボンディング
する準備ができ、実施例１及び実施例２に比較し接着剤
５の塗布と接着剤５の硬化の２工程が削減できる。In the third embodiment, the adhesive 5 is applied on the island portion 4 of the lead frame 3,
Mounting the relay board 1 on top of it, further mounting the semiconductor chip 2 in the through hole of the relay board 1, curing the adhesive 5, and the preparation for wire bonding with the conductive wire 6 is completed. Compared to Example 1 and Example 2, the two steps of applying the adhesive 5 and curing the adhesive 5 can be reduced.

【００２２】さらに、半導体チップ２が中継基板１の貫
通穴に搭載されるため、従来の技術を示す図４はもとよ
り、実施例１及び実施例２に比較してリードフレーム３
のアイランド部表面から半導体チップ２表面までの距離
を小さくでき、よりパッケージの薄型化、小型化が実現
されるという優れた効果がある。Furthermore, since the semiconductor chip 2 is mounted in the through hole of the relay substrate 1, the lead frame 3 is different from the first and second embodiments as well as FIG. 4 showing the conventional technique.
There is an excellent effect that the distance from the surface of the island portion to the surface of the semiconductor chip 2 can be reduced, and the package can be made thinner and smaller.

【００２３】また実施例２と同様に、中継基板１の貫通
穴の段差部９を斜めに角度をつけることによって、半導
体チップ２を搭載する際の位置決め機能が増し、中継基
板１に半導体チップ２搭載時の位置ずれを減少でき安定
した実装が可能となる。Further, similarly to the second embodiment, by obliquely angling the step portion 9 of the through hole of the relay board 1, the positioning function when mounting the semiconductor chip 2 is increased, and the semiconductor chip 2 is mounted on the relay board 1. Positional displacement during mounting can be reduced and stable mounting is possible.

【００２４】[0024]

【発明の効果】本発明の半導体装置は、以上説明したよ
うに中継基板に凹み叉は貫通穴を設けるといった簡単な
構造によって、パッケージ面積の小型化，パッケージの
薄型化，ワイヤーショートの減少、エッジショートの減
少といったボンディング品質の向上，半導体チップ搭載
時の位置決め安定化などの効果がある。As described above, the semiconductor device of the present invention has a simple structure in which a recess or a through hole is formed in the relay substrate, so that the package area can be made smaller, the package can be made thinner, wire shorts can be reduced, and edges can be reduced. It has the effects of improving the bonding quality such as the reduction of short circuits and stabilizing the positioning when mounting a semiconductor chip.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の実施例を示す縦断面図。FIG. 1 is a vertical sectional view showing an embodiment of the present invention.

【図２】 本発明の別の実施例を示す縦断面図。FIG. 2 is a vertical sectional view showing another embodiment of the present invention.

【図３】 本発明の別の実施例を示す縦断面図。FIG. 3 is a vertical cross-sectional view showing another embodiment of the present invention.

【図４】 従来の半導体装置を示す縦断面図。FIG. 4 is a vertical sectional view showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ 中継基板 ２ 半導体チップ ３ リードフレーム ４ アイランド部 ５ 接着剤 ６ 導電性ワイヤー ７ インナーリード部 ８ 樹脂封止材 ９ 段差部 1 Relay Board 2 Semiconductor Chip 3 Lead Frame 4 Island 5 Adhesive 6 Conductive Wire 7 Inner Lead 8 Resin Sealant 9 Step

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】１個以上の半導体チップを搭載し、導電体
でパターン配線された中継基板を介し外部に入出力する
半導体装置に於て、前記中継基板の半導体チップ搭載部
に凹みを設けた事を特徴とする半導体装置。1. A semiconductor device in which one or more semiconductor chips are mounted and input / output to / from the outside through a relay substrate patterned by a conductor, wherein a recess is provided in a semiconductor chip mounting portion of the relay substrate. A semiconductor device characterized by that. 【請求項２】１個以上の半導体チップを搭載し、導電体
でパターン配線された中継基板を介し外部に入出力する
半導体装置に於て、前記中継基板の半導体チップ搭載部
に貫通穴を設けた事を特徴とする半導体装置。2. A semiconductor device in which one or more semiconductor chips are mounted and which inputs and outputs to and from the outside through a relay substrate patterned by a conductor, wherein a through hole is provided in a semiconductor chip mounting portion of the relay substrate. A semiconductor device characterized by the following.
JP15647392A 1991-06-25 1992-06-16 Semiconductor device Pending JPH05175267A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15647392A JPH05175267A (en) 1991-06-25 1992-06-16 Semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP15311491 1991-06-25
JP3-153114 1991-06-25
JP15647392A JPH05175267A (en) 1991-06-25 1992-06-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05175267A true JPH05175267A (en) 1993-07-13

Family

ID=26481832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15647392A Pending JPH05175267A (en) 1991-06-25 1992-06-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05175267A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011023416A (en) * 2009-07-13 2011-02-03 Dainippon Printing Co Ltd Wiring member for semiconductor device, composite wiring member for semiconductor device, and resin-sealed semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011023416A (en) * 2009-07-13 2011-02-03 Dainippon Printing Co Ltd Wiring member for semiconductor device, composite wiring member for semiconductor device, and resin-sealed semiconductor device

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