JPH05102150A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device with a via hole structure which has a low resistance and can prevent the occurrence of a disconnection trouble caused by an electromigration or stress migration in multilayered wiring by burying upper-layer wiring in a connection hole so that the upper-layer wiring can be connected to conductive films formed on the side wall of the connection hole. CONSTITUTION:This semiconductor device is provided with a semiconductor substrate 8 on which first wiring 10 and 11 is formed and conductive films 13 and 14 formed on the side wall of a connection hole 20 bored through an insulating film 12 coating the substrate 8. In addition, this semiconductor device is also provided with second wiring 15 buried in the hole 20 so that the wiring 15 can be connected to the first wiring 10 and films 13 and 14. For example, after first-layer Al-wiring 10 and 11 is formed on a silicon substrate 8 with a BPSG film 9 in between, a silicon oxide film 12 is formed on the entire surface of the substrate 8 and a via hole 20 is formed through the film 12. Then, after forming a W film on the entire surface of the substrate 8 and leaving parts 13 and 14 of the W film on the side wall of the hole 20 only, second-layer Al-wiring 15 is formed and the Al film 15 is buried in the hole 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a connection hole (via hole) in a multi-layer wiring of a semiconductor device and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, with the increase in density of semiconductor devices, reliability of wiring, that is, electromigration and stress migration has become a problem. Usually, as the wiring metal, A deposited by the sputtering method is used.
1 or an Al alloy containing Si, Ti, Cu, Ge, Hf, B, etc. is used (hereinafter, Al or Al alloy will be referred to as Al unless otherwise specified).
As a conventional method of forming a via hole structure in a semiconductor device, as shown in FIG. 2, first layer wirings 3, 4 are formed on a silicon substrate 1 on which a semiconductor element is formed, with an insulating film 2 interposed therebetween.
After forming, the interlayer insulating film 5 is deposited and flattened,
A method of forming a via hole 20 in the interlayer insulating film 5 and forming a second layer wiring 6 is used. However, as the density of semiconductor devices increases, the ratio of the interlayer insulating film thickness to the diameter of the connection hole (aspect ratio) increases, and the via hole 20 becomes deeper. As a result, the Al wiring deposited by the sputtering method has a problem that the step coverage (step coverage) in the via hole 20 is deteriorated, which leads to disconnection in the initial stage, or electromigration or stress migration causes disconnection.

As a method for solving the above problems,
As shown in FIG. 3, there is a method of embedding the metal film 7 in the via hole 20 by using the selective CVD method (for example, I.E.E.I.E. Proceeding of V.L.S.I.M.
Conference (1989), pages 113-121 (IEEE, Proc
eeding of VLSI Multilevel Interconnection Con
ference (1989) pp.113-121).

A W selective CVD method using a WF ₆ gas is widely used for burying the metal film 7. If such a method is used, it is considered that the step coverage of the wiring in the via hole is not reduced, and that the W film is a refractory metal, so that a disconnection defect due to electromigration or stress migration can be prevented. ..

[0005]

However, in the above structure, when W is selectively deposited in the via hole, W and A are caused by the reaction of WF ₆ and Al in the initial stage of deposition.
Since the fluoride of Al is generated at the interface of l and the specific resistance of the W film existing between the first layer Al wiring and the second layer Al wiring is higher than that of Al, the via hole resistance is increased. Occurs. As a result, there has been a problem that the operating speed of the device is lowered and the variation of its characteristics is increased.

In view of the above-mentioned problems, the present invention provides a semiconductor device having a via hole structure having a low resistance in a multilayer wiring of a semiconductor device and capable of preventing disconnection failure due to electromigration or stress migration, and the same. It is intended to provide a manufacturing method.

[0007]

In order to solve the above-mentioned problems, a semiconductor device of the present invention is provided on a semiconductor substrate having a first wiring formed thereon and an insulating film deposited on the semiconductor substrate. A conductive film formed on a sidewall of the connection hole and a second wiring embedded in the connection hole so as to be connected to the first wiring and the conductive film are provided.

Further, the method of manufacturing a semiconductor device of the present invention comprises the steps of providing an insulating film having a connection hole on the semiconductor substrate on which the first wiring is formed, and forming a conductive film on the insulating film. A step of removing the conductive film by a dry etching method and leaving the conductive film only on the side wall of the connection hole; and a second wiring connected to the first wiring and the conductive film through the connection hole. And a step of forming.

[0009]

According to the present invention, since the first wiring and the second wiring are directly connected to each other by the structure described above, the via hole resistance can be reduced, so that a high-speed operation semiconductor device can be manufactured. .. In addition, since the second wiring in the via hole is reinforced by the surrounding conductive film, disconnection due to electromigration or stress migration can be prevented.

[0010]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a process sectional view showing an embodiment of the present invention.

First, in FIG. 1a, first layer Al wirings 10 and 11 having a thickness of 0.8 μm are formed on a silicon substrate 8 on which semiconductor elements are formed with a silicon oxide film 9 containing B and P having a thickness of 0.8 μm interposed. It is formed to have a thickness of μm. First layer Al wiring 1
The sputtering method was used to form 0 and 11, and the material was A containing 1% of Si and 0.5% of Cu.
1 alloy is used. Alternatively, an Al alloy containing an element such as Ti, Ge, Hf, or B may be used. First layer Al wiring 1
The structure of 0, 11 has Ti, TiN, Ti on the top and bottom.
A structure in which a film of W, TiSi ₂ , WSi ₂ , Mo, MoSi ₂ or the like is formed may be used. Next, the silicon oxide film 12 is formed on the entire surface by the plasma CVD method, and the via hole 20 is formed in the silicon oxide film 12 by the dry etching method. In this case, the silicon oxide film 12 is flattened by the resist etch back method.

Next, in FIG. 1b, after the W film is formed on the entire surface, the W film on the silicon oxide film 12 is removed by the sputter etching method using Ar gas, and the W films 13 and 14 are formed only on the sidewalls of the via holes. To leave. At this time, since the fluoride of Al existing at the interface between W and Al at the bottom of the via hole is also removed, the via hole resistance does not increase. In this case, the W film is deposited by the CVD method using WF ₆ and SiH ₄ or H ₂ . When depositing the W film, a film of TiN, Ti, or the like may be used as the adhesion layer. Further, TiW or Ti film may be used instead of the W film. In particular, when the TiW film is formed by the sputtering method, it has good step coverage and is therefore effective in forming a highly reliable via hole structure.

Next, in FIG. 1c, the second layer Al wiring 15 is formed on the entire surface, and the Al film 15 is embedded in the via hole 20. The material of the second layer Al wiring 15 is 1% of Si,
Complete filling can be achieved by using an Al alloy containing 0.5% Cu and using a sputtering method in which the substrate temperature is set to 400 to 500 ° C. The structure of the second layer Al wiring 15 includes Ti, TiN, TiW
A structure in which a film of TiSi ₂ , WSi ₂ , Mo, MoSi ₂ or the like is formed may be used.

As described above, when the semiconductor device and the method of manufacturing the same according to this embodiment are used, the first film can be formed without interposing the W film.
Since the layer Al wiring 10 and the second layer Al wiring 15 can be connected, a low via hole resistance can be obtained. In addition, since the Al film in the via hole can have a laminated structure with the W film, it is possible to form the via hole with high reliability.

The formation of the W film, the Ar sputter etching, and the formation of the second layer wiring are preferably performed by the same apparatus which can maintain a vacuum state. Because, when forming the second layer wiring,
This is because if the W film is exposed to air and oxidized, the wettability of the Al film deteriorates and complete filling of the via hole cannot be achieved.

[0016]

As described above, according to the present invention, since the first wiring and the second wiring are directly connected to each other, the via hole resistance can be reduced, so that a high-speed operation semiconductor device can be manufactured. Is possible. In addition, the second in the via hole
Since the wiring is reinforced by the surrounding conductive film, it is possible to prevent disconnection due to electromigration or stress migration.

[Brief description of drawings]

FIG. 1 is a process sectional view in an embodiment of the present invention.

FIG. 2 is a sectional view of a conventional multilayer wiring structure.

FIG. 3 is a sectional view of a conventional multilayer wiring structure.

[Explanation of symbols]

 8 Silicon Substrate 9 Silicon Oxide Film Containing B and P 10,11 First Layer Al Wiring 12 Silicon Oxide Film 13,14 W Film 15 Second Layer Al Wiring 20 Via Hole

Claims (2)

[Claims] 1. A semiconductor substrate on which a first wiring is formed, a conductive film formed on a side wall of a connection hole formed in an insulating film deposited on the semiconductor substrate, the first wiring and the conductive material. A second embedded in the connection hole so as to be connected to the membrane
And a wiring of the semiconductor device. 2. A step of providing an insulating film having a connection hole on a semiconductor substrate having a first wiring formed thereon, a step of forming a conductive film on the insulating film, and removing the conductive film by a dry etching method. And a step of leaving the conductive film only on the side wall of the connection hole, and a step of forming a second wiring connected to the first wiring and the conductive film through the connection hole. A method of manufacturing a semiconductor device, which is characterized.