JPH05100889A - Self diagnostic circuit - Google Patents

Abstract

PURPOSE:To provide a self diagnostic circuit capable of diagnosing the function of a monitoring means without interfering with normal computer processing operation. CONSTITUTION:A digit scanning signal 4 generated by a microcomputer is inputted in a watchdog timer 6. An OR gate 14 is provided, which inputs a reset control signal 15 from a test switch 11 and an abnormality signal from the watchdog timer 6 so as to output a reset signal to the microcomputer 1 at the time of only abnormality signals and which prohibits the output of the reset signal 9 when both the reset control signal 15 and the abnormality signal are inputted. The microcomputer 1 stops the digit scanning signal 4 when the test switch 11 is operated and operates prescribed display in accordance with the presence or absence of the abnormality signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-diagnosis circuit for diagnosing the function of monitoring means for monitoring malfunction of a computer.

[0002]

2. Description of the Related Art A watchdog timer is usually used as a monitoring means for monitoring a computer's operation such as runaway or latch-up and detecting a malfunction and resetting the malfunction. In the case of diagnosing whether is normally operating, a self-diagnosis circuit as shown in the block diagram of FIG. 7 has been conventionally used.

That is, in FIG. 7, a microcomputer 1 as a computer is connected between a circuit power supply 2 and a ground, and outputs a digit scan signal 4 and display data 5 to a display section 3. A part of the digit scan signal 4 is used as an input signal 7 of a watchdog timer 6 as a monitoring means, and a watchdog timer output signal 8 which is an output of the watchdog timer 6 is input to the microcomputer 1 as a reset signal 9. .. A resistor 10 and a test switch 11 as a test operating unit of the watchdog timer 6 are provided between the circuit power source 2 and the ground.
Is connected to the microcomputer 1, and the terminal voltage of the test switch 11 is input to the microcomputer 1 as a diagnostic operation instruction signal 12.

Next, the function and operation of the conventional self-diagnosis circuit of FIG. 7 will be described with reference to the flow chart of the microcomputer 1 of FIG. 8 and the timing chart of FIG. The microcomputer 1 employs a display system in which the display unit 3 is dynamically lit. In this case, the display content is determined by the display data 5 and the display digit is determined by the digit scan signal 4. Further, in such a dynamic lighting system, the digit scan signal 4 for determining the display digit is continuously output without interruption in the normal operation state of the microcomputer 1.

By the way, the watchdog timer 6 is
Since part of the digit scan signal 4 is used as the input signal 7 as described above, the input signal 7 of the watchdog timer 6 is continuously input without interruption if the microcomputer 1 is in a normal operating state. It will be. Therefore, when the input signal 7 is continuously input, the watchdog timer 6 determines that the microcomputer 1 is in a normal operation state and has a high potential (hereinafter, referred to as “H”).
Called. The normal signal of 1) is output to the microcomputer 1 as a watchdog timer output signal 8.

When the input signal 7 is interrupted for a certain time or longer due to some reason, the watchdog timer 6 judges that the microcomputer 1 is in an abnormal operation state and has a low potential (hereinafter referred to as "L"). The abnormal signal is output as a watchdog timer output signal 8, which is input to the microcomputer 1 as a reset signal 9.
Watchdog timer 6 in microcomputer 1
If the watchdog timer output signal 8 sent from is a normal signal of "H", the operation of the microcomputer 1 is maintained, but if it is an abnormal signal of "L", that is, the reset signal 9, the operation of the microcomputer 1 is immediately started. To stop. By such an operation, the watchdog timer 6
Constantly monitors the operating state of the microcomputer 1.

The test switch 11 is normally closed, and is opened by the user when diagnosing the function of the watchdog timer 6. In FIG. 8, the microcomputer 1 is initialized at step S1 after the power is turned on, determines at step S2 whether or not the test switch 11 is opened, and if it remains closed, the normal operation program is executed at step S3. ing. When the test switch 11 is opened at time T1 in FIG. 9 and the diagnostic operation instruction signal 12 changes from “L” to “H”, the microcomputer 1 proceeds from step S2 to step S4 to stop the digit scan signal 4 and In S5, it is determined whether a certain time has passed.

Here, the watchdog timer 6 always outputs the watchdog timer output signal 8 of "H", and if the watchdog timer 6 is functioning normally, the digit scan signal 4 is stopped. At time T2 when the watchdog timer 6 continues for a predetermined period of time, the watchdog timer 6 judges that the microcomputer 1 is in an abnormal operation state, and outputs an "L" abnormal signal as shown in the third stage from the top of FIG. 8 as a reset signal 9 (“L”) as in the second row from the bottom of FIG. 9 and is input to the microcomputer 1. At time T3 (after T2) when a certain time has passed from T1, the microcomputer 1 determines in step S6 whether the watchdog timer output signal 8 is "H" or "L", and in this case "L". Therefore, it is reset in step S7.

When the watchdog timer 6 is not functioning normally, the watchdog timer output signal 8 remains "H" at time T2 as shown in the fourth row from the top of FIG. Reset signal 9 as below
("L") is not input to the microcomputer 1 either, and the flow advances from step S6 to step S8 to display NG.

[0010]

As described above, in the conventional self-diagnosis circuit, when diagnosing the function of the watchdog timer 6, an abnormal state is artificially created and the watchdog timer output signal 8 is reset. As a result, the microcomputer 1 is diagnosed according to whether or not the microcomputer 1 is reset by inputting it to the microcomputer 1. Therefore, if the watchdog timer 6 is normal, the microcomputer 1 is always reset. As a result, there is a problem in that the operation of the microcomputer 1 is stopped and the normal microcomputer processing work is hindered.

The present invention has been made in order to solve the above-mentioned conventional technical problems, and the function diagnosis of the monitoring means is
An object of the present invention is to provide a self-diagnosis circuit that can be executed without affecting normal computer processing work.

[0012]

According to the present invention, a computer that outputs a signal corresponding to a normal state and an abnormality of the computer are detected by monitoring the state of the signal, and an abnormal signal is generated if the state is abnormal. Monitoring means, a test operating portion of the monitoring means, a reset control signal generated based on the operation of the test operating portion, and the abnormal signal are input, the reset control signal is not input, and the abnormal signal is input. Output a reset signal to the computer,
When a reset control signal and an abnormal signal are both input, a self-diagnosis circuit is formed from a gate that prohibits the output of the reset signal, and the computer is a signal corresponding to the normal state in accordance with the operation of the test operating unit. Is stopped, and a predetermined display operation is executed according to the presence or absence of the abnormal signal.

[0013]

When the test operating section is operated to diagnose the function of the monitoring means, a reset control signal is generated on the basis of the operation and is input to the gate. Since the computer stops the output of the signal corresponding to the normal state by the operation of the test operation unit, if the monitoring means is normal, the abnormal signal is generated by the stop of the input. In this case, both the reset control signal and the abnormal signal are input to the gate, and the computer reset signal is not output from the gate. If the monitoring means does not operate normally, no abnormal signal is generated, and in any case, the computer does not generate a reset signal from the gate. On the other hand, the computer executes a predetermined display operation depending on whether or not the monitoring means outputs an abnormal signal, and notifies the user of the operating status of the monitoring means.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of a self-diagnosis circuit of the present invention, and FIG. 2 is a microcomputer 1 as an example of a computer.
FIG. 3 is a flowchart showing the program of FIG. 3, and FIG. 3 is a timing chart of each signal of FIG. In addition, in FIG.
Those denoted by the same reference numerals as in FIG.

In the case of the present invention, a watchdog timer output signal 8 which is an output of a watchdog timer 6 as an example of the monitoring means is input to a logical sum gate (hereinafter referred to as an OR gate) 14 and at the same time, It is also input to the input terminal 1A of the microcomputer 1. Further, the terminal voltage of the test switch 11 as the test operation unit is input to the input terminal 1B of the microcomputer 1 as the diagnostic operation instruction signal 12 and also to the OR gate 14 as the reset control signal 15. The output of the OR gate 14 is input to the input terminal 1C of the microcomputer 1 as the reset signal 9.

Next, referring to FIGS. 2 and 3, FIG.
The function and operation of the self-diagnosis circuit of the present invention will be described. The microcomputer 1 controls, for example, a room heater, adopts a display system that dynamically lights the display unit 3 as described above, and continuously outputs the digit scan signal 4 for determining a display digit without interruption in a normal operation state. Is being output. Similarly, the watchdog timer 6 also uses a part of the digit scan signal 4 as an input signal 7, and if the microcomputer 1 is in a normal operating state, the input signal 7 is continuously input without interruption. The watchdog timer 6 judges that the microcomputer 1 is in a normal operating state and outputs a normal signal of "H" as the watchdog timer output signal 8 as shown in the third or fourth row from the top of FIG. ing.

When the input signal 7 is interrupted for a certain time or longer for some reason, the watchdog timer 6 judges that the microcomputer 1 is in an abnormal operation state and outputs an "L" abnormal signal to the watchdog timer output signal 8
Output as. Further, the microcomputer 1 is reset when the input terminal 1C becomes "L",
The watchdog timer 6 is not being diagnosed, the test switch 11 is closed, and the reset control signal 15 is "L".
If so, the watchdog timer output signal 8 is "L".
The output of the OR gate 14 also becomes "L" when it becomes the abnormal signal of 1., and this becomes the reset signal 9 and is input to the input terminal 1C of the microcomputer 1, and the microcomputer 1 is reset.

In FIG. 2, the microcomputer 1 is initialized at step S10 after the power is turned on, and at step S11 the test switch 11 is set by the potential of the input terminal 1B.
It is determined whether or not is opened, and if it is still closed, the normal operation program is executed in step S12. When the test switch 11 is opened at time T1 in FIG. 3 and the diagnostic operation instruction signal 12 changes from "L" to "H", the microcomputer 1 proceeds from step S11 to step S11.
Proceed to step 13 to stop the digit scan signal 4, and step S1
At 4, it is determined whether a certain time has passed. Further, the reset control signal 15 is also changed from “L” to “H” by the opening of the test switch 11, and is input to the OR gate 14.

On the other hand, if the watchdog timer 6 is functioning normally, the watchdog timer 6 determines that the microcomputer 1 is in an abnormal operating state at time T2 when the stop of the digit scan signal 4 is continued for a predetermined period. Then, an abnormal signal of "L" is generated as the watchdog timer output signal 8 as shown in the third row from the top of FIG. However, the watchdog timer output signal 8
Is "L", the reset control signal 15 is "H" as described above. Therefore, the output of the OR gate 14 remains "H" and does not become the reset signal 9, and the microcomputer The input terminal 1C of No. 1 remains "H" and the microcomputer 1 is not reset.

The microcomputer 1 performs step S15 at time T3 (after T2) after a lapse of a certain time from T1.
Determines whether the watchdog timer output signal 8 of the input terminal 1A is "H" or "L". In this case, since it is the abnormal signal "L", the generation of the digit scan signal 4 is restarted in step S16. Then, in step S17, the display 3 is OK.
The display is performed, and it is determined in step S18 whether a certain time has elapsed, and after a certain time, the process returns to step S11. The user can confirm that the watchdog timer 6 operates normally by looking at the OK display on the display unit 3.

Next, when the watchdog timer 6 is not functioning normally, the watchdog timer output signal 8 remains "H" at the time T2 as in the fourth step from the top of FIG. The output of the gate 14 is "H", and the microcomputer 1 is not reset. On the other hand, the watchdog timer output signal 8 of the input terminal 1A
Is "H", the microcomputer 1 advances from step S15 to step S19 to restart the output of the digit scan signal 4, and the display unit 3 displays N in step S20.
The G display is performed, and it is determined in step S18 whether a certain time has elapsed, and after a certain time, the process returns to step S11. The user can confirm that the watchdog timer 6 is not operating normally by looking at the NG display on the display unit 3. Further, at this time, since the microcomputer 1 is not reset, the function diagnosis of the watchdog timer 6 can be executed without affecting the normal processing work of the microcomputer 1.

Next, FIGS. 4 to 6 show another embodiment of the present invention. In the above embodiment, the terminal voltage of the test switch 11 was directly used as hardware as the reset control signal 15, but in the case of this embodiment, the test switch 1 is used.
The terminal voltage of 1 is not directly used as the reset control signal 15, but the diagnostic operation instruction signal 12 is once input to the microcomputer 1 and, after some processing, is output as the reset control signal 15 from the output terminal 1D of the microcomputer 1. The method of doing is taken. The other circuit configuration is similar to that of FIG.

The operation of this embodiment will be described with reference to the flow chart of FIG. 5 and the timing chart of FIG. 6 in comparison with the above embodiment. The difference between the flowchart of FIG. 2 and the flowchart of FIG. 5 is that step S in FIG.
When the test switch 11 is opened at 11 and the diagnostic operation instruction signal 12 changes from “L” to “H”, step S
Prior to step 13, the reset control signal 15 is set (“L” to “H”) in step S21 and output from the output terminal 1D. That is, the reset control signal 15 is generated by the microcomputer 1, and the generation time thereof is also entrusted to the microcomputer 1.

Therefore, for example, as shown in the first row from the top of FIG. 6, even if the diagnostic operation instruction signal 12 becomes "H" at time T1, the reset control signal 1 of "H" is shown in the second row.
5 can be sent to the OR gate 14 as "H" at time T4 which is slightly delayed without outputting 5 at the same time. As a result, the T2 and T3 times are all T5 and T6 times delayed by the period T1 to T4. However, as described above, the reset control signal 15 is output as the output of the microcomputer 1.
In addition to the effects of the above embodiment, there is an advantage that the diagnosis of the function of the watchdog timer 6 can be started at a timing convenient for the normal processing operation of the microcomputer 1.

In each embodiment, a part of the digit scan signal 4 is used as the input signal 7 of the watchdog timer 6, but this may be another signal, and the operation of the microcomputer 1 is in a normal state. Needless to say, the same effect can be obtained if the signal is continuous without interruption in the case of 1) and stops for a certain period of time or more in the case of an abnormal state.

[0026]

As described above in detail, according to the present invention, it is possible to realize the function diagnosis of the monitoring means without interfering with the normal computer processing operation.

[Brief description of drawings]

FIG. 1 is a block diagram of a self-diagnosis circuit of the present invention.

2 is a flowchart showing a program of the microcomputer of FIG.

FIG. 3 is a timing chart of each signal in FIG.

FIG. 4 is a block diagram of a self-diagnosis circuit according to another embodiment of the present invention.

5 is a flowchart showing a program of the microcomputer shown in FIG.

FIG. 6 is a timing chart of each signal in FIG.

FIG. 7 is a block diagram of a conventional self-diagnosis circuit.

8 is a flowchart showing a program of a microcomputer of the conventional self-diagnosis circuit of FIG.

9 is a timing chart of each signal of the conventional self-diagnosis circuit of FIG.

[Explanation of symbols]

 1 Microcomputer 3 Display 4 Digit scan signal 6 Watchdog timer 7 Input signal 8 Watchdog timer output signal 9 Reset signal 11 Test switch 12 Diagnostic operation instruction signal 14 OR gate 15 Reset control signal

Claims (1)

[Claims] 1. A computer that outputs a signal corresponding to a normal state, a monitoring unit that detects an abnormality of the computer by monitoring the state of the signal, and generates an abnormal signal if the computer is in an abnormal state, and the monitoring unit. A test actuation unit of the means, a reset control signal generated based on the actuation of the test actuation unit, and the abnormality signal are input, and the reset control signal is not input, but when the abnormality signal is input, the computer A reset signal is output, and a gate that prohibits the output of the reset signal when both the reset control signal and the abnormal signal are input is provided, and the computer is brought into the normal state with the operation of the test operating unit. A self-diagnosis circuit, which stops the output of a corresponding signal and executes a predetermined display operation according to the presence or absence of the abnormal signal.