KR860003526Y1 - Crt terminal power saving circuit - Google Patents

Abstract

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Description

CTR terminal power saving circuit

Figure 1 is a schematic diagram of this paper.

2 is an exemplary circuit diagram of the present invention.

3 is a timing diagram of each part of the present invention.

* Explanation of symbols on the main parts of the drawings

1: signal detection unit 2: keyboard control unit

3: time delay unit 4: comparison unit

5: time control section 6: central control section

8: power display unit

This paper proposes a circuit which is intended to activate or deactivate a video signal input from a video controller to a monitor as a control signal of a central controller in accordance with the execution order of micro instructions by providing a power saving circuit and hardware according to the existing internal circuit of the CRT terminal. will be.

Conventionally, the power is applied even when the terminal is not used for a long time during data input operation or after the end of the operation in the CRT terminal, and thus power consumption is high. Or even when the monitor is not turned off after being small due to the nerves of the operator, the power consumption was considerable.

The present invention has been made in view of the above-described problems of the related art, which is intended to prevent unnecessary power consumption in the CRT terminal by adding a power saving circuit and a logic configuration according to the existing CRT terminal circuit.

This will be described in detail below.

1 is a schematic diagram of the present invention, which connects the time delay unit 3 between the output control signal line of the central control unit 6 and the keyboard control unit 2, and the output of the time delay unit 3 is connected to the comparison unit 4. do.

The output of the comparing section 4 is connected to the time counting section 5, which in turn applies an interrupt output to the central control section 6.

The output of the central control section 6 is applied to the power off display section 8 and the image adjusting section 7, while being applied to the time detection section 1 and has a system for controlling the time delay section 3.

The present invention of the system is realized through a specific embodiment as shown in Figure 2, which is an input unit keyboard 11, 2 is a keyboard control unit, 3 is a time delay unit consisting of a time delay circuit, 4 is a comparator such as an operational amplifier and the like. A comparator composed of the Oi gate 42, 5 is a chip configured together with the central controller 6 as a time controller, 7 is a conventional image controller, 1 is a signal detector composed of an AND gate (HD), 8 is It is a power display part made of transistor (TR) LED.

Reference numeral 9 denotes a clock generator, 10 denotes a known display logic, and 12 denotes a power supply.

In this configuration, the signal input into the terminal from the keyboard 11 of the input unit is inputted through the keyboard control unit 2 and the line 103 through the serial data line 101 and the AND gate of the signal detection unit 1. It is applied at once.

At this time, the end combination is output from the AND gate AD connected to the line 127 output from the central controller 6 and output to the line 105, and this signal is compared after the time delay is delayed in the time delay unit 3. It is applied to the comparator 41 of the section (4).

Here, the reason for delaying the time is that the operator tries to input data from the keyboard 11 and causes the central controller 6 to perform other tasks for a minimum period of time until the second key input. Lines 127 and 125 give an input condition to the AND gate AD as output logic L. In this case, when the keyboard 11 is input, the output line 105 stops the time controller 5 with logic L.

However, data is applied from the keyboard adjusting section 2 to the central control section 6 via the time delay section 3.

The central control unit 6 that senses this data activates the screen using the video signal and the active inactive control line 125 as logic H according to the micro-instruction order, and the AND output logic is H from the next key input. The time controller 5, which is a time counter, is driven.

In this case, if there is no known time delay unit 3, the signals entering the line 127 collide with each other, and thus a necessary configuration.

The signal input to the comparator 41 is compared with the input level of the comparison input 111 to generate an output signal at the corresponding output line.

In the comparator 41, outputs 113 are logic H, 115, and 117 are logic L for the two input conditions Va and Va '.

Therefore, when only one of these 113,117 output logics becomes the logic H, the timer of the time control section 5 is reset to drive the time control section 5.

However, as soon as power is applied to the terminal, a value previously set by the user or the producer is set in the time control unit 5, which is a time counting device, so that an interrupt pulse is provided to the central control unit 6 when the designated time is reached.

Accordingly, assuming that the logic of the output line 125 becomes L, the output of the image controller 7 is lost, and the screen of the monitor screen display part disappears, thereby eliminating power consumption.

In addition, the transistor TR of the power display unit 8 connected to the line 125 is turned OFF in the normally ON state to turn on the LED.

This interrupt pulse causes the central control unit 6 to deactivate line 125 according to the interrupt program of the internal microinstruction.

In addition, the transistor TR of the power display unit 8 connected to the line 125 is turned OFF from the usual ON state to turn on the LED.

In this state, when the key operation is performed, the signal is transmitted to the line 103 and the keyboard control unit 2 and input to the central control unit 6, whereby the central control unit 6 sets the line 125 to logic H.

This operation is described by a timing chart as shown in FIG. 3, where CK is a clock pulse, (a) is a detection signal of lines 101 and 103, (b) is a line 127, (c) is a line 105, (d) is a line 111, ( e) line 111 ', 115, (f) line 113, (g) line 117, (h) line 119, (i) line 121, (j) line 123, (k) line 125 , (l) illustrates the logic state of line 129.

In addition, t ₁ is the detection signal pulse width, t ₂ is the period from the first key input to the next key input, t ₃ is the time from the first key input to the screen off after all processes, and t ₄ is the first key input pulse delay period. , t _5, after the timer reset to the interrupt pulse occurs time, t ₆ of time the control unit 5 is a control time, t ₇ is a video signal-off period, such as after an interrupt pulse video monitor.

The present invention significantly improves the power consumption prevention and utilization of the device by providing a display function that automatically turns off and checks the image output of the CRT terminal when the operation after the power input is not continued for a predetermined period of time in the CRT terminal. There are beneficial features that have been made.

Claims (1)

In a CRT terminal having a keyboard 11 of an input unit, a monitor of an on-screen display unit, an image controller 7 and a central control unit 6, a signal detection unit of a keyboard adjusting unit 2 and an AND gate is connected to the input unit output. 1), and the output line of the comparator 4 and the central controller 6 through the time delay unit 3 to the output line thereof, and the output of the comparator 4 is the time controller 5 And the time control section 5 outputs to act as an interrupt input of the central control section 6, and the output of the central control section 6 is an image control section 7, a signal detection section 1, and a power display section 8 CRT terminal power saving circuit, characterized in that for connecting to control each.