JPH05100639A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To obtain a liquid crystal display device in which high-quality display is realized by simple CONSTITUTION:In driving by a line sequential system and a voltage averaging method by using a liquid crystal display panel of a simple matrix system where a picture element is constructed at an intersection between a scanning line electrode and a signal line electrode, a current flowing in a driving voltage generation circuit VG for driving the signal line electrode is detected and voltage corresponding to the detected current is fed back to the driving voltage generation circuit VG for driving the scanning line electrode. By generating correction voltage corresponding to the portion of crosstalk by the detection of the current and feeding it back to the driving voltage generation circuit VG side on the scanning line electrode side, the portion of crosstalk is cancelled in substance, so that the high-quality display which is not influenced by the crosstalk is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a technique effective for use in a liquid crystal display panel of a simple matrix type which is driven by a voltage averaging method.

[0002]

2. Description of the Related Art When a simple matrix type liquid crystal display panel is driven by a line-sequential type and a voltage averaging method, a selection / non-selection voltage applied to a scanning line electrode and a signal line electrode is
For example, it is a constant voltage as determined by the voltage averaging method as described in JP-A-54-2096.

[0003]

The simple matrix type liquid crystal display panel has a capacitance at the intersection of the scanning line electrode and the signal line electrode. Due to this capacitance and the output impedance of the driver that drives the scanning line electrodes and the signal line electrodes, crosstalk corresponding to the drive voltage sequentially applied to the signal line electrode side occurs on the non-selected scanning line electrode side. In the voltage averaging method, lighting / non-lighting of liquid crystal pixels is controlled by an effective voltage in a 1H period. Therefore, there is a problem that the effective voltage changes due to the above-mentioned crosstalk and uneven lightness / lighting unevenness and a ghost phenomenon occur. is there. Further, the capacitance has a large capacitance value when the pixel is in a lighting state, and the selection voltage waveform of the scanning line electrode is distorted at rising and falling, which also causes a change in the effective voltage. The inventor of the present application paid attention to the fact that the current supply by the crosstalk is performed from the drive voltage generation circuit side, and considered to detect the current change and substantially cancel the crosstalk. An object of the present invention is to provide a liquid crystal display device that realizes high quality display with a simple configuration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0004]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a driving voltage for driving the signal line electrodes in the line-sequential driving and the voltage averaging method using a simple matrix type liquid crystal display panel in which pixels are formed at the intersections of the scanning line electrodes and the signal line electrodes. The current flowing in the generating circuit is detected and the corresponding voltage is fed back to the drive voltage generating circuit that drives the scanning line electrodes.

[0005]

According to the above-mentioned means, a correction voltage commensurate with the crosstalk amount is generated by the above current detection and is fed back to the driving voltage generating circuit side on the scanning line electrode side to substantially cancel the crosstalk amount. Therefore, it is possible to realize high-quality display that is not affected by it.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a schematic block diagram of an embodiment of a liquid crystal display device according to the present invention. In the figure, three scanning line electrodes, three signal line electrodes, and a drive circuit corresponding thereto are illustrated as representatives. In the liquid crystal display panel, pixels shown as capacitors in the figure are formed at the intersections of the scanning line electrodes extending in the horizontal direction and the signal line electrodes extending in the vertical direction. In the figure, the capacitors surrounded by circles represent the lighting state.

The scanning line driving circuit receives a shift register SR which performs a shift operation in response to a clock pulse CL2 corresponding to a 1H period and a selection voltage VS1 formed by a driving voltage generating circuit VG in response to output signals S1 to S3 thereof. Switch circuits SW11 to SW that output to the corresponding scanning line electrodes
31 and an inverter circuit N for receiving the signals S1 to S3
1-N3 receives the inversion signal and the non-selection voltage VNS1 formed by the drive voltage generation circuit VG.
Circuits SW12 to SW3 for outputting the scanning lines to the scanning line electrodes
It consists of 2.

When the output signal S1 of the shift register SR is set to the selection level, the switch SW11 is turned on to output the scanning line drive voltage VX1 corresponding to the selection voltage VS1. At this time, the other scanning line drive voltages VX2, VX3
In accordance with the non-selection level of the output signals S2, S3 of the shift register SR, the switch circuits SW22, SW32 are turned on and set to the non-selection voltage VNS1. Since the shift register SR synchronizes with the clock pulse CL2 and sequentially shifts the selection level, the output signal S2 is set to the selection level instead of the output signal S1 at the next timing. As a result, by the switch control similar to the above, the scanning line drive voltages VX1 and VX3 are set to the non-selection voltage VNS1, and only the scanning line drive voltage VX2 is set to the selection voltage VS1. When the output signal S3 instead of the output signal S2 is set to the selection level by the shift operation of the shift register SR, the scanning line drive voltages VX1 and VX2 are set to the non-selection voltage VNS1 by the switch control similar to the above, and the scanning line Only the drive voltage VX3 is set to the selection voltage VS1. In this way, the scanning line electrodes are sequentially selected.

The pixel data Din is the clock pulse CL1.
And is serially input to the serial / Pasarelle conversion circuit SPC. The pixel signals of the signal line electrodes corresponding to one scanning line are serially input in the 1H period (within one cycle of the clock pulse CL2) in synchronization with the clock pulse CL1. The pixel signals for one scanning line captured serially in this way are latched in parallel in the latch circuits FF1 to FF3.
Transferred to.

The signal line drive circuit includes a serial / Pasarelle conversion circuit SPC as described above and latch circuits FF to FF3.
And a switch circuit S that receives the output signals D1 to D3 of the latch circuits FF1 to FF3 and outputs the selection voltage VS2 formed by the drive voltage generation circuit VG to the corresponding signal line electrodes.
A switch circuit SW that receives the inversion signal formed by W41 to SW61 and the inverter circuits N4 to N6 receiving the signals D1 to D3 and outputs the non-selection voltage VNS2 formed by the drive voltage generation circuit VG to the signal line electrode.
42 to SW62.

When the output signal D1 of the latch circuit FF1 is set to the lighting level, the switch SW41 is turned on to output the signal line drive voltage VY1 corresponding to the selection voltage VS2. At this time, the other signal line drive voltages VY2 and VY3
When the output signals D2 and D3 of the latch circuits FF2 and FF3 are at the non-lighting level, the switch circuits SW52 and SW62 are turned on and set to the non-selection voltage VNS2. If the output signals D2 and D3 are at the lighting level, the switch circuit SW5
1, SW61 is turned on and the selection voltage V
It is set to S2.

FIG. 3 is a waveform diagram for explaining an example of the display operation in the liquid crystal display device of FIG.
The scanning signals S1 to S3 are synchronized with the clock pulse CL2.
Are sequentially output from the shift register SR. As shown in FIG. 2, when the pixels marked with a circle are turned on and the other pixels are turned off, the output signals D1 to D3 of the latch circuits FF1 to FF3 are D3 at the timing of the scanning signal S1.
However, at the timing of the scanning signal S2, D2
At the timing of 3, D1 is set to the high level.

When the scanning signal S1 and the signal D3 are at the high level, the drive voltage VX1 becomes the selection voltage VS1 (1 and 0), and the drive voltage VY1 becomes the selection voltage VS2 [2 / a and (1
-2 / a)]. The drive voltages VX2 and VY2 or VX3 and VY1 in the other pixels which are turned on by the scanning signals S2 and S3 have the same voltage relationship as described above, and the pixels in the non-illuminated state have VX1 as shown by the scanning signals S2 and S3 in FIG.
Becomes a non-selection voltage VNS1 composed of a combination of 1 / a and 1-1 / a, and VY1 is 2 / a and 1-2 / a or 0 and 1
Is placed in a semi-lit or unlit state.

FIG. 1 is a circuit diagram of an embodiment of a drive voltage generating circuit according to the present invention. Power supply voltage VLC
D is divided by resistors R1, R, (a-4) and R and R2 to form six reference voltages such as Va to Vf serving as a reference. If the maximum voltage Va is 1, the voltage Vb is 1.
-1 / a, voltage Vc is 1-1 / a, and voltage Vd is 2 /
a is represented by Ve, 1 / a is represented by Ve, and 0 is represented by Vf. These ratios correspond to the selection voltage and the non-selection voltage shown in FIG.

The voltages Va and Vf are power-amplified through a voltage follower circuit VF1 and the like and output as a selection voltage VS1. That is, as shown in the above publication, Va and Vf are alternately output as the selection voltage VS1 through the switch circuit that is switched in synchronization with the clock pulse CL2. The voltages Vb and Ve are power-amplified through the voltage follower circuit VF3 and the like and alternately output as the non-selection voltage VNS1 through the switch circuit which is switched by the clock pulse CL2 in the same manner as above. Further, the voltages Va and Vf are power-amplified through the voltage follower circuit VF2 and the like, and alternately output as the selection voltage VS2 through the switch circuit which is switched by the clock pulse CL2 in the same manner as above. Voltage Vc and V
d is power-amplified through the voltage follower circuit VF4 and the like and is alternately output as the non-selection voltage VNS2 through the switch circuit which is switched by the clock pulse CL2 in the same manner as above.

In this embodiment, a small resistor R3 is inserted in series with the output terminal of the voltage follower circuit VF1 in order to detect the current due to crosstalk. This resistance R3
The voltage generated at both ends of the capacitor is amplified through the amplifier circuit VC1, and the AC component is converted into the resistors R4 and R through the capacitor C1.
It is added to the voltage Va by the adder circuit composed of 5 and supplied to the input of the voltage follower circuit VF2 corresponding to the selection voltage VS2. That is, the selection voltage V on the signal line electrode side
S2 is a voltage obtained by adding the feedback voltage to the voltage Va.

A small resistor R6 is inserted into the output terminal of the voltage follower circuit VF2, the voltage corresponding to the current flowing through the selected signal line electrode is amplified through the amplifier circuit VC2, and its AC component is passed through the capacitor C2 and the resistor R9. Is supplied to the input of. This resistor R9 is the resistor R7
Together with this, an adder circuit is configured to feed back the output voltage of the amplifier circuit VC2 to the voltage Vb corresponding to the non-selection voltage VNS2 on the scanning line electrode side. Similarly, a small resistor R8 is connected to the output terminal of the voltage follower circuit VF4 corresponding to the voltage Vc forming the non-selection voltage VNS2 on the signal line electrode side.
Is inserted, the voltage corresponding to the current flowing through the signal line electrode in the selected state is amplified through the amplifier circuit VC3, and its AC component is supplied to the input side of the resistor R9 that constitutes the above-mentioned adding circuit through the capacitor C3. That is, the crosstalk component detected in the non-selection voltage VNS2 on the signal line electrode side is fed back to the non-selection voltage VNS1 side on the scanning line electrode side.

In the above series resistance circuit, (a-4) R
Selection voltage V similar to the above, which is set to the negative side voltage with reference to
Also for S1 and VS2 and the non-selection voltages VNS1 and VNS2, the same current detection resistance and amplification circuit as the above-mentioned selection voltage on the positive side and the resistance addition circuit for feedback are provided. In the figure, the circuit elements are omitted because the respective resistance elements and the voltage follower circuit are configured symmetrically with the circuit on the positive side.

FIG. 4 is a waveform diagram for explaining the voltage correction operation in the liquid crystal display device according to the present invention. The scanning line electrodes X are selected once per frame, and the rest are maintained in a non-selected state. During this period, the potential of the signal line electrode Y changes due to the writing of pixel data corresponding to lighting / non-lighting corresponding to the other selected scanning line electrode, which causes crosstalk to the scanning line electrode on the non-selected side. I will end up. Since the liquid crystal display device is a passive element equivalently regarded as a capacitor, the voltage change due to the crosstalk is caused by the current supply from the drive voltage generation circuit.

With this in mind, for example, in the circuit of FIG. 1, the crosstalk component is detected from the change of the drive current when the selection voltage of the signal line electrode is supplied by the resistor R6, and it is amplified by the amplifier circuit VC2. , The AC component is fed back to the non-selection voltage VNS1 side on the scanning line electrode side. The resistance R
The resistance value of 6 and the gain of the amplifier circuit VC2 and the resistance values of the resistors R9 and R7 forming the resistance addition circuit are adjusted appropriately,
The non-selection level of the scanning line electrodes is changed so as to cancel out the crosstalk amount in FIG.

Further, when the scanning line electrode side is set to the selected state, when the pixel is in the lighting state, the capacitance value increases and the rising and falling waveforms are blunted. The voltage corresponding to this waveform rounding is detected by the resistor R3, and the detected voltage is amplified by the amplifier circuit V.
It is amplified by C1 and fed back to the selection voltage VS2 on the signal line side through the capacitor C1 and the resistor R4. As a result, the voltage on the signal line electrode side in the lighted state is adjusted, and control is performed so as to suppress fluctuations in the effective voltage due to rounding of the rising and falling waveforms on the scanning line electrode side. In this manner, the crosstalk component shown in FIG. 4 and the dullness of the driving voltage due to the change of the capacitance value of the liquid crystal pixel are substantially canceled out, and a high quality display operation can be performed.

In FIG. 1, reference voltages Va to Vf are used.
In the resistance circuit forming a, a is a constant determined according to the optimum driving condition. In the series resistance circuit,
The resistor R2 may be omitted and the ground potential may be set to the reference potential 0.

The operational effects obtained from the above embodiment are as follows. That is, (1) by using a simple matrix type liquid crystal display panel in which pixels are formed at the intersections of the scanning line electrodes and the signal line electrodes, the signal line electrodes are driven in the line sequential method and the voltage averaging method. By detecting the current flowing in the drive voltage generating circuit and feeding back the voltage corresponding to it to the drive voltage generating circuit that drives the scanning line electrodes,
Since the amount of crosstalk can be substantially canceled out, it is possible to obtain a high quality display that is not affected by it. (2) Increase the contrast of lighting / non-lighting by detecting the rounding of the scanning line selection voltage due to lighting / non-lighting of the liquid crystal and changing the driving voltage on the signal line electrode side accordingly. The effect that can be obtained is obtained. (3) The effect that high quality display can be achieved is achieved only by adding a simple circuit such as a resistor and an amplifier circuit for current detection, a coupling capacitor and a resistor addition circuit.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the driving voltage of the scanning line electrode and the signal line electrode is set by combining the above-described six types of voltages, and the liquid crystal pixels of the simple matrix configuration are selectively turned on / off by the voltage averaging method. Anything that can be controlled to When performing color display, a color filter may be formed corresponding to the signal line electrode and pixel data corresponding to the color filter may be input. INDUSTRIAL APPLICABILITY The present invention can be widely used for a liquid crystal display device driven by a line-sequential method and a voltage averaging method using a simple matrix type liquid crystal display panel.

[0025]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a driving voltage for driving the signal line electrodes in the line-sequential driving and the voltage averaging method using a simple matrix type liquid crystal display panel in which pixels are formed at the intersections of the scanning line electrodes and the signal line electrodes. By detecting the current flowing in the generation circuit and feeding back the corresponding voltage to the drive voltage generation circuit that drives the scan line electrodes, it is possible to substantially cancel out the crosstalk, so that high quality display that is not affected by it can be obtained. realizable.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a drive voltage generating circuit according to the present invention.

FIG. 2 is a schematic block diagram showing an embodiment of a liquid crystal display device according to the present invention.

FIG. 3 is a waveform diagram for explaining an example of the operation of the liquid crystal display device of FIG.

FIG. 4 is a waveform diagram of a drive voltage for explaining the present invention.

[Explanation of symbols]

VF1 to VF4 ... Voltage follower circuit, VC1 to V
C3 ... Amplifying circuit, C1 to C3 ... Capacitors, R, R1
R9 ... resistor, N1-N6 ... inverter circuit, SW11-
SW62 ... switch circuit, VG ... drive voltage generating circuit, C
R ... Shift register, SPC ... Serial / parallel conversion circuit, FF1 to FF3 ... Latch circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hitoshi Suzuki, 3300 Hayano, Mobara-shi, Chiba, Hitachi, Ltd. Mobara factory (72) Inventor Takayuki Iura, 3300, Hayano, Mobara-shi, Chiba, Hitachi Ltd., Mobara, Hitachi, Ltd.

Claims (1)

[Claims] 1. A simple matrix type liquid crystal display panel in which a pixel is formed at an intersection of a scanning line electrode and a signal line electrode, and a current flowing in a drive voltage generating circuit for driving the signal line electrode or the scanning line electrode is detected. And a voltage correction circuit for feeding back a voltage corresponding thereto to a drive voltage generation circuit for driving the scanning line electrodes or the signal line electrodes.