JPH0499061A - Gate array type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To appoint reliably the position of a specified flip-flop as the position of a flip-flop which is required for test circuit use can be appointed by a method wherein circuit elements for flip-flop constituting a shift register, which is used for a functional test, of a scanning system are arranged at previously appointed positions, such as in an array type. CONSTITUTION:A gate array type semiconductor integrated circuit is constituted of a chip 1, a group 2 of external pads, which are arranged on the periphery of the chip 1 and are used for signal input/output and power supply, four lines of flip-flop-only cell arrays 11 to 14, which respectively consist of 10 rows of flip-flop-only cells, and 6 lines of logical circuit cell arrays 21 to 26, which respectively consist of 10 rows of logical circuits and the like. The cell arrays 11 to 14 constitute a shift register, which is used for a test circuit, of a scanning system. As the arrays 11 to 14 are respectively arranged at a previously appointed position, that is, in a linear form and the position of a flip-flop which is required for test circuit use can be appointed, the position of a specified flip-flop in the shift register can be reliably appointed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a gate array type semiconductor integrated circuit.

[Conventional technology]

In a gate array type semiconductor integrated circuit, logic circuit cells and wiring regions are alternately arranged in an array over the entire semiconductor chip.

The arrangement of transistor elements and resistance elements in logic circuit cells in each array arrangement and the number of transistor elements accommodated therein are the same, and various functional blocks are realized by wiring within the cells.

This type of gate array type semiconductor integrated circuit is generally
Perform functional tests using a well-known scanning method. For this purpose, a shift register composed of flip-flops has been formed inside the device as part of a test circuit.

FIG. 3 shows an example of the arrangement of flip-flops constituting a shift register for a test circuit using a scan method in a conventional gate array semiconductor device circuit.

In FIG. 3, a shift register for a test circuit of a conventional gate array type semiconductor integrated circuit has a flip 7 placed on a chip 1 by automatic wiring using a router.
It consisted of 0 knobs FFI to FF7.

These flip-flops are originally for general use in logic circuits, and are not specifically provided for use in test circuits.

Therefore, depending on the type of gate array type semiconductor integrated circuit, a circuit such as a shift register for testing is constructed by combining circuit elements not used in the original logic circuit design, that is, surplus circuit elements.

[Problem to be solved by the invention]

In the conventional gate array type semiconductor integrated circuit described above,
Since identical logic circuit cells are arranged in an array,
There are no circuit elements specifically dedicated to the test circuit. Therefore, for each product type, circuit elements such as shift registers for testing are constructed by combining circuit elements that were not used in the original logic circuit design, that is, surplus circuit elements. The disadvantage was that the arrangement differed depending on the variety.

As a result, for example, where each of the flip-flops that make up a series of shift registers is located is
The drawback was that it was impossible to predict until the automatic wiring results from the router were seen.

Therefore, in the scan method test which is a general test method, when a defective element is found, it is extremely difficult to analyze which element is defective.

[Means to solve the problem]

The gate array type semiconductor integrated circuit of the present invention includes circuit elements for logic circuits arranged in an array, and circuit elements dedicated to flip-flops constituting a shift register for functional testing using a scan method, and dedicated to the flip-flops. The circuit element is arranged at a predetermined position, and has a wiring path between the flip-flop dedicated circuit elements close to the flip-flop dedicated circuit element.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a chip layout diagram showing one embodiment of the present invention.

Referring to FIG. 1, the gate array type semiconductor integrated circuit of the present invention has a chip 1, a group of external pads 2 arranged around the chip 1 for signal input/output and power supply, and 10 rows of flip-flops each. 4 rows of flip-flop dedicated cell arrays 11 to 14 each consisting of cells, and 6 rows of logic circuit cell arrays 21 to 26 each consisting of 10 columns of cells such as logic circuits.
It is composed of.

The flip-flop dedicated cell arrays 11 to 14 are for configuring a shift register for a scan type test circuit.

In this embodiment, the flip 70 tube dedicated cell array 11 to
14 are arranged in a predetermined position, that is, in a straight line as shown in FIG. can be determined, and therefore the wiring route (hereinafter referred to as scan path) of the test circuit is simplified.

Furthermore, by setting the area of the scan path as a prohibited area for other automatic wiring, other wiring can be done regardless of the scan path.

FIG. 2 is a detailed diagram of the flip-flop dedicated cell array 11 of this embodiment shown in FIG. 1 and wiring areas such as scan paths.

In FIG. 2, a flip-flop dedicated cell array 11
The flip-flop FFII constitutes the.

FF12. FF13. . . , a dedicated scan path channel 111, and a wiring area 112 for other logic circuits and the like.

Each flip-flop FFI 1. FF12. FF13.
..., wiring for test signal input/output, that is, wiring from the input terminal to SI and from So to the output terminal, is formed by a metallized pattern.

Further, the scan path dedicated channel 111 is arranged as close as possible to the flip-flop dedicated cell array 11.

Furthermore, the area of the scan path dedicated channel 111 is
This area is set as an area where automatic wiring is prohibited for the wiring area 112 of other logic circuits, etc.

Depending on the type of gate array type semiconductor integrated circuit, not all of the prepared flip-flop dedicated cells are necessarily used. In this case, it goes without saying that the test circuit can be configured without any problem by not connecting the wiring of the scan path in order to skip the unused seven lip-flops.

Although the present invention has been described in detail above, the present invention is not limited to the above embodiments and can be modified in various ways.

For example, although the number of rows and columns of cells such as logic circuits is set to 10 each, it is of course possible to use 100 each without departing from the gist of the present invention.

〔Effect of the invention〕

As explained above, the present invention arranges flip-flop circuit elements constituting a shift register for a scan-type functional test at predetermined positions, for example, in an array, so that the flip-flop circuit elements necessary for the test circuit can be Since the position of the flip-flop can be specified, there is an effect that the position of a specific flip-flop in the shift register can be determined.

Therefore, the wiring path of the test circuit is simplified.
This has the effect of facilitating analysis in the event of a test circuit failure.

Further, by setting the area of the wiring route of the test circuit as a prohibited area for other automatic wiring, other wiring can be done regardless of the wiring route of the test circuit, and there is an effect that wiring can be performed efficiently.

[Brief explanation of the drawing]

FIG. 1 is a chip layout diagram showing an embodiment of the present invention;
FIG. 2 is a detailed diagram of the flip-flop dedicated cell array and wiring areas such as scan paths in the embodiment shown in FIG. It is a figure showing an example of arrangement. 1... Chip, 2... External pad group, 11-14.
・・Flip-flop dedicated cell array, 21-26・・
- Logic circuit cell array, 111... channel dedicated to scan path, 112... wiring area for other logic circuits, etc.

Claims (1)

[Scope of Claims] 1. A circuit element for a logic circuit arranged in an array and a circuit element dedicated to a flip-flop constituting a shift register for functional testing using a scanning method, the circuit element dedicated to a flip-flop comprising: A gate array type semiconductor integrated circuit, comprising: a wiring path between the flip-flop dedicated circuit elements arranged at a predetermined position and close to the flip-flop dedicated circuit element. 2. The gate array type semiconductor according to claim 1, wherein the flip-flop dedicated circuit elements are arranged in an array, and the wiring route prohibits wiring other than wiring between the flip-flop dedicated circuit elements. integrated circuit.